JPH1131640A - Method for manufacturing stuck soi substrate - Google Patents

Method for manufacturing stuck soi substrate

Info

Publication number
JPH1131640A
JPH1131640A JP18621797A JP18621797A JPH1131640A JP H1131640 A JPH1131640 A JP H1131640A JP 18621797 A JP18621797 A JP 18621797A JP 18621797 A JP18621797 A JP 18621797A JP H1131640 A JPH1131640 A JP H1131640A
Authority
JP
Japan
Prior art keywords
substrate
polishing
crystal silicon
silicon layer
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18621797A
Other languages
Japanese (ja)
Inventor
Yasunori Okubo
安教 大久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP18621797A priority Critical patent/JPH1131640A/en
Publication of JPH1131640A publication Critical patent/JPH1131640A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To make a substrate flat by polishing a single-crystalline silicon layer on an insulation film to a first predetermined thickness and dry-etching it to a second predetermined thickness and then polishing it until the insulation film is exposed. SOLUTION: A single-crystalline silicon layer 32 is ground to a thickness of 3-5 μm ±0.5 μm, for example and then is etched by dry etching to a thickness of 0.5-1.0 μm. Next, the whole surface of the single crystal silicon layer 32 is polished at the same time by a selective polishing method with the use of an insulation film 34 as a stopper, until the convex insulation film 34 is exposed and polishing is stopped, when the single crystal silicon layer 32 is polished to the top surface of the insulation film 34. A thin film SOI(silicon-on-insulator) structure having the single-crystalline silicon layer 32 formed into island shape on the insulation film 34 is formed in this manner. Since the amount of polishing is extremely small, unevenness in polishing and hence polishing variation are hardly produced and even if the unevenness in polishing is produced, the polishing variation is small and hence the substrate can be plavarized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、貼り合わせSOI
基板の作製方法に関し、更に詳細には、研磨むらによる
基板面の凹凸の発生を抑制して、基板全面にわたり平面
性が良好で平坦な面を備えた貼り合わせSOI基板を高
い生産性で作製する方法に関するものである。
TECHNICAL FIELD The present invention relates to a bonded SOI
More specifically, the method for manufacturing a substrate suppresses the occurrence of unevenness on the substrate surface due to uneven polishing, and manufactures a bonded SOI substrate having good flatness and a flat surface over the entire surface of the substrate with high productivity. It is about the method.

【0002】[0002]

【従来の技術】SOI(Silicon On Insulator)構造
は、絶縁膜上に単結晶シリコン層を有する構造で、絶縁
膜により完全な素子間分離ができ、かつ接合容量や配線
容量を低減できるので、高密度化され、高速動作性の優
れた集積回路素子、或いは優れた特性を示す光機能素子
の製作に好都合であると言われている。本明細書でいう
SOI基板とは、SOI構造を備えた基板、即ち図3に
示すように、支持基板20上の絶縁層22の凹部に島状
に形成された薄膜単結晶シリコン層24を有するものを
SOI基板26と言う。また、SOI構造は、図3の左
手に示すように、絶縁層22上に細い櫛歯状に形成され
た単結晶シリコン層28の場合もある。
2. Description of the Related Art An SOI (Silicon On Insulator) structure is a structure having a single crystal silicon layer on an insulating film. The insulating film enables complete isolation between elements and reduces junction capacitance and wiring capacitance. It is said that it is convenient for manufacturing an integrated circuit element having a high density and excellent high-speed operation or an optical functional element exhibiting excellent characteristics. As used herein, the term “SOI substrate” refers to a substrate having an SOI structure, that is, as shown in FIG. 3, a thin-film single-crystal silicon layer 24 formed in an island shape in a concave portion of an insulating layer 22 on a supporting substrate 20. This is called an SOI substrate 26. The SOI structure may be a single-crystal silicon layer 28 formed in a thin comb shape on the insulating layer 22, as shown on the left side of FIG.

【0003】SOI基板は種々の方法により製作するこ
とができるが、その中で、貼り合わせ方式によるSOI
基板の作製は、最も良好な結晶性の単結晶シリコン層を
有するSOI基板を作製でき、その基板から優れた特性
の素子を形成できる方法であると評価され、開発が進ん
でいる。ここで、図4を参照して、従来の貼り合わせS
OI基板の作製方法を説明する。図4(a)から(e)
は、それぞれ、貼り合わせSOI基板の作製工程毎の基
板断面図である。表面が鏡面に仕上げられた単結晶シリ
コンウエハからなる素子形成基板10の表面にフォトリ
ソグラフィ技術により所定パターンに従って複数個の凹
部12を、図4(a)に示すように、形成する。次い
で、凹部12の全面にSiO2 膜等の絶縁膜14を成膜
する。次いで、図4(b)に示すように、SiO2 膜1
4上全面に別の層、例えば多結晶シリコン層16を成膜
して凹部12を埋め、その多結晶シリコン層16の表面
を平坦化する。多結晶シリコン層に代えて別の組成の
層、例えば絶縁膜でも良い。次に、図4(c)に示すよ
うに、平坦化した多結晶シリコン層16上に鏡面化され
たシリコンからなる支持基板18を面接触させて素子形
成基板10に貼り合わせ、基板10と基板18とを合体
する。次いで、図4(d)に示すように、貼り合わせた
素子形成基板10を必要なSOI層の層厚+3〜5μm
の層厚になるまで研削する。ここで、必要なSOI層の
層厚とは、島状に形成されるSOI構造の単結晶シリコ
ン層の厚さを言う。研削するには、例えば図5に示すよ
うな研削装置52を使用する。研削装置52は、図5に
示すように、下面にレジンボンド(ダイヤモンドとレン
ジを混合して固めた砥石)56を有し、回転軸回りに回
転するともに昇降自在なレジン砥石54と、基板Wを保
持して回転軸回りに回転する回転ウエハホルダ58とか
ら構成されている。研削に当たっては、回転ウエハホル
ダ58に基板10を真空吸着して上向けに保持し、レジ
ン砥石54を回転させつつ基板W上に押圧して、レジン
ボンド56で基板10を研削する。更に、図4(e)に
示すように、SiO2 膜14が露出して、必要なSOI
構造を形成できるまで、基板10を研磨して、貼り合わ
せSOI基板19を形成する。研磨するには、回転ウエ
ハホルダに基板10を真空吸着させて保持し、回転研磨
パッド上に研磨剤を供給しながら回転ウエハホルダによ
り保持した基板10を回転させつつ押圧して研磨する。
[0003] SOI substrates can be manufactured by various methods.
The production of a substrate is evaluated as a method capable of producing an SOI substrate having a single crystal silicon layer having the best crystallinity and forming an element having excellent characteristics from the substrate, and development is proceeding. Here, with reference to FIG.
A method for manufacturing an OI substrate will be described. 4 (a) to 4 (e)
[FIG. 2] is a cross-sectional view of a substrate in each manufacturing step of a bonded SOI substrate. As shown in FIG. 4A, a plurality of recesses 12 are formed on the surface of an element forming substrate 10 made of a single crystal silicon wafer having a mirror-finished surface according to a predetermined pattern by a photolithography technique. Next, an insulating film 14 such as a SiO 2 film is formed on the entire surface of the concave portion 12. Then, as shown in FIG. 4 (b), SiO 2 film 1
4, another layer, for example, a polycrystalline silicon layer 16 is formed to fill the recess 12, and the surface of the polycrystalline silicon layer 16 is flattened. Instead of the polycrystalline silicon layer, a layer having another composition, for example, an insulating film may be used. Next, as shown in FIG. 4C, a support substrate 18 made of mirror-finished silicon is brought into surface contact with the flattened polycrystalline silicon layer 16 and bonded to the element formation substrate 10, and the substrate 10 and the substrate And 18 are combined. Next, as shown in FIG. 4D, the bonded element forming substrate 10 is formed into a layer thickness of a required SOI layer + 3 to 5 μm.
Grind to a layer thickness of. Here, the necessary thickness of the SOI layer refers to the thickness of a single-crystal silicon layer having an SOI structure formed in an island shape. For grinding, for example, a grinding device 52 as shown in FIG. 5 is used. As shown in FIG. 5, the grinding device 52 has a resin bond (grinding stone obtained by mixing diamond and a range) 56 on the lower surface. And a rotating wafer holder 58 that rotates around a rotation axis while holding the rotating shaft. In the grinding, the substrate 10 is vacuum-adsorbed to the rotating wafer holder 58 and held upward, and the resin grindstone 54 is pressed against the substrate W while rotating, and the substrate 10 is ground by the resin bond 56. Further, as shown in FIG. 4E, the SiO 2 film 14 is exposed and necessary SOI
Until the structure can be formed, the substrate 10 is polished to form a bonded SOI substrate 19. In order to polish, the substrate 10 is vacuum-adsorbed and held on the rotating wafer holder, and the substrate 10 held by the rotating wafer holder is pressed while rotating while polishing is supplied onto the rotating polishing pad.

【0004】貼り合わせ方式によりSOI基板を作製す
る際、研磨加工は次の二つの理由から必要であるとされ
ている。第1には、研削加工の過程では、どうしても3
〜5μm 程度の研削ダメージが研削面に生じる。例え
ば、ダイヤモンド砥粒の鋭い角が研削面に当接して、大
きな傷或いは深い切れ込みが基板10の研削面に生じ
る。そのために、研磨加工を行って、研削ダメージを除
去する必要がある。第2には、研削加工のみでは粗削り
になってSOI構造の面の平面化、平坦化及び平滑化が
不足するために、仕上げ加工として研磨加工を行う必要
がある。従って、研磨加工では、図4に示す貼り合わせ
SOI基板19に島状に形成されたSiO2 膜14の凹
部の単結晶シリコン薄層10の上面と周辺のSiO2
14の上面とが同一平面上にあって、しかも平坦でかつ
研磨ダメージが生じないようにすることが最も重要であ
る。なお、本明細書で言う平面化とは、単結晶シリコン
薄層10の上面と周辺のSiO2 膜14の上面とを同一
平面上にあるようにすること言う。換言すれば、従来の
貼り合わせSOI基板の作製方法では、SOI層の層厚
が必要なSOI層の層厚+3〜5μmになった時点で研
削加工を停止し、研削加工で生じた3〜5μmの研削ダ
メージが生じており、かつ平坦性にバラツキのある研削
面を研磨して、取り代バラツキ±10%の研磨により平
坦で平滑なSOI層を得ている。
When fabricating an SOI substrate by a bonding method, it is said that polishing is necessary for the following two reasons. First, in the process of grinding, 3
Grinding damage of about 5 μm occurs on the ground surface. For example, the sharp corners of the diamond abrasive grains come into contact with the ground surface, causing large scratches or deep cuts on the ground surface of the substrate 10. Therefore, it is necessary to remove the grinding damage by performing polishing. Secondly, since only the grinding process results in rough cutting, and the planarization, flattening and smoothing of the surface of the SOI structure are insufficient, it is necessary to perform polishing as a finishing process. Therefore, in the polishing, the upper surface and the same plane of the SiO 2 film 14 upper surface and the surrounding single crystal silicon thin layer 10 of the recess of the SiO 2 film 14 formed in an island shape on the SOI substrate 19 bonded 4 It is of the utmost importance that it is on top and flat and free of polishing damage. The term “planarization” in this specification means that the upper surface of the single-crystal silicon thin layer 10 and the upper surface of the peripheral SiO 2 film 14 are on the same plane. In other words, in the conventional method for manufacturing a bonded SOI substrate, the grinding process is stopped when the thickness of the SOI layer reaches the required layer thickness of the SOI layer + 3 to 5 μm, and 3 to 5 μm generated by the grinding process. Then, the ground surface which has been subjected to grinding damage and has unevenness in flatness is polished, and a flat and smooth SOI layer is obtained by polishing with a variation of a margin of ± 10%.

【0005】[0005]

【発明が解決しようとする課題】しかし、上述した従来
の貼り合わせSOI基板の作製方法では、たとえ研削工
程で研削ダメージがあるものの平坦化された研削面を有
する単結晶シリコン層が得られたとしても、次の研磨工
程で、3〜5μm の厚さの単結晶シリコン層を研磨する
ために、どうしても研磨する単結晶シリコン層に比例す
る大きさの研磨むらが生じて、研磨面に面内バラツキが
生じる。そのために、単結晶シリコン層の膜厚分布に面
内バラツキが生じ、基板全面にわたり均一な膜厚のSO
I構造を得ることが難しかった。
However, in the above-mentioned conventional method for manufacturing a bonded SOI substrate, even if a single-crystal silicon layer having a flattened ground surface is obtained even though grinding damage is caused in the grinding process. However, in the next polishing step, since the single-crystal silicon layer having a thickness of 3 to 5 μm is polished, polishing unevenness inevitably occurs in a size proportional to the single-crystal silicon layer to be polished. Occurs. As a result, in-plane variation occurs in the thickness distribution of the single-crystal silicon layer, and the SO
It was difficult to obtain an I structure.

【0006】従来の貼り合わせSOI基板の作製方法で
生じる研磨むらの問題を解決する方法として、特開平9
−102540号公報で開示された方法、或いはPAC
E法(Plasma Assisted Chemical Etching) が提案され
ている。しかし、前掲公報の方法及びPACE法とも、
基板の被研磨面を走査して凸部を検出し、そこをプラズ
マ・エッチング或いは研磨加工等により局所的に凸部を
除去して平面化する方法である。従って、基板面を走査
して凸部を検出し、検出した凸部を除去して平面化する
ために、走査と除去加工に時間を要する。その結果、生
産性の向上が難しいという問題があった。また、走査装
置及びその制御装置を必要とするために、加工装置が大
がかりになり、コストが嵩むという問題もあった。
As a method for solving the problem of uneven polishing caused by the conventional method for manufacturing a bonded SOI substrate, Japanese Patent Application Laid-Open No.
-102540, the method disclosed in
The E method (Plasma Assisted Chemical Etching) has been proposed. However, both the method of the above-mentioned publication and the PACE method,
In this method, a surface to be polished is scanned to detect a convex portion, and the convex portion is locally removed by plasma etching or polishing to flatten the surface. Therefore, it takes time for scanning and removing processing to scan the substrate surface to detect the convex portion and remove the detected convex portion to make the surface flat. As a result, there is a problem that it is difficult to improve productivity. Further, since a scanning device and a control device for the scanning device are required, there is a problem that the processing device becomes large-scale and the cost increases.

【0007】そこで、本発明の目的は、従来の方法に比
べて、更に平坦化された、平面化された基板面を有する
SOI層を備えたSOI基板を貼り合わせ方式により作
製する方法を提供することである。
Accordingly, an object of the present invention is to provide a method for manufacturing an SOI substrate having an SOI layer having a flattened substrate surface, which is further flattened as compared with the conventional method, by a bonding method. That is.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係る貼り合わせSOI基板の作製方法は、
単結晶シリコン基板をパターニングして所定パターンの
凹部を単結晶シリコン基板面に形成し、凹部壁及び基板
面に沿って絶縁膜を成膜し、更に別の層を基板全面に成
膜して上面を平坦化し、平坦化した上面を別の支持基板
上に面接触させるようにして単結晶シリコン基板と別の
支持基板とを貼り合わせて合体し、次いで絶縁膜を露出
させるまで単結晶シリコン基板を研削して、支持基板上
に薄膜SOI構造を備えたSOI基板を作製する方法に
おいて、薄膜SOI構造を形成する絶縁膜上の単結晶シ
リコン層の厚さが第1の所定厚さになるまで、単結晶シ
リコン層を研削する研削工程と、次いで、単結晶シリコ
ン層の厚さが第2の所定厚さになるまで、ドライエッチ
ングにより単結晶シリコン層をエッチングする工程と、
次いで、絶縁膜を露出させるまで単結晶シリコン層を研
磨する仕上げ工程とを有することを特徴としている。
In order to achieve the above object, a method for manufacturing a bonded SOI substrate according to the present invention comprises:
The single crystal silicon substrate is patterned to form a concave portion of a predetermined pattern on the surface of the single crystal silicon substrate, an insulating film is formed along the concave wall and the substrate surface, and another layer is formed on the entire surface of the substrate. The single crystal silicon substrate and another support substrate are bonded together so that the flattened upper surface is in surface contact with another support substrate, and then the single crystal silicon substrate is exposed until the insulating film is exposed. Grinding to produce an SOI substrate provided with a thin film SOI structure on a supporting substrate, wherein the thickness of the single crystal silicon layer on the insulating film forming the thin film SOI structure becomes a first predetermined thickness. A grinding step of grinding the single-crystal silicon layer, and then a step of etching the single-crystal silicon layer by dry etching until the thickness of the single-crystal silicon layer reaches a second predetermined thickness;
Then, a finishing step of polishing the single crystal silicon layer until the insulating film is exposed.

【0009】薄膜単結晶シリコン層の厚さが0.03〜
0.1μm で、絶縁膜の厚さが400〜800nm程度
のSOI構造では、第1の所定厚さ及び第2の所定厚さ
は、実際的には、それぞれ、3〜5μm 及び0.5〜
1.0μm で良い。研削工程及びエッチング工程で適用
する研削方法及びドライエッチング方法は、それぞれ、
既知の研削方法及びエッチング方法でよい。仕上げ工程
で適用する研磨方法は、既知の研磨方法であって、CM
P法及びその他一般に使用されている方法である。好適
には、仕上げ工程では、絶縁膜を研磨ストッパとして単
結晶シリコン層を研磨する選択研磨法により研磨する。
When the thickness of the thin film single crystal silicon layer is 0.03-
In an SOI structure having a thickness of 0.1 μm and an insulating film thickness of about 400 to 800 nm, the first predetermined thickness and the second predetermined thickness are actually 3 to 5 μm and 0.5 to 0.5 μm, respectively.
1.0 μm may be sufficient. The grinding method and the dry etching method applied in the grinding step and the etching step are, respectively,
A known grinding method and etching method may be used. The polishing method applied in the finishing step is a known polishing method,
The P method and other commonly used methods. Preferably, in the finishing step, polishing is performed by a selective polishing method for polishing a single crystal silicon layer using the insulating film as a polishing stopper.

【0010】[0010]

【発明の実施の形態】以下に、実施形態例を挙げ、添付
図面を参照して、本発明の実施の形態を具体的かつ詳細
に説明する。実施形態例1 本実施形態例は、本発明に係る貼り合わせSOI基板の
作製方法の実施の形態の一つの例であって、図1(a)
から(c)は、それぞれ、本実施形態例の各工程の基板
断面図である。先ず、従来の方法と同様にして、図4
(c)に示すように、素子形成基板上の平坦化した多結
晶シリコン層にシリコンからなる支持基板を面接触させ
て素子形成基板に貼り合わせ、素子形成基板と支持基板
とを合体した貼り合わせ基板30を作製する。貼り合わ
せ基板30は、図1(a)に示すように、上から順に言
って、単結晶シリコン層32と、絶縁膜34と、多結晶
シリコン層36と、シリコンの支持基板38とから構成
されている。絶縁膜34の膜厚は600nm、絶縁膜3
4の凹部の深さは0.03〜0.1μm である。先ず、
貼り合わせ基板30の単結晶シリコン層32を既知の研
削方法により研削する。研削工程では、図1(a)に示
すように、単結晶シリコン層の厚さが3〜5μm ±0.
5μmの厚さまで単結晶シリコン層32を研削加工す
る。ここで、単結晶シリコン層の厚さとは、凹部40の
SiO2 膜34の上面から単結晶シリコン層32上面ま
での厚さを言う。
Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment 1 This embodiment is an example of an embodiment of a method for manufacturing a bonded SOI substrate according to the present invention, and FIG.
FIGS. 3A to 3C are cross-sectional views of the substrate in each step of the embodiment. First, as shown in FIG.
As shown in (c), a support substrate made of silicon is brought into surface contact with the flattened polycrystalline silicon layer on the element formation substrate and bonded to the element formation substrate, and the element formation substrate and the support substrate are combined. The substrate 30 is manufactured. As shown in FIG. 1A, the bonded substrate 30 is composed of, in order from the top, a single-crystal silicon layer 32, an insulating film 34, a polycrystalline silicon layer 36, and a silicon support substrate 38. ing. The thickness of the insulating film 34 is 600 nm,
4 has a depth of 0.03 to 0.1 μm. First,
The single crystal silicon layer 32 of the bonded substrate 30 is ground by a known grinding method. In the grinding step, as shown in FIG. 1A, the thickness of the single-crystal silicon layer is 3 to 5 μm ± 0.
The single crystal silicon layer 32 is ground to a thickness of 5 μm. Here, the thickness of the single crystal silicon layer refers to the thickness from the upper surface of the SiO 2 film 34 in the recess 40 to the upper surface of the single crystal silicon layer 32.

【0011】次いで、図1(b)に示すように、単結晶
シリコン層の厚さが0.5〜1.0μm残るように、単
結晶シリコン層32をドライエッチングによりエッチン
グする。ドライエッチングの方法は、プラズマエッチン
グ法、RIE法等により行う。エッチングする際、エッ
チング時間はエッチングレートから逆算して処理時間を
設定しておく。次いで、絶縁膜34をストッパにして選
択研磨法により凸状の絶縁膜34が露出するまで、単結
晶シリコン層32を研磨し、図1(c)に示すように、
絶縁膜34上に島状に形成された単結晶シリコン層を有
する薄膜SOI構造を形成する。これにより、SOI基
板39を得ることができる。本実施形態例では、研磨工
程で研磨すべき単結晶シリコン層の厚さが0.5〜1.
0μm であって、従来の方法に比べて研磨量が格段に少
ないため、研磨むら、従って研磨バラツキが生じ難く、
また生じてもバラツキ量が小さく、従来の基板に比べ
て、遙に良好に平面化、平坦化及び平滑化されたSOI
構造を備えた基板を提供することができる。また、本実
施形態例は、単結晶シリコン層の研磨面を全面同時に研
磨しているので、研磨面の凸部を局所的に除去する方法
に比べて、研磨に要する時間が短いので生産性が高く、
しかも装置コスト及び研削コストが低い。また、オーバ
ー研磨によるディシングを抑制でき、SOI層バラツキ
の低減によりSOI構造の薄膜化にとって格段に有利に
なる。
Next, as shown in FIG. 1B, the single crystal silicon layer 32 is etched by dry etching so that the thickness of the single crystal silicon layer remains 0.5 to 1.0 μm. Dry etching is performed by a plasma etching method, an RIE method, or the like. At the time of etching, the processing time is set in advance by calculating the etching time backward from the etching rate. Next, the single crystal silicon layer 32 is polished by the selective polishing method using the insulating film 34 as a stopper until the convex insulating film 34 is exposed, as shown in FIG.
A thin film SOI structure having a single crystal silicon layer formed in an island shape on the insulating film is formed. Thus, an SOI substrate 39 can be obtained. In this embodiment, the thickness of the single-crystal silicon layer to be polished in the polishing step is 0.5 to 1.
0 μm, and the polishing amount is much smaller than that of the conventional method, so that polishing unevenness and therefore polishing variation hardly occur.
Also, even if it occurs, the variation amount is small, and the planarization, flattening and smoothing SOI are much better than those of the conventional substrate.
A substrate with a structure can be provided. Further, in the present embodiment, since the entire polished surface of the single-crystal silicon layer is simultaneously polished, the time required for polishing is shorter than in the method of locally removing the projections of the polished surface, so that the productivity is reduced. high,
Moreover, the equipment cost and the grinding cost are low. Further, dishing due to overpolishing can be suppressed, and the variation in the SOI layer is reduced, which is extremely advantageous for reducing the thickness of the SOI structure.

【0012】選択研磨法とは、絶縁膜34を研磨ストッ
パにして単結晶シリコン層32全面を同時に研磨し、絶
縁膜34の上面に到達した時点で研磨を終了する研磨法
である。図2を参照して、選択研磨法により貼り合わせ
基板30を研磨する研磨装置40の構成及び動作を説明
する。選択研磨法用の研磨装置40は、図2に示すよう
に、貼り合わせ基板30を真空吸着して保持し、かつ回
転するウエハホルダ42と、研磨定盤44とその上面に
貼り付けられた研磨パッド46とからなる回転自在な研
磨盤48と、研磨パッド46上に研磨液Lを供給するノ
ズル50とから構成されている。研磨パッド46は、セ
ラミック板などの超硬質定盤からスウェードタイプの発
泡ポリウレタンの軟質クロスまで、必要とする研磨材の
硬さに応じて使用できる。研磨する際には、先ず、研磨
する貼り合わせ基板30を下向きしてウエハホルダ42
に保持させる。次いで、ノズル50から研磨パッド46
上に研磨液Lを供給しながら、基板の被研磨面を研磨パ
ッド46に面接触させ、かつ回転させて基板の被研磨面
の全面を同時に研磨する。研磨液Lには、SiO2 膜と
は化学反応せず、単結晶シリコンと化学反応するアルカ
リ性の研磨液を使用する。研磨液の化学反応選択性によ
り、シリコン層を選択的に研磨することができる。
The selective polishing method is a polishing method in which the entire surface of the single-crystal silicon layer 32 is simultaneously polished using the insulating film 34 as a polishing stopper, and the polishing is completed when the polishing reaches the upper surface of the insulating film 34. The configuration and operation of the polishing apparatus 40 for polishing the bonded substrate 30 by the selective polishing method will be described with reference to FIG. As shown in FIG. 2, the polishing apparatus 40 for the selective polishing method includes a wafer holder 42 that rotates and holds the bonded substrate 30 by vacuum suction, a polishing platen 44, and a polishing pad bonded to the upper surface thereof. And a nozzle 50 for supplying a polishing liquid L onto the polishing pad 46. The polishing pad 46 can be used according to the required hardness of the abrasive, from a super-hard platen such as a ceramic plate to a soft cloth of suede-type foamed polyurethane. When polishing, first, the bonded substrate 30 to be polished is faced down and the wafer holder 42 is
To be held. Next, the polishing pad 46 is
While supplying the polishing liquid L thereon, the surface to be polished of the substrate is brought into surface contact with the polishing pad 46, and is rotated to simultaneously polish the entire surface to be polished of the substrate. As the polishing liquid L, an alkaline polishing liquid that does not chemically react with the SiO 2 film but chemically reacts with the single crystal silicon is used. The silicon layer can be selectively polished by the chemical reaction selectivity of the polishing liquid.

【0013】上述の実施形態例のように、貼り合わせ基
板30の単結晶シリコン層32の厚さが5μm になるま
で研削し、次いで単結晶シリコン層32の厚さが1.0
μmになるまでドライエッチングし、最後に研磨工程を
行う場合、ドライエッチングの取り代バラツキを±5%
とし、選択研磨の取り代バラツキを±10%〜±15%
として、最終の基板面の凹凸の大きさを計算すると、次
のようになる。 4μm ×0.05×2+1μm ×0.1×2=0.6μ
m 一方、従来の方法によりSOI基板を作製し、研削工程
で単結晶シリコン層の厚さが5μm になるまで研削する
とした場合、研磨工程で研磨する単結晶シリコン層の厚
さは5μm となる。5μm を研磨すると、±10%の取
り代バラツキが生じるので、SOI構造の基板面の凹凸
の大きさは、5μm ×0.1×2=1μm となる。以上
の計算から判るとおり、本発明方法によれば、表面の凹
凸が従来の方法に比べて小さいSOI基板を提供するこ
とができる。
As in the above-described embodiment, the single-crystal silicon layer 32 of the bonded substrate 30 is ground until the thickness thereof becomes 5 μm, and then the thickness of the single-crystal silicon layer 32 becomes 1.0 μm.
When dry-etching to a thickness of μm and finally performing the polishing process, the variation in dry etching allowance is ± 5%
± 10% to ± 15%
When the size of the irregularities on the final substrate surface is calculated, the result is as follows. 4μm × 0.05 × 2 + 1μm × 0.1 × 2 = 0.6μ
m On the other hand, when an SOI substrate is manufactured by a conventional method and the single crystal silicon layer is ground in the grinding step until the thickness of the single crystal silicon layer becomes 5 μm, the thickness of the single crystal silicon layer polished in the polishing step is 5 μm. If 5 μm is polished, a variation of ± 10% is generated, so that the size of the unevenness on the substrate surface of the SOI structure is 5 μm × 0.1 × 2 = 1 μm. As can be seen from the above calculations, according to the method of the present invention, it is possible to provide an SOI substrate whose surface unevenness is smaller than that of the conventional method.

【0014】[0014]

【発明の効果】本発明によれば、SOI基板を貼り合わ
せ方式により作製する際、研削工程に次いでエッチング
により単結晶シリコン層を薄層化し、最終の仕上げ工程
で研磨加工を行う。本発明では、研磨すべき単結晶シリ
コン層の厚さが従来の方法に比べて格段に薄いので、研
磨むらの発生を最小限に抑制することができる。これに
より、研削精度を損なうことなく、研磨加工を施すこと
ができるので、均一な薄膜SOI構造を得ることができ
る。更には、均一な薄膜SOI層を基板全面にわたり得
ることができるので、製品歩留りが向上する。また、局
所研磨とは異なり基板面を全面研磨加工しているので、
加工時間が短くて済み、生産性が向上する。また、均一
な薄膜SOI層を形成できるので、0.1μm以下の貼
り合わせSOI基板の薄膜化が可能となる。
According to the present invention, when an SOI substrate is manufactured by a bonding method, a single crystal silicon layer is thinned by etching after a grinding step, and polishing is performed in a final finishing step. In the present invention, since the thickness of the single-crystal silicon layer to be polished is much smaller than that of the conventional method, it is possible to minimize the occurrence of uneven polishing. Thus, the polishing can be performed without deteriorating the grinding accuracy, so that a uniform thin film SOI structure can be obtained. Further, since a uniform thin film SOI layer can be obtained over the entire surface of the substrate, the product yield is improved. Also, unlike local polishing, the entire substrate surface is polished,
Processing time is short, and productivity is improved. Further, since a uniform thin SOI layer can be formed, the thickness of the bonded SOI substrate having a thickness of 0.1 μm or less can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1(a)から(c)は、それぞれ、本実施形
態例の各工程の基板断面図である。
FIGS. 1A to 1C are cross-sectional views of a substrate in respective steps of an embodiment of the present invention.

【図2】選択研磨装置の構成を示す模式図である。FIG. 2 is a schematic diagram illustrating a configuration of a selective polishing apparatus.

【図3】SOI基板の構成を示す基板断面図である。FIG. 3 is a cross-sectional view illustrating a configuration of an SOI substrate.

【図4】従来の貼り合わせSOI基板の作製方法の各工
程の基板断面図である。
FIG. 4 is a cross-sectional view of a substrate in each step of a conventional method for manufacturing a bonded SOI substrate.

【図5】研削装置の構成を示す模式図である。FIG. 5 is a schematic diagram showing a configuration of a grinding device.

【符号の説明】[Explanation of symbols]

10……素子形成基板、12……凹部、14……絶縁
膜、16……多結晶シリコン層、18……支持基板、1
9……貼り合わせSOI基板、20……支持基板、22
……絶縁膜、24……薄膜単結晶シリコン層、26……
SOI基板、28……細い櫛歯状に形成された単結晶シ
リコン層、30……貼り合わせ基板、32……単結晶シ
リコン層、34……絶縁膜、36……多結晶シリコン
層、38……支持基板、39……SOI基板、40……
選択研磨法用の研磨装置、42……ウエハホルダ、44
……研磨定盤、46……研磨パッド、48……研磨盤、
50……ノズル、52……研削装置、54……レジン砥
石、56……レジンボンド56、58……回転ウエハホ
ルダ。
10 ... element forming substrate, 12 ... recess, 14 ... insulating film, 16 ... polycrystalline silicon layer, 18 ... support substrate, 1
9 bonded SOI substrate, 20 support substrate, 22
... insulating film, 24 ... thin film single crystal silicon layer, 26 ...
SOI substrate, 28 single crystal silicon layer formed in a thin comb shape, 30 bonded substrate, 32 single crystal silicon layer, 34 insulating film, 36 polycrystalline silicon layer, 38 ... Support substrate, 39 ... SOI substrate, 40 ...
Polishing device for selective polishing, 42 Wafer holder 44
… Polishing table, 46… polishing pad, 48… polishing table,
50 ... Nozzle, 52 ... Grinding device, 54 ... Resin grindstone, 56 ... Resin bond 56, 58 ... Rotary wafer holder.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 単結晶シリコン基板をパターニングして
所定パターンの凹部を単結晶シリコン基板面に形成し、
凹部壁及び基板面に沿って絶縁膜を成膜し、更に別の層
を基板全面に成膜して上面を平坦化し、平坦化した上面
を別の支持基板上に面接触させるようにして単結晶シリ
コン基板と別の支持基板とを貼り合わせて合体し、次い
で絶縁膜を露出させるまで単結晶シリコン基板を研削し
て、支持基板上に薄膜SOI構造を備えたSOI基板を
作製する方法において、 薄膜SOI構造を形成する絶縁膜上の単結晶シリコン層
の厚さが第1の所定厚さになるまで、単結晶シリコン層
を研削する研削工程と、 次いで、単結晶シリコン層の厚さが第2の所定厚さにな
るまで、ドライエッチングにより単結晶シリコン層をエ
ッチングする工程と、 次いで、絶縁膜を露出させるまで単結晶シリコン層を研
磨する仕上げ工程とを有することを特徴とする貼り合わ
せSOI基板の作製方法
1. A single crystal silicon substrate is patterned to form a recess having a predetermined pattern on a surface of the single crystal silicon substrate.
An insulating film is formed along the concave wall and the substrate surface, another layer is formed on the entire surface of the substrate, the upper surface is flattened, and the flattened upper surface is brought into surface contact with another supporting substrate. In a method for manufacturing an SOI substrate having a thin-film SOI structure over a support substrate, a single-crystal silicon substrate is ground until a crystalline silicon substrate and another support substrate are bonded to each other, and then the insulating film is exposed. A grinding step of grinding the single-crystal silicon layer until the thickness of the single-crystal silicon layer on the insulating film forming the thin-film SOI structure reaches a first predetermined thickness; A step of etching the single crystal silicon layer by dry etching until a predetermined thickness of 2 is obtained, and a finishing step of polishing the single crystal silicon layer until the insulating film is exposed. Method for manufacturing an SOI substrate
【請求項2】 仕上げ工程では、選択研磨法により研磨
することを特徴とする請求項1に記載の貼り合わせSO
I基板の作製方法。
2. The bonding SO according to claim 1, wherein in the finishing step, polishing is performed by a selective polishing method.
Method for manufacturing I substrate.
【請求項3】 第1の所定厚さ及び第2の所定厚さが、
それぞれ、3〜5μm 及び0.5〜1.0μm であるこ
とを特徴とする請求項1又は2に記載の貼り合わせSO
I基板の作製方法。
3. The method according to claim 1, wherein the first predetermined thickness and the second predetermined thickness are:
3. The bonded SO according to claim 1, wherein the thickness is 3 to 5 [mu] m and 0.5 to 1.0 [mu] m, respectively.
Method for manufacturing I substrate.
JP18621797A 1997-07-11 1997-07-11 Method for manufacturing stuck soi substrate Pending JPH1131640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18621797A JPH1131640A (en) 1997-07-11 1997-07-11 Method for manufacturing stuck soi substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18621797A JPH1131640A (en) 1997-07-11 1997-07-11 Method for manufacturing stuck soi substrate

Publications (1)

Publication Number Publication Date
JPH1131640A true JPH1131640A (en) 1999-02-02

Family

ID=16184427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18621797A Pending JPH1131640A (en) 1997-07-11 1997-07-11 Method for manufacturing stuck soi substrate

Country Status (1)

Country Link
JP (1) JPH1131640A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100511896B1 (en) * 1999-06-24 2005-09-02 주식회사 하이닉스반도체 Method of manufacturing soi substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100511896B1 (en) * 1999-06-24 2005-09-02 주식회사 하이닉스반도체 Method of manufacturing soi substrate

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