JPH04226031A - Manufacture of semiconductor wafer and semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacture of a semiconductor wafer or SOI substrate having a TTV of less than 1 micron that is required for manufacture of a highly packed IC in the future. CONSTITUTION:A crystalline semiconductor ingot is sliced into crystalline semiconductor wafers. These wafers are flattened by chemical or mechanical abrasion before they are given asymmetry by orientation flats. This avoids effects of the orientation flat on the flatness of wafers. Since grinding is used instead of conventional lapping, wafer flatness is improved, and etching can be eliminated which is needed after lapping. As a result, 6-inch wafers with a TTV of less than 1 micron is obtained at a yield of 90%. When this method is applied to an SOI substrate having two wafers joined with an insulating layer between, one wafer can be several microns thick, thereby promoting the realization of an integrated circuit of SOI structure.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a so-called orientation flat.
The present invention relates to a semiconductor wafer provided with positioning means such as an OF or a notch, and a semiconductor device manufactured using this wafer.

The trend toward higher integration, higher speed, and smaller size of semiconductor devices is becoming more and more rapid. Along with this, the patterns of semiconductor device components are shrinking, but in order to form submicron-scale fine patterns on semiconductor wafers, it is necessary to improve the flatness and thickness uniformity of the wafer surface by 1 μm or more. A value lower than that is now required. In addition, so-called SOI (Silicon-on-
In the practical application of high-performance semiconductor devices using an insulator structure, a substrate is created by bonding two silicon wafers with an insulating layer in between.
The approach using te) currently seems the most promising, but this requires thinning one silicon wafer to a thickness of several micrometers.

0003

[Prior Art] Semiconductor wafers as described above are usually
It is manufactured according to the steps shown in FIG. That is, (a) a semiconductor single crystal ingot having a desired composition is pulled up by, for example, the Czochralski (CZ) method, and (b) this ingot is roughly cut into appropriate lengths. (c) The side surface of the ingot is processed into a cylindrical shape, and a flat surface parallel to the axis of the cylinder is formed on the side surface. This plane constitutes the OF described later. Next, (d) the ingot is sliced into a number of disks using a rotary blade slicer, and (e) the circumference of the disks is chamfered or beveled.
(f) lapping at least the surface on which semiconductor devices will be formed in the future;
) Etching using a chemical solution, and (h) mirror finishing using so-called chemical/mechanical polishing. Finally,
(i) Clean and complete. This mirror-finished surface has smoothness and crystallinity suitable for forming semiconductor devices. The semiconductor wafer manufactured by the above process is a disk in which, for example, a linear notch, that is, an OF, is provided in a part of the circumference.

[0004] The etching in (g) above is performed using (f
) This is done to remove crystal defects that occur on the wafer surface during lapping, but at this time, the flatness actually deteriorates due to differences in the etching rate on the surface due to the circulation of the etching solution and uneven temperature. However, the flatness is restored by polishing in (h).

[0005]

[Problem to be Solved by the Invention] However, the flatness of a semiconductor wafer manufactured by the above conventional process is determined by the TTV (TTV), which is expressed as the difference between the maximum and minimum heights of the wafer surface.
total thickness variation
) is about 2 μm, and for this reason, the yield of wafers that can meet the above-mentioned flatness requirements of 1 μm or less has been extremely low. This means that
This also means that in the process of manufacturing a substrate with an SOI structure as described above, it is difficult to uniformly thin one of the bonded wafers to a thickness of several μm or less.

[0006] Therefore, the present invention provides high flatness,
Specifically, it is an object of the present invention to provide a practical method that enables semiconductor wafers having a TTV value of 1 μm or less to be manufactured with good yield. Another object of the present invention is to provide a method that enables one wafer of an SOI structure substrate formed by bonding two semiconductor substrates via an insulating layer to have a uniform thickness of several μm or less. do.

[0007]

[Means for Solving the Problems] The above object is to form an ingot made of a semiconductor crystal and having a cylindrical side surface, to slice the ingot to form a semiconductor crystal disk, and to slice at least one of the disks. The circular surface is subjected to a process of applying mechanical force to flatten the surface, and a notch is provided in a part of the circumference of the disk where the circular surface has been flattened, so that the outer shape is made into a non-rotationally symmetrical shape. A method for manufacturing a semiconductor wafer according to the present invention, characterized by including various steps, or
forming an ingot with cylindrical sides of semiconductor crystal; slicing the ingot to form semiconductor crystal disks; planarizing at least one circular surface in each of the two disks; applying a mirror finish to the flattened circular surface of each of the two discs, forming an insulating layer on the mirror finished surface of at least one of the two discs, and applying the mirror finished surface to the mirror finish surface through the insulating layer. This is achieved by the semiconductor wafer manufacturing method according to the present invention, which is characterized by including the steps of joining the two disks while facing each other.

[0008]

[Operation] In the present invention, asymmetrical shape processing such as an OF or a notch provided to indicate the crystal orientation of the semiconductor wafer is performed after the planarization processing. therefore,
For the two wafers in the SOI structure substrate, the surface of the wafer on which the semiconductor device is to be formed is flattened or mirror-finished, and then asymmetrical contour processing such as OF is performed. In addition, surface grinding replaces the conventional lapping and subsequent etching for flattening a disk formed by slicing a semiconductor crystal ingot. As a result, it is possible to obtain with high yield a wafer with excellent flatness after mirror finishing or an SOI substrate having a semiconductor layer uniformly thinned to a thickness of several μm.

[0009]

[Example] The present inventors obtained the following findings in preliminary research on improving the flatness of semiconductor wafers. In other words, a)
By performing so-called surface grinding using a flat grindstone instead of lapping (f) in the conventional process above, better flatness can be obtained, and if a grindstone with a small grain size is used, compared to lapping, A surface with little residual crystal distortion can be obtained.

(b) The thickness in a triangular region connecting the center of the semiconductor wafer and the side of the OF tends to be relatively small. The above findings indicate that by using surface grinding, the time for lapping (f) and etching (g) in the above conventional process can be shortened or omitted;
Furthermore, this suggests that it is possible to reduce the amount of thickness reduction due to polishing in (h) above. moreover,
The above findings suggest that in the planarization or mirror finishing process of semiconductor wafers, asymmetric shapes such as OF may act to degrade the flatness of the wafer surface.

[0011] Therefore, the inventor of the present invention modified the semiconductor wafer manufacturing process as shown in the chart of FIG. In Fig. 1, the steps from crystal growth in (a) to side grinding of the ingot in (c) are the same as in Fig. 2. However, in (c) side grinding of the ingot, a surface that will become the OF in the future is not formed as in the conventional method. (d) After slicing the ingot into disks of semiconductor crystal, (e) chamfering the sides of the disks. Then, (f) this disk is surface ground with a surface grindstone, and (g
) A mirror finish is applied to the plane-ground surface by chemical and mechanical polishing. After that, (h) machining the disc into an asymmetrical shape such as OF, and (i) machining the O
Chamfer the F part, and finally clean (j).

As mentioned above, the main difference between the conventional process and the process of the present invention is that instead of lapping (f) and etching (g) in FIG. 2, (e) In FIG. 1, the formation of the OF is performed after slicing in (d), surface grinding in (f), and polishing in (g).

As described above, in the present invention, the surface of a sliced disk of semiconductor crystal is ground to approximately a predetermined thickness by surface grinding using a flat grindstone and is flattened. Figure 3 is a schematic plan view (A) and side view (B) for explaining this surface grinding. ) 2 is ground with a flat grindstone 4 rotating counterclockwise.

FIG. 4 is a graph showing the improvement in flatness due to the surface grinding in comparison with a semiconductor wafer subjected to conventional lapping and etching. The horizontal axis is TTV
The vertical axis shows the flatness expressed as , and the vertical axis shows the proportion (%) of the number of semiconductor wafers. For the surface grinding described above, a high-precision surface grinding device manufactured by Shibayama Kikai Co., Ltd. (Osaka) was used. The flat grindstone has a diameter of approximately 150 cm and a roughness of #2000. Figure 4 shows the results after plane-grinding both sides of a 6-inch diameter silicon wafer, which has a thickness of about 800 μm immediately after slicing, to a thickness of about 40 μm on each side. However, for samples made using the conventional process, both sides of a silicon wafer of the same size are separated by approximately 40 μm.
It is individually wrapped. OFs are formed in both groups of samples. The length of OF is 55.5 mm.

As shown in the figure, the flatness of the wafer surface due to lapping ranges from 1.5 to 2.2 μm, while the flatness due to surface grinding ranges from 0.5 to 0.
．． 8. It is distributed in μm. In other words, it can be seen that surface grinding provides better flatness and less variation from wafer to wafer.

However, when the chemical/mechanical polishing shown in FIG. 1(f) is applied to the wafer that has undergone the surface grinding described above, the flatness deteriorates as shown in FIG. 5. Figure 5A shows the flatness distribution of the semiconductor wafer immediately after surface grinding.
B is a graph showing the flatness distribution of semiconductor wafers polished after surface grinding, where the horizontal axis represents the flatness expressed in TTV, and the vertical axis represents the proportion (%) of the number of semiconductor wafers. , respectively. In addition, each of both figures shows 192 silicon wafers with a diameter of 6 inches.
Each wafer has a thickness of 40 to 50 μm.
m This is the result of polishing.

As shown in both figures, the TTV of the wafer immediately after surface grinding is in the range of 0.4 to 0.8 μm, with an average value of 0.58 μm. On the other hand, the TTV of polished wafers is 0.6 to 2.3.
It is distributed in μm, and the average value is 1.21 μm. In the latter case, only 42% of the total wafers have a TTV of 1 μm or less. However, compared to the TTV distribution of a typical finished wafer, which is 2.0 to 3.0 μm, the improvement effect of surface grinding is clear.

[0018] Based on the above knowledge that in flattening or polishing a semiconductor wafer, asymmetry such as the OF may act to deteriorate the flatness, the inventor has determined that the flat surface constituting the OF 6 inches in diameter, approximately 80mm thick, made by slicing an ingot without forming sides.
A 0 μm silicon disk was surface ground as described above,
Thereafter, these disks were subjected to the chemical and mechanical polishing described above. The flatness of these silicon disks is shown in FIG. Figure 6A shows the TTV distribution of 192 silicon wafers that were surface ground, and Figure 6B shows the TTV distribution of these silicon wafers after polishing them to a thickness of 40 to 50 μm.
TV distribution is shown.

As shown in the figure, the TTV of the wafer before polishing
Distribution is 0.4-0.9 μm, average value 0.61 μm
It is. TTV distribution after polishing is 0.5-1.3
μm, the average value is 0.80 μm, and 92% of the wafers have a TTV of 1 μm or less. from this result,
Regarding wafers that were surface ground without forming an OF,
Deterioration of flatness due to polishing is observed. However, Figure 6
A comparison between Figure 5B and Figure 5B shows that the deterioration in flatness due to polishing is significantly smaller when surface grinding is performed without forming an OF.

FIG. 7 is a schematic bird's-eye view showing an example of measuring the height distribution of the wafer surface immediately after surface grinding, and FIG. 7A is a wafer without an OF (actually no OF
Figure 7B shows a wafer provided with OF. Each TTV is 0.54 μm and TTV is 0.58 μm, so there is no difference. However, in Figure 7A, where no OF is provided, no specific non-flatness is observed on the surface, whereas in Figure 7B, where OF is provided,
The presence of a recess extending from the center of the wafer toward the OF is clearly recognized. In this way, it can be seen that OF influences flatness, although it does not appear noticeably in TTV.

The above relationship between wafer flatness and OF can be interpreted as follows. That is, FIG. 8A
The contact area between the surface of the wafer 12 and the flat grinding wheel 4 is different between the period when the OF 12a overlaps with the flat grinding wheel 4 as shown in ~8C and the period when the OF 12a does not overlap with the flat grinding wheel 4 as shown in FIG. 8D. It is presumed that as a result of the non-uniform pressure, the triangular region connecting the center of the wafer 12 and both ends of the OF 12a tends to become thinner. A similar problem occurs in the chemical/mechanical polishing described above in which a polishing cloth and abrasive grains are pressed against the wafer surface.

As shown in FIG. 6, when the OF is not provided, the contact area between the wafer and the flat grindstone or polishing surface plate is always constant, so the thickness is not uniform. As a result, TTV becomes smaller. It is currently not clear why the effect of the presence of OF is small in surface grinding and becomes noticeable in polished wafers.

From the above results, according to surface grinding,
The surface flatness of the majority of semiconductor wafers is measured at 1μ by TTV.
m or less. Furthermore, by using a flat grindstone with low roughness, crystal distortion occurring on the wafer surface can be reduced. Therefore, the chemical and mechanical polishing that follows only needs to be applied to the minimum amount necessary and sufficient to remove crystal distortion on the wafer surface. Furthermore, conventional wrapping and chemical etching can be substantially omitted.

FIG. 1 shows the flow of forming an OF on a wafer after the above-mentioned surface grinding and subsequent polishing. Therefore, the amount of polishing required for subsequent mirror finishing is small. This means that even if surface grinding is followed by OF formation and subsequent polishing, the deterioration in flatness can be kept to a sufficiently small level. or,
A method may be adopted in which rough polishing to a thickness of approximately 10 μm μm is performed before the OF formation, and final polishing to a thickness of approximately 0.5 μm is performed after the OF formation.

The OF may be formed on the semiconductor wafer subjected to the surface grinding or polishing as described below. In other words, similar to the dicing process in which a wafer is normally cut into chips, adhesive tape is attached to the back of the wafer, the wafer is vacuum-adsorbed and fixed to the stage of a dicer via the adhesive tape, and then the wafer is diced using the cutter of the dicer. The end of the disc-shaped wafer is fully cut at a speed of about 50 mm/min. Cutting time per wafer is about 1 minute.

In order to facilitate the cutting process for forming the OF, marks for indicating the cutting position may be formed on the side surface of the semiconductor crystal ingot before it is sliced into disks. As such a mark, as shown in FIG. 9, a mark 11 consisting of, for example, a linear shallow groove (mark) parallel to the axis of the cylinder is formed on the cylindrical side surface of the ingot 1. It goes without saying that the mark 11 is formed in relation to the crystal orientation of the ingot 1. In addition, in the case of groove-shaped mark 11,
It is formed as shallowly as possible so that it does not disappear when the side surface of the semiconductor wafer is chamfered later, and does not reach the effective circular surface of the wafer after chamfering. This makes it possible to eliminate the influence on the surface flatness during the surface grinding and polishing. As such marks, grooves may be formed using a laser beam, or ruled lines may be drawn using water-resistant ink. Furthermore, mark such as groove 11 as above,
If two marks are formed on the side of an ingot, the OF can be formed by cutting on the line connecting these two marks remaining on the side of the surface-ground or polished semiconductor wafer.
can be easily formed.

SOI made by bonding two semiconductor wafers
The process of manufacturing a substrate according to the present invention will be explained with reference to FIG. Two silicon wafers having at least one side chemically and mechanically polished are prepared according to the steps (a) to (g) in FIG. Note that marks indicating the crystal orientation are formed on the side surfaces of these wafers as described above.

Next, as shown in FIG. 10A, the surface of at least one of the two silicon wafers 20 or 21 is coated by, for example, a well-known thermal oxidation method.
As shown in FIG. 10A, an oxide film 22 with a thickness of about 1 μm
form. Then, these silicon wafers 20 and 21 are stacked so that the polished surfaces face each other, and
Heat treatment is performed at 1100° C. in a nitrogen gas atmosphere. It is also known to apply a pulse voltage between the silicon wafers 20 and 21 before heat treatment to increase the bonding strength. As a result, the silicon wafers 20 and 21 are firmly bonded to each other via the oxide film 22. Note that when the silicon wafers 20 and 21 are stacked on top of each other, their mutual crystal orientations are related based on the mark 11 remaining on each side surface. FIG. 10B is a plan view of the stacked silicon wafers 20 and 21, showing the circular flat surface and the chamfered area around it.

Next, for example, the silicon wafer 21 is
The surface is ground to a thickness of ~4 μm, and then chemically and mechanically polished. As a result, the thickness of the silicon wafer 21 is uniformly reduced to 2 μm, as shown in FIG. 11C.
Thin until After that, with reference to the mark 11 remaining on the side surface of the silicon wafer 20,
As shown in the cross-sectional view, silicon wafers 20 and 2
1 to form OF21a. Figure 11E is
FIG. 3 is a corresponding plan view. The mark 11 on the side surface of the silicon wafer 21 may disappear during the process of forming the oxide film 22 or thinning it by surface grinding or polishing. Therefore, silicon wafer 20
When overlapping and 21, if the mutual crystal orientations are related based on the mark 11 as described above, the crystal orientation of the silicon wafer 21 can be known from the OF 21a. In this way, an SOI substrate consisting of a 2 μm thick silicon single crystal layer supported by a silicon wafer several 100 μm thick through an insulating layer is completed.

A semiconductor device is formed on the semiconductor wafer manufactured according to the process shown in FIG. 1 or on the SOI substrate manufactured according to the process shown in FIGS. 10 and 11 according to the usual process. An example of this will be described using the above SOI substrate. Figure 12A is
FIG. 4 is a partially enlarged view of the SOI substrate shown in FIG. A separation region 25 is formed around the element formation region defined in the silicon wafer 21, which is thinned to about 2 μm on this substrate. The isolation region 25 is a well-known LOCOS (Local
It may be any structure such as a field oxide film formed by the Oxidation of Silicon method or a trench reaching the oxide film 22.

Next, the surface of the silicon wafer 21 separated into each element forming region is thermally oxidized, as shown in FIG. 12B.
As shown in the figure, a gate insulating film 26 with a thickness of about 200 Å
form. Then, the well-known CVD (chemical
A gate electrode 27 made of, for example, a polysilicon layer is formed using a vapor deposition technique and a lithography technique. Furthermore, a resist mask 28 is formed on the surface of the SOI substrate to expose a predetermined element formation region, and the resist mask 28 and the gate electrode 2
For example, arsenic (
Source/drain regions 29 are formed by ion-implanting impurities such as As).

Next, as shown in FIG. 12C, S
For example, on the surface of the OI substrate, PSG (phospho
Insulating layer 3 consisting of sili-cate glass)
0 is formed, and contact holes are formed at predetermined positions in the insulating layer 30. After that, an aluminum layer is deposited on the insulating layer 30, and this is patterned using well-known lithography technology to form a gate wiring 31 as shown in the figure.
and source/drain electrodes 32 are formed, SOI
MISFET (metal-insulator) structure
-se-mincoductor field-eff
ect transistor) is completed.

[0033] The OF 21 formed on the SOI substrate
a is the mask and SOI in the above lithography process
Needless to say, this is essential for alignment with the substrate. According to the method for manufacturing a semiconductor wafer according to the present invention as explained above, it is easier to polish a large area compared to the conventional method in which dummy members of the same thickness are placed around the object to be processed. The surface can be flattened. In other words, in the conventional method described above, the dummy member must have the same thickness and material as the workpiece, and
A large number of man-hours are required to spread such dummy members around the workpiece. Furthermore, these dummy members cannot be reused. Therefore, the present invention is excellent in terms of cost and mass productivity.

As is clear from the above description, the method for manufacturing a semiconductor wafer of the present invention is effective regardless of the size or material of the wafer. In addition, the SOI substrate according to the present invention can be used not only for manufacturing MISFETs as in the above embodiments, but also for manufacturing MISFETs.
Needless to say, the present invention is applicable to the manufacture of bipolar transistors, so-called Bi-MOS structure semiconductor devices in which MISFET and bipolar are mixed, or integrated circuits made of these.

[0035]

[Effects of the Invention] According to the present invention, semiconductor wafers with excellent flatness that can respond to the formation of fine patterns of submicron rule can be manufactured with high yield, and this promotes the development and practical application of high-density integrated circuits. effective. Also,
The wafer in a bonded SOI substrate can be uniformly thinned to several micrometers or less, which has the effect of promoting the development and practical application of integrated circuits with an SOI structure.

[Brief explanation of the drawing]

[Fig. 1] Chart for explaining one embodiment of the semiconductor wafer manufacturing process according to the present invention

[Figure 2] Chart for explaining the conventional process of manufacturing semiconductor wafers

[Figure 3] Schematic diagram to explain surface grinding

[Figure 4]
Graph to explain improvement in flatness due to surface grinding

[Figure 5] Graph showing the deterioration of flatness due to chemical/mechanical polishing

[Figure 6] Chemical analysis of wafers without OF
Graph showing changes in flatness due to mechanical polishing

[Figure 7]
Schematic bird's eye view showing an example of deterioration of wafer surface flatness due to the presence of OF

[Figure 8] Schematic plan view for explaining the mechanism of deterioration of wafer surface flatness due to the presence of OF

[Fig. 9] A schematic perspective view showing an example of a mark provided on the side surface of a semiconductor crystal ingot.

FIG. 10 A schematic cross-sectional view (part 1) for explaining the manufacturing process of an SOI substrate according to the present invention

FIG. 11 A schematic cross-sectional view (part 2) for explaining the manufacturing process of an SOI substrate according to the present invention.

FIG. 12 is a schematic cross-sectional view for explaining an example of the manufacturing process of a semiconductor device using the semiconductor wafer according to the present invention.

[Explanation of symbols]

1 ingot
25 Separation area 2, 12 Wafer
26 Gate insulating film 3 stage
27 Gate electrode 4 Flat grindstone
28 Resist Mask 11 Mark
29 Source/drain region 12a, 21a Orientation flat 30 Insulating layer 20, 21 Silicon wafer
31 Gate wiring 22 Oxide film
32 Source/drain electrode

Claims (24)

[Claims] 1. Forming an ingot with cylindrical sides made of a semiconductor crystal; slicing the ingot to form a semiconductor crystal disk; and mechanically cutting at least one circular surface of the disk. a step of flattening the surface by applying force; and a step of creating a notch in a part of the circumference of the disk with the flattened circular surface to give the outer shape a non-rotationally symmetrical shape. A method for manufacturing a semiconductor wafer, comprising: 2. The method of manufacturing a semiconductor wafer according to claim 1, wherein the circular surface of the disk is flattened using rotary grinding means. 3. The method of manufacturing a semiconductor wafer according to claim 1, wherein the notch is formed by cutting the disk along a straight line connecting two points on the circumference. 4. Prior to the step of slicing the ingot, a step of providing a linear mark parallel to the axis of rotational symmetry of the ingot on the side surface of the ingot, and a step of slicing the ingot on the side surface of the disk with the circular surface flattened. 2. The method of manufacturing a semiconductor wafer according to claim 1, further comprising the step of forming the notch based on the mark remaining on the wafer. 5. Prior to the step of slicing the ingot, the step of forming two linear marks parallel to the rotational symmetry axis of the ingot on the side surface of the ingot, and flattening the circular surface. 2. The method of manufacturing a semiconductor wafer according to claim 1, further comprising the step of cutting the disk based on the two marks remaining on the side surface of the disk to form the notch. . 6. Prior to the flattening step, chamfering the side surface of the disk so that the mark remains on the side surface of the disk and the mark does not appear on the circular surface to be flattened. 6. The method of manufacturing a semiconductor wafer according to claim 4, further comprising: 7. The method of manufacturing a semiconductor wafer according to claim 4, wherein the mark is formed by scanning a side surface of the ingot with a laser beam. 8. The method of manufacturing a semiconductor wafer according to claim 1, further comprising the step of mirror-finishing the flattened surface. 9. The method of manufacturing a semiconductor wafer according to claim 8, wherein the mirror finishing is performed by chemical/mechanical polishing. 10. A method for manufacturing a semiconductor device, comprising the step of introducing impurities into the mirror-finished surface of a semiconductor wafer manufactured by the manufacturing method according to claim 8. 11. Forming an ingot of semiconductor crystal with cylindrical sides; slicing the ingot to form semiconductor crystal disks; and at least one circular surface in each of the two disks. a step of flattening the flattened circular surface of each of the two disks, and forming an insulating layer on the mirror-finished surface of at least one of the two disks. A method for manufacturing a semiconductor wafer, comprising: a step of bonding the two disks with the mirror-finished surfaces facing each other with the insulating layer interposed therebetween. 12. The method of manufacturing a semiconductor wafer according to claim 11, wherein the two disks are bonded so that they face each other so that their crystal orientations are in a predetermined relationship. 13. A step of providing a linear mark parallel to a rotational symmetry axis of the ingot on a side surface of the ingot prior to the step of slicing the ingot, and an insulating layer is formed on at least one surface of the ingot. 12. The method of manufacturing a semiconductor wafer according to claim 11, further comprising the step of bringing the two disks into the opposed state based on the mark remaining on each side surface of the two disks. 14. Prior to the step of flattening a circular surface of each of the two discs, the mark is left on the side surface of each of the discs, and the mark is exposed on the circular surface to be flattened. 14. The method of manufacturing a semiconductor wafer according to claim 13, further comprising the step of chamfering the side surface of the disk so that the side surface does not come out. 15. The method of manufacturing a semiconductor wafer according to claim 11, wherein the circular surface of each of the two disks is flattened using rotary grinding means. 16. The method of manufacturing a semiconductor wafer according to claim 11, wherein the mirror finishing is performed by chemical/mechanical polishing. 17. The method of manufacturing a semiconductor wafer according to claim 11, further comprising the step of thinning one of the two joined disks to a substantially uniform thickness. 18. The method of manufacturing a semiconductor wafer according to claim 17, wherein said one disk is made thinner by using rotary grinding means. 19. The method of manufacturing a semiconductor wafer according to claim 17, wherein the surface of the thinned disk is mirror-finished. 20. The method of manufacturing a semiconductor wafer according to claim 19, wherein the mirror finishing is performed by chemical/mechanical polishing. 21. The method further includes the step of providing a notch in a part of the circumference of at least the other of the two discs, one of which is thinned, to make the outer shape a rotationally non-symmetrical shape. The method for manufacturing a semiconductor wafer according to claim 18. 22. The method of manufacturing a semiconductor wafer according to claim 21, wherein the notch is formed by cutting the two disks along a straight line connecting two points on the circumference. 23. A method of manufacturing a semiconductor device, further comprising the step of introducing impurities into the mirror-finished surface of the semiconductor wafer according to claim 19. 24. A step of mirror-polishing the circular surface of the thinned disk in the semiconductor wafer according to claim 17; a step of providing a common notch in a part of the semiconductor wafer to make the outer shape a non-rotationally symmetrical shape; a step of aligning the semiconductor wafer with reference to the notch; and a step of aligning the semiconductor wafer with reference to the notch; A method for manufacturing a semiconductor device, comprising the step of introducing impurities into the mirror-polished surface of a semiconductor wafer.