JP6525046B1 - Semiconductor wafer manufacturing method - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor wafer capable of enhancing the film thickness uniformity of a semiconductor layer. A method for manufacturing a semiconductor wafer according to the present invention includes a processing tendency acquisition step S10 for obtaining a processing tendency of a planarization apparatus using a local dry etching method, and a processing for measuring a film thickness distribution before the planarization processing of a semiconductor layer. In the planarizing device, a front film thickness distribution measuring step S20, a step S30 of setting a virtual film thickness distribution of the semiconductor layer, a target film thickness distribution of the semiconductor layer and a target etching amount distribution based on the virtual film thickness distribution And a step of setting S40, and a planarization step S50 of locally dry etching the entire surface of the semiconductor layer based on the distribution of the target etching amount. [Selected figure] Figure 3B.

Description

  The present invention relates to a method of manufacturing a semiconductor wafer, and more particularly to a method of manufacturing an SOI (Silicon on Insulator) wafer in which a semiconductor layer is formed on a surface of a silicon wafer serving as a support substrate via an insulating film.

As semiconductor wafers, silicon wafers made of single crystal silicon and bulk wafers made of compound semiconductors such as GaAs (hereinafter sometimes referred to as "bulk wafers") are known. In addition, an epitaxial wafer is known in which an epitaxial layer is formed on the surface of such a bulk wafer using a CVD method or the like. Furthermore, there is known a semiconductor wafer in which an insulating film such as a SiO ₂ layer is provided on the surface of a bulk wafer, and a semiconductor layer (called an active layer) to be a semiconductor device formation region is formed via the insulating film. Wafers having these various structures are used properly depending on the semiconductor devices to be formed.

In particular, in recent years, SOI wafers having an SOI (Silicon on Insulator) structure have attracted attention in the field of highly integrated CMOS devices, high breakdown voltage devices, and further image sensors. The SOI wafer has a structure in which an insulating film such as silicon oxide (SiO ₂ ) and a semiconductor layer such as a single crystal silicon layer used as a device active layer are sequentially formed on a supporting substrate. Although the bulk silicon substrate has a relatively large parasitic capacitance that can be generated between the element and the substrate, the parasitic capacitance is greatly reduced in the SOI wafer, so the device can be faster, the withstand voltage can be increased, the power consumption can be reduced, etc. Can be realized.

  One of the representative methods of manufacturing such SOI wafers is a bonding method. In this bonding method, an insulating film is formed on at least one of the supporting substrate wafer and the active layer wafer, and then these wafers are bonded via the insulating film, and then heat treatment is performed at a high temperature of about 1200.degree. Apply. Then, the wafer for active layer is thinned by grinding and polishing to obtain an active layer having a desired film thickness, whereby an SOI wafer is obtained.

  Here, in order to thin the wafer for active layer after bonding to obtain an active layer having desired film thickness and film thickness uniformity, the local dry etching such as the above-mentioned grinding and polishing and plasma etching are used in combination. There is a thing. For example, in Patent Document 1, a polishing process for polishing the surface of the active wafer after bonding, a wafer thickness measurement process for measuring the thickness of the entire area of the active layer after polishing, and the obtained thickness data Based on the foregoing, there is disclosed a method of manufacturing a bonded SOI substrate including a plasma etching step of plasma etching a polished active layer. In Patent Document 1, high film thickness uniformity is realized by adjusting the moving speed of the plasma generating electrode position of the plasma etching apparatus according to the thickness data.

Unexamined-Japanese-Patent No. 2004-235478

  As described in Patent Document 1, prior to planarizing the entire surface of the semiconductor layer by local dry etching, the thickness of the entire semiconductor layer is measured, and etching by local dry etching is performed based on the measurement results. Adjusting the amount at various places in the surface to enhance the film thickness uniformity and performing the planarization process is referred to as “in-plane etching amount adjustment planarization process method”. By the in-plane etching amount adjustment flattening processing method, the film thickness uniformity of the semiconductor layer after local dry etching is performed on the entire surface of the semiconductor layer can be improved to a considerable extent. In fact, by performing plasma etching according to Patent Document 1, it is possible to make the film thickness tolerance of the active layer within ± 0.3 μm. However, with the miniaturization of semiconductor devices in recent years, the required level of film thickness tolerance of the semiconductor layer after local dry etching is within ± 0.10 μm or even ± 0.05 μm as thickness tolerance. It is getting tougher. Therefore, in order to further improve the film thickness tolerance of the semiconductor layer after the local dry etching, establishment of a technique capable of further improving the film thickness uniformity at the stage after the local dry etching is desired.

  Therefore, in view of the above problems, the present invention provides a method of manufacturing a semiconductor wafer capable of enhancing the film thickness uniformity of a semiconductor layer after planarization in a method of manufacturing a semiconductor wafer to be planarized using a local dry etching method. Intended to be provided.

  The present inventors diligently studied to solve the above problems. As described above, when the in-plane etching amount adjustment flattening processing method is used to obtain the SOI wafer, the thickness of the entire active layer of the SOI wafer is measured, and the active layer is measured based on the obtained thickness data. Local dry etching is performed by plasma etching. Theoretically, although the in-plane uniformity seems to be sufficient by the in-plane etching amount adjustment and flattening processing method, considering the film thickness distribution after actual processing, it is considered that processing uneven distribution occurs after local dry etching Be

  According to the inventors of the present invention, when the in-plane etching amount adjustment flattening process is performed, the processing tendency of the device changes with time, and further, the processing tendency changes when material replacement of the device is performed. But this time it turned out anew. In the local dry etching in this in-plane etching amount adjustment flattening processing method, plasma etching is performed by moving the nozzle in the X axis direction and the Y axis direction without rotating the wafer to be processed (see FIG. 1A). Specifically, as shown in FIG. 1A, the processing is advanced in the Y direction, moved in the X direction at a predetermined pitch, and further advanced in the Y direction, and this is repeated. Therefore, even if there is processing-specific uneven distribution unique to the apparatus, concentric uneven distribution does not occur. In addition, since the uneven processing distribution actually observed may be local, it is difficult to determine whether the uneven distribution due to the apparatus or the uneven distribution due to the wafer is present even if the measurement result is confirmed. Moreover, even if uneven distribution could be specified as the plasma etching device origin, it was also confirmed that if the wafer is polished after plasma etching (the wafer is polished while being polished), correction can not be made.

  Hereinafter, the X axis (X direction) and the Y axis (Y direction) in the present specification will be defined with reference to FIG. 1A. As used herein, the Y-axis is a direction parallel to the direction from the wafer notch or orientation flat toward the wafer center, and the X-axis is orthogonal to the Y-axis.

  Now, in order to further investigate the change in processing tendency at the time of material change and material exchange, the present inventors, unlike the in-plane etching amount adjustment flattening processing method, perform local dry etching regardless of thickness data. The etching amount distribution in the case of performing equal amounts of the entire surface of the active layer was investigated. As described above, in order to carry out local dry etching with an equal amount on the entire surface of the active layer, it is sufficient to scan the stage for scanning the SOI wafer at a constant speed while keeping the etching rate of the local dry etching apparatus constant. Below, it calls "constant speed processing."

  FIG. 1B shows cross section data of etching amounts in the X-axis direction and the Y-axis direction when processed at a constant speed using a local dry etching machine at a predetermined time. In FIG. 1B, the notch of the wafer is also illustrated, and the same applies to the following. Further, FIG. 1C shows cross section data of etching amounts in the X-axis direction and the Y-axis direction when constant velocity processing is performed using the same local dry etching apparatus after half a year from FIG. 1B. Further, in FIG. 1D, the amount of etching in the X-axis direction and the Y-axis direction when constant velocity machining is performed after parts replacement (specifically, a discharge tube and a nozzle for discharge) to the same local dry etching device. Shows cross section data of

  According to FIG. 1B, it can be confirmed that a substantially uniform etching amount can be obtained except for the wafer edge by constant velocity processing in both the X-axis direction and the Y-axis direction. On the other hand, according to FIG. 1C, while a substantially uniform etching amount can be obtained in the Y-axis direction, the etching amount is small in the first half of processing despite the constant velocity processing in the X-axis direction. It can be confirmed that the amount of etching is large (that is, the amount of etching is rising to the right). Further, according to FIG. 1D, although a substantially uniform etching amount can be obtained in the Y-axis direction, the etching amount is large in the first half of the processing despite the constant velocity processing in the X-axis direction. It can be confirmed that the etching amount is small (that is, the etching amount falls to the right). In FIG. 1B, strictly speaking, the amount of etching decreases in the second half of the processing, which corresponds to falling to the right.

  Based on the results of FIGS. 1B to 1D, if the same local dry etching machine is continuously used or if parts are replaced, the processing tendency changes even if constant velocity processing is performed. It was confirmed.

  Moreover, FIG. 2 is a figure which shows an example of film thickness distribution after planarizing processing by in-plane etching amount adjustment planarization processing method using said local dry etching processing machine. As shown in FIG. 2, a locally high portion with a film thickness of about 0.1 μm to 0.2 μm is formed in a circumferential partial region of the wafer peripheral portion (in other words, the etching amount is It was also found that there may be less).

  As described above, when the in-plane etching amount adjustment / flattening method is performed using the local dry etching apparatus, the processing amount (etching amount) in the plane can be obtained depending on the secular change of the local dry etching machine or the timing of component replacement. Uneven distribution may occur. Therefore, in order to offset the uneven distribution of the processing amount, the inventor grasps the processing tendency of the local dry etching apparatus, and considers the virtual film thickness distribution taking into consideration the processing tendency and the film thickness distribution of the active layer to be processed. It was conceived to improve the in-plane etching amount adjustment flattening processing method by setting. Then, it has been found that the tolerance of the film thickness distribution after planarization processing can be improved by using this hypothetical film thickness distribution. Furthermore, the present inventors have found that the method using this virtual film thickness distribution is not limited to the case of planarizing the active layer of the SOI wafer, but is applicable to the case of locally dry etching the entire surface of the semiconductor layer. The present invention has been completed. That is, the gist configuration of the present invention is as follows.

(1) A method of manufacturing a semiconductor wafer, comprising: a semiconductor layer forming step of forming a semiconductor layer on one side of a semiconductor wafer for support substrate; and a planarization step of planarizing the entire surface of the semiconductor layer by a local dry etching method. And
A processing tendency acquisition step for determining the processing tendency of the planarization apparatus using the local dry etching method;
A pre-processing film thickness distribution measuring step of measuring a film thickness distribution before flattening processing of the semiconductor layer;
A virtual film thickness distribution setting step of setting a virtual film thickness distribution of the semiconductor layer based on the processing tendency and the film thickness distribution before processing;
A target etching amount distribution setting step of setting a target etching amount distribution based on the target film thickness distribution and the virtual film thickness distribution of the semiconductor layer after planarization processing in the planarization device;
And D. a planarization step of performing local dry etching on the entire surface of the semiconductor layer by the planarization device based on the set target etching amount distribution.

(2) The method for manufacturing a semiconductor wafer according to (1), wherein the processing tendency is obtained based on the planarization processing results of a plurality of sample semiconductor wafers in the processing tendency acquisition step.

(3) The method for manufacturing a semiconductor wafer according to (1) or (2), further including a thinning step of thinning the semiconductor layer between the semiconductor layer forming step and the planarization step.

(4) The semiconductor wafer for support substrate is a silicon wafer,
The method for manufacturing a semiconductor wafer according to any one of the above (1) to (3), wherein the silicon wafer is bonded to the semiconductor layer through an insulating film in the semiconductor layer forming step.

(5) The method for producing a semiconductor wafer according to (4), wherein the semiconductor layer is a single crystal silicon layer.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor wafer which can improve the film thickness uniformity of a semiconductor layer can be provided.

It is a schematic diagram explaining the X-axis and Y-axis in local dry etching. It is a graph which shows the cross section data of the amount of etching when constant velocity processing is performed at predetermined | prescribed time by experiment of this inventor. It is a graph which shows the cross section data of the amount of etching when constant velocity processing is performed at the half year progress from predetermined | prescribed time by experiment of this inventor. It is a graph which shows the cross section data of the amount of etching when equal velocity processing is performed after replacement | exchange of components of a local dry etching apparatus by experiment of this inventor. It is a figure which shows an example of the uneven distribution position of film thickness distribution when the in-plane etching amount adjustment planarization process by this inventor's experiment is performed. It is a schematic cross section explaining the manufacturing method of the semiconductor wafer by one embodiment of the present invention. It is a flowchart explaining the manufacturing method of the semiconductor wafer by one Embodiment of this invention. It is the cross section data of the direction of the X-axis which shows an example of the processing tendency of a local dry etching device. It is a graph which shows an example of the amount of correction in the direction of the X-axis for setting the virtual film thickness distribution in the case of the example of FIG. 4A. It is a contour map which shows an example of the X-axis direction correction amount for setting virtual film thickness distribution in the case of an example of FIG. 4A. It is a schematic diagram and a graph showing an example of a diameter direction amendment quantity for setting up hypothetical film thickness distribution, when processing partial distribution arises in a partial peripheral direction field of a wafer edge part. It is a schematic diagram and a graph which show an example of the amount of peripheral direction amendments for setting up hypothetical film thickness distribution, when processing partial distribution arises in a partial peripheral direction field of a wafer edge part. It is a contour map which shows an example of the radial direction and circumferential direction correction amount for setting virtual film thickness distribution in the case of an example of FIG. 5A and 5B. It is a contour map and histogram which show the film thickness distribution of the active layer before local plasma etching by Example 1. FIG. It is a contour map and histogram which show film thickness distribution of the active layer before local plasma etching by Example 2. FIG. It is a contour map and histogram which show the film thickness distribution of the active layer after local plasma etching by Example 1. FIG. It is a contour map and histogram which show the film thickness distribution of the active layer after local plasma etching by Example 2. FIG. It is a contour map and a histogram which show film thickness distribution of the active layer before local plasma etching by a prior art example 1. FIG. It is a contour map and a histogram which show film thickness distribution of the active layer before local plasma etching by a prior art example 2. FIG. It is a contour map and a histogram which show film thickness distribution of the active layer after local plasma etching by a prior art example 1. FIG. It is a contour map and histogram which show the film thickness distribution of the active layer after local plasma etching by the prior art example 2. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, a method of manufacturing a semiconductor wafer 100 having an SOI structure will be described as one embodiment according to the present invention with reference to FIG. 3A. In FIG. 3A, the thickness of the semiconductor wafer 10 for support substrate, the insulating film 20, the wafer 30A for active layer, and the semiconductor layers 30B, 30C, and 30D is exaggerated to be different from the actual thickness ratio for simplification of the drawing. Show.

  As shown in FIG. 3A, in order to manufacture the semiconductor wafer 100 having the SOI structure, the supporting substrate semiconductor wafer 10 is prepared (step A), and the insulating film 20 is formed on one surface or the entire surface of the supporting substrate semiconductor wafer 10. The wafer 30A for active layer to be formed (Step B, single-sided formation in FIG. 3A) and to be a semiconductor layer after planarization may be bonded to the semiconductor wafer 10 for support substrate through the insulating film 20 (Step C). The active layer wafer 30A can then be thinned to obtain the semiconductor layer 30B before the local dry etching (step D). Then, the entire surface of the semiconductor layer 30B is planarized by the local dry etching method to obtain the semiconductor layer 30C after the local dry etching (step E). Furthermore, the semiconductor layer 30C can be finish-polished to obtain the semiconductor layer 30D after finish-polishing, and the finished semiconductor wafer 110 can be manufactured.

  In addition, it can be said that the semiconductor layer formation process of forming a semiconductor layer in the single side | surface side of the semiconductor wafer for support substrates corresponds to above-mentioned step A thru | or step D. FIG. Also, in general, the semiconductor layer 30C after the local dry etching or the semiconductor layer 30D after the final polishing becomes an active layer of the SOI wafer.

  Next, the manufacturing method according to the present invention will be described in more detail with reference to the flowchart of FIG. 3B. For the reference numerals, refer to FIG. 3A as well. In the present embodiment, the following steps are performed in step E described above. That is, in the manufacturing method of the present embodiment, the processing tendency acquisition step S10 for obtaining the processing tendency of the planarization apparatus using the local dry etching method, and the film thickness distribution before the planarization processing of the semiconductor layer (that is, the film of the semiconductor layer 30B) Thickness distribution measurement step S20 for measuring thickness distribution), virtual thickness distribution setting step S30 for setting a virtual thickness distribution of semiconductor layer 30B based on processing tendency and thickness distribution before processing, and planarization processing A target etching amount distribution setting step S40 of setting a target etching amount distribution based on a target film thickness distribution and a virtual film thickness distribution of the subsequent semiconductor layer (that is, the semiconductor layer 30C) in a planarization apparatus, and a target etching amount distribution set And performing a planarizing step S50 in which the entire surface of the semiconductor layer 30B is locally dry-etched by the planarizing device. The details of each step will be sequentially described below.

<Machining tendency acquisition process S10>
First, in the processing tendency acquisition step S10, the processing tendency of the planarization apparatus using the local dry etching method is determined. As such a planarization apparatus, dry planarization apparatuses such as Speedfam's DCP (Dry Chemical Planarization) and PACE (Plasma Assisted Chemical Etching) manufactured by the company are known, and in addition, GCIB (gas cluster ion beam) is used. Even flattening processing is possible. Various techniques can be applied to determine the processing tendency of the planarization apparatus. For example, the processing result immediately before performing the processing for obtaining the semiconductor wafer 100 according to the present embodiment can be used. That is, the above-mentioned in-plane etching amount adjustment flattening processing method is performed on one sample wafer, and the difference between the target film thickness distribution and the film thickness distribution of the processing result is compared based on the flattening processing result. Then, the processing tendency of the planarization apparatus can be determined. Further, in order to make the processing tendency apparent, it is preferable to obtain the processing tendency based on the planarization processing result of a plurality of sample semiconductor wafers rather than one sheet. In addition, the processing tendency of the planarization apparatus can be obtained every predetermined period (for example, every week, every month), and can be used as the processing tendency to be used for the next predetermined period. In addition, the etching rate of the sample wafer is scanned at a constant speed over the entire surface of the sample wafer while the etching rate of the local dry etching apparatus is kept constant, and the in-plane distribution of the etching amount is measured. It is also possible to confirm the uneven distribution in the in-plane distribution of Above all, it is preferable to planarize the plurality of sample wafers by the in-plane etching amount adjustment flattening processing method, acquire the difference from the target film thickness distribution, and acquire the processing tendency. By performing processing on a plurality of sheets, it becomes easy to distinguish processing uneven distribution caused by a wafer or uneven distribution caused by local dry etching. Moreover, it is also because it is difficult to acquire the tendency of the circular-arc-shaped convex shape illustrated by FIG. 2 in constant-velocity processing.

<Processing thickness distribution measurement step S20 before processing>
Aside from the processing tendency acquisition step S10 described above, a pre-processing film thickness distribution measurement step S20 of measuring the film thickness distribution of the semiconductor layer 30B is performed. In this step S20, the measurement may be performed using a film thickness distribution measuring device incorporated in the planarization apparatus, or the film thickness of the semiconductor layer 30B using a film thickness distribution measuring device other than the planarization apparatus. The distribution may be measured. An appropriate measurement method may be used depending on the material and thickness of the semiconductor layer. In the case of measuring the film thickness distribution of the semiconductor layers 30B and 30C (that is, the active layer) of the SOI wafer, a film thickness measuring device using a commercially available reflection spectroscopy, a spectroscopic ellipsometry film thickness measuring device, or the like can be used.

<Virtual Film Thickness Distribution Setting Step S30>
Next, a virtual film thickness distribution of the semiconductor layer 30B is set based on the processing tendency obtained in the processing tendency acquisition process S10 and the film thickness distribution before processing obtained in the film thickness distribution measurement process S20 before processing. That is, in order to offset the influence of uneven processing when planarizing the entire surface of the semiconductor layer 30B by local dry etching using a planarization apparatus, the processing tendency is made relative to the film thickness distribution actually measured in step S20. Set the hypothetical film thickness distribution in consideration. For example, in the case where there is a tendency for a partial region in a plane after planarization processing to be convex as a processing tendency, it means that the etching amount of that portion is small. Therefore, in the virtual film thickness distribution, the virtual film thickness distribution in which the film thickness of the partial region is increased is set, and in the planarization processing step, the scanning speed is adjusted to be flat so that the etching amount of the region is large. Perform chemical processing. In general, since the etching rate per unit area of the planarization apparatus using the local dry etching method is constant, the etching amount is adjusted by adjusting the scanning rate.

  Steps S10 to S30 will be described with reference to specific examples of FIGS. 4A to 4C and 5A to 5C.

  FIG. 4A shows the film thickness distribution before and after the entire surface of the active layer of the SOI is planarized by the local dry etching method by the conventional in-plane etching amount adjustment planarization processing (that is, from the semiconductor layer 30B to the semiconductor layer Got 30 C). Processing is started by scanning in the Y-axis direction from -100 mm at the X-axis position, scanning in the positive direction of the X-axis at a predetermined pitch and folding back in the Y-axis direction, and this is repeated to +100 mm at the X-axis position. Finished processing at the position of. From the cross section data in the X-axis direction of film thickness distribution after flattening processing, the film thickness is smaller than the average film thickness in the first half of processing (X axis position minus side) (more etching amount), the second half of processing (X axis position plus On the side), the film thickness is larger (the etching amount is smaller) than the average film thickness. Therefore, as the processing tendency in this case, it is confirmed that as the processing progresses, the etching amount falls to the right in the X-axis direction with respect to the target etching amount.

  In the case of this example, after measuring the film thickness distribution of the active layer to be actually processed, with respect to the film thickness distribution (that is, the film thickness distribution before processing), as shown in FIG. The hypothetical film thickness distribution may be set by adding the film thickness correction amount of the shoulder rising. For the entire film thickness distribution in the plane, as shown in the contour map of FIG. 4C, the film thickness correction may be performed only in the X-axis direction, and when there is uneven processing in the Y-axis direction, Furthermore, the processing uneven distribution may be taken into consideration. Thus, a hypothetical film thickness distribution can be obtained. If local dry etching is performed on this hypothetical film thickness distribution, processing uneven distribution is offset and the final film thickness uniformity is improved.

  Further, as shown in FIG. 2 described above, when there is uneven processing in a circumferential partial area of the wafer peripheral portion, the film thickness distribution of the active layer to be actually processed is measured and then the film thickness distribution (ie, processing The virtual film thickness distribution may be set by adding the film thickness correction amount in the radial direction (see FIG. 5A) and the film thickness correction amount in the circumferential direction (see FIG. 5B) to the front film thickness distribution). When the film thickness correction amount shown in FIGS. 5A and 5B is applied to the entire film thickness distribution in the plane, the contour map in FIG. 5C is obtained.

<Target etching amount distribution setting step S40>
Following the virtual film thickness distribution setting step S30, a target etching amount distribution setting step S40 is performed. In this process, a target etching amount distribution based on the target film thickness distribution and the virtual film thickness distribution of the semiconductor layer (that is, the semiconductor layer 30C) after the planarization processing is set in the planarization apparatus. The target etching amount distribution is the difference between the target film thickness distribution and the virtual film thickness distribution.

<Planarization step S50>
Then, following the target etching amount distribution setting step S40, the entire surface of the semiconductor layer 30B is locally dry-etched by the planarization apparatus based on the target etching amount distribution set in the step S40 to obtain the semiconductor layer 30C. Since the processing tendency of the planarization apparatus is taken into consideration in the target etching amount distribution, the semiconductor layer 30C after planarization can be improved as compared with the conventional in-plane etching amount adjustment planarization processing method. Therefore, according to this embodiment, the semiconductor wafer 100 having high film thickness uniformity can be manufactured.

  Hereinafter, specific embodiments of the aforementioned steps A to D and step E (FIG. 3A) for manufacturing the semiconductor wafer 100 having the SOI structure will be described.

  As the semiconductor wafer 10 for support substrates prepared in Step A, a single crystal silicon wafer made of silicon single crystal can be used. As the single crystal silicon wafer, a single crystal silicon ingot grown by the Czochralski method (CZ method) or the floating zone melting method (FZ method) can be sliced by a wire saw or the like. In addition, carbon and / or nitrogen may be added to the single crystal silicon wafer. Furthermore, any impurity may be added to make it n-type or p-type. In addition, the semiconductor wafer 10 for support substrate may be a bulk compound semiconductor other than silicon single crystal.

  In step B, the insulating film 20 can be provided on the surface of the supporting substrate semiconductor wafer 10 by performing heat treatment in an oxidizing atmosphere or the like. Further, the insulating film 20 is not limited to a silicon oxide film, and an electrical insulator can be used. For example, a silicon nitride film may be used as the insulating film 20, or diamond like carbon (DLC) may be used.

  In Step C, the active layer wafer 30A is bonded to the supporting substrate semiconductor wafer 10 through the insulating film 20. This bonding can be performed by a general method. The active layer wafer 30A is a wafer used as a device active layer of an SOI wafer, and a single crystal silicon wafer made of silicon single crystal can be used similarly to the semiconductor wafer 10 for support substrate, or an SiC single crystal It is also possible to use a support substrate semiconductor wafer 10 and a different substrate such as a layer.

  Although the insulating film 20 is formed on the supporting substrate semiconductor wafer 10 in FIG. 3A, the insulating film may be formed on the active layer wafer 30A in order to manufacture an SOI wafer. It is generally known that an insulating film may be formed on both the wafer 10 and the active layer wafer 30A, and the insulating film may be formed on both sides of the wafer, not only on one side of the wafer. .

  In step D, the semiconductor layer 30B before the local dry etching is obtained by a thinning process in which the active layer wafer 30A is thinned by grinding and polishing. Grinding can be performed by a general method such as mechanical grinding and chemical mechanical polishing. Generally, the removal allowance after thinning at this stage is several hundred μm (for example, 500 to 650 μm).

  The flattening process performed in step E is as described above. In addition, the removal allowance of the planarization process by local dry etching is about 0.5 micrometer-about 3.0 micrometers normally, and is significantly smaller than the removal allowance by step D. In addition, the surface of the semiconductor layer 30B subjected to step D is a mirror-polished surface, and planarization processing by local dry etching is performed on the mirror-polished surface.

  As described above, the semiconductor layer 30C may be further finish-polished by Step F, as desired. Since the polishing removal by finish polishing is usually 0.3 μm or less, for example, 0.1 to 0.2 μm, and even smaller than the removal in Step D, the film thickness uniformity and thickness of the semiconductor layer 30D of the semiconductor wafer 110 The tolerance is dominated by the processing result of planarization before finish polishing. Therefore, if the film thickness uniformity of the semiconductor layer 30C of the semiconductor wafer 100 is insufficient, the improvement effect of the film thickness uniformity of the semiconductor layer 30D after finish polishing is poor. On the other hand, if the film thickness uniformity of the semiconductor layer 30C is high, the amount of polishing at the time of final polishing can be made uniform within the surface, so that it is possible to obtain an accurate finished film thickness.

  In addition, when producing the semiconductor wafer 100,110 which has SOI structure, it is needless to say that the general technique used for producing a bonded wafer, such as bonding strengthening heat processing, can be applied.

  So far, the semiconductor wafer 100 having the SOI structure has been described in the above embodiment, but in the present invention, a semiconductor layer forming step of forming a semiconductor layer on one surface side of a semiconductor wafer for support substrate It is applicable to the manufacturing method of the semiconductor wafer including the planarization process which carries out the planarization process by a local dry etching method. For example, it is applicable also to the epitaxial wafer which formed the epitaxial layer in the surface of the semiconductor wafer for support substrates by CVD method etc. as a semiconductor layer formation process. In this case, when the surface of the epitaxial layer of the epitaxial wafer is locally dry etched, the steps S10 to S50 described above with reference to FIG. 3B are performed.

  Hereinafter, the present invention will be described in more detail using examples, but the present invention is not limited to the following examples.

Example 1
A silicon wafer with a diameter of 200 mm was prepared as a supporting substrate wafer and an active layer wafer. Next, the supporting substrate wafer was introduced into a thermal oxide film manufacturing apparatus, and an oxide film forming process was performed in an oxidizing atmosphere to form an insulating film made of a silicon oxide film on the supporting substrate wafer. Then, the wafer for active layer was bonded to the oxide film side of the wafer for support substrate. Then, the bonded wafers were transferred into a vertical heat treatment apparatus under an oxidizing atmosphere, and heat treatment for strengthening bonding was performed to obtain one bonded wafer. Thereafter, the wafer for active layer in the bonded wafer was ground and polished to thin the wafer for active layer, thereby obtaining an active layer (SOI film) before local dry etching. In this state, when the film thickness distribution of the active layer was measured using reflection spectroscopy, it was as shown by the contour map in FIG. FIG. 6 also shows a histogram of the SOI film thickness.

Example 2
As in Example 1, an active layer (SOI film) before local dry etching was obtained. In this state, the film thickness distribution of the active layer was measured in the same manner as in Example 1. As a result, the contour map in FIG. 7 was obtained. FIG. 7 also shows a histogram of the SOI film thickness.

  Planarization processing by local dry etching was performed on the active layer (SOI film) before local dry etching obtained in Examples 1 and 2 according to the flowchart described using FIG. 3B. First, DCP 200X manufactured by SpeedFam Corporation was used as a planarization apparatus. In order to confirm the processing tendency of the planarization apparatus, the previous planarization processing result was referred to. Then, it was confirmed that it is necessary to perform the film thickness correction on the upper right in the X-axis direction according to FIG. 4B and FIG. 4C. In addition, it was also confirmed that it is necessary to perform film thickness correction to compensate for the insufficient etching amount in a partial region in the circumferential direction of the wafer peripheral portion according to FIGS. 5A to 5C. Therefore, the film thickness correction was performed on the contour map of FIGS. 6 and 7, and the hypothetical film thickness distributions of the first and second embodiments were set. Thereafter, the target film thickness distribution of the active layer is set to a uniform thickness of 3.5 μm in the plane, and the target etching amount distribution set in the planarization apparatus from the difference with the virtual film thickness distribution (in-plane average etching amount is about 1 .5 μm) was set. Finally, on the basis of the set target etching amount distribution, the entire surface of the active layer was subjected to planarization processing by local dry etching.

  In Examples 1 and 2, the film thickness distribution after flattening processing and the histogram of the SOI film thickness are respectively shown in FIGS.

<Conventional Examples 1 and 2>
A bonded wafer was obtained in the same manner as in Examples 1 and 2. However, the thickness (SOI film thickness) of the active layer before the local dry etching was about 2.5 μm. 10 and 11 show the film thickness distribution and the histogram of the SOI film thickness before flattening processing in Conventional Examples 1 and 2, respectively.

  Although the same planarization apparatus as in Embodiments 1 and 2 was used, the active layer was planarized by the conventional in-plane etching amount adjustment planarization processing unlike the Embodiments 1 and 2. The in-plane average etching amount is about 1.5 μm. 12 and 13 show the film thickness distribution after flattening processing and the histogram of the SOI film thickness in the conventional examples 1 and 2, respectively.

  Further, according to the histograms in FIGS. 8, 9, 12 and 13, the film thickness tolerance in the wafer surface is ± 0.05 μm (the peripheral exclusion region Edge Exclusion is 5 mm) in Examples 1 and 2 and Conventional Examples 1 and 2. The occupancy rates of were compared. The results are as shown in Table 1 below. While the occupancy rate is 86 to 87% in the conventional examples 1 and 2, it is around 99% in the examples 1 and 2, and a dramatic improvement can be confirmed.

  From the comparison results of Examples 1 and 2 and Conventional Examples 1 and 2 above, it is confirmed that the film thickness uniformity of the semiconductor layer after planarization processing by local dry etching can be improved by applying the present invention. did it.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor wafer which can improve the film thickness uniformity of a semiconductor layer can be provided.

10 Semiconductor wafer 20 for support substrate Insulating film 30A Wafer for active layer 30B Semiconductor layer (before local dry etching)
30C semiconductor layer (after local dry etching)
30D semiconductor layer (after finish polishing)
100 semiconductor wafer 110 semiconductor wafer (after finish polishing)

Claims (4)

A semiconductor wafer manufacturing method comprising: a semiconductor layer forming step of forming a semiconductor layer on one side of a supporting substrate semiconductor wafer; and a planarization step of planarizing the entire surface of the semiconductor layer by a local dry etching method. ,
A processing tendency acquisition step for determining the processing tendency of the planarization apparatus using the local dry etching method;
A pre-processing film thickness distribution measuring step of measuring a film thickness distribution before flattening processing of the semiconductor layer;
A virtual film thickness distribution setting step of setting a virtual film thickness distribution of the semiconductor layer based on the processing tendency and the film thickness distribution before processing;
A target etching amount distribution setting step of setting a target etching amount distribution based on the target film thickness distribution and the virtual film thickness distribution of the semiconductor layer after planarization processing in the planarization device;
And D. a planarization step of performing local dry etching on the entire surface of the semiconductor layer by the planarization device based on the set target etching amount distribution.
In the processing tendency acquisition step, the processing tendency is determined from the difference between the target film thickness distribution of a plurality of sample semiconductor wafers and the film thickness distribution of the processing result,
The processing tends to seek in the machining tend acquisition step, the Rukoto be derived from at least one of continued use processing ubiquitous due to aging caused by and processing ubiquitous due to the component replacement of the flattening device flattening device A method of manufacturing a semiconductor wafer characterized by Wherein the semiconductor layer forming step between the planarization process, further comprising thinning step of thinning the semiconductor layer, a method of manufacturing a semiconductor wafer according to claim 1. The semiconductor wafer for the support substrate is a silicon wafer,
Wherein the semiconductor layer forming step, the silicon wafer with an insulating film bonded to the semiconductor layer, a method of manufacturing a semiconductor wafer according to claim 1 or 2. The method for manufacturing a semiconductor wafer according to claim 3 , wherein the semiconductor layer is a single crystal silicon layer.