JPH02102514A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To improve the coefficient of utilization of a semiconductor material by a method wherein the face of the ingot or the block of the semiconductor material of high quality, which becomes an active region, is processed into the state suitable for lamination, and on the other hand, the main surface of a water, which becomes a susceptor, is also processed so as to obtain the state suitable for lamination. CONSTITUTION:The edge face 11 of the ingot or the block 10 of a semiconductor substrate, forming an active region, is processed to obtain the surface suitable for lamination. On the other hand, one main surface of a water 20, which becomes a susceptor, is processed into the surface suitable for lamination. Then, after both of them are heat-treated and laminated, said ingot or block 10 is cut into the prescribed thickness, and the cut section is processed. As a result, the amount to be removed by grinding is reduced, the coefficient of utilization of the semiconductor material can be reduced. Also, the curve and the undulation of the laminated semiconductor substrate 30 can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor substrate for a semiconductor integrated circuit or a compound semiconductor thin film device, and in particular to an inexpensive method for manufacturing a semiconductor substrate formed by bonding two types of wafers. Regarding the manufacturing method.

[Conventional technology]

2. Description of the Related Art A method is known in which a semiconductor substrate is produced by bonding semiconductor wafers directly to each other with crystal planes or through dissimilar materials such as oxide films.

Related methods of this type include, for example, JP-A-62
-226640, JP-A No. 62-229820, and the like.

[Problem to be solved by the invention]

In all of the above conventional techniques, after bonding wafers together, at least one of the wafers is polished to form a thin piece to a predetermined thickness to form a semiconductor substrate. In particular, since the thickness of the wafer, which is the main active area, is several tens of micrometers to several micrometers, most of one wafer is removed by polishing after bonding, which results in an extremely low utilization rate of semiconductor materials, which is one of the causes of high costs. It is one.

An object of the present invention is to reduce costs by reducing the amount removed by polishing and increasing the utilization rate of semiconductor material. Another purpose is to reduce curvature and waviness of the bonded semiconductor substrates.

[Means to solve the problem]

The above purpose is to process the end faces of ingots or blocks of high-grade semiconductor material that will serve as active areas into a state suitable for bonding, and to process one main surface of a wafer that will serve as a support for sumo wrestlers into a state suitable for bonding. This is accomplished by bonding the two together by bringing them into close contact and heat-treating them, and then cutting the ingot or block to a predetermined thickness.

[Effect]

The utilization rates of semiconductor materials in the conventional wafer-to-wafer bonding method and the method in which a support wafer and a semiconductor material block serving as an active region are bonded and then cut are considered using a 6'φ Si single crystal as an example.

First, in the conventional method, ■ Si single crystal ■ Slicing (to form a wafer) ■ Chamfering ■ Lapping, etching, and polishing (A wafer with a specified thickness (approximately 500 μm) and a specified surface finish is completed.) ■ Support stand Lamination with a wafer for use ■ Lapping, etching, polishing (A semiconductor substrate with a predetermined thickness (several tens of μm to several μm) and a predetermined surface finish for devices is completed.) Here, ■ is approximately 400 μm, and ■ is approximately 400 μm. 50~100μ
A kerf loss of 1 m is generated, and only about 1000 500 μm thick wafers can be made from a 1 m long ingot. In addition, 450 to 500 .mu.rn is removed in (2), and a total of about 1 mm is discarded without being used in the device.

On the other hand, in the method of the present invention, ■ Si single crystal ingot ■ Wrapping, etching, polishing (one end surface is processed to make it suitable for lamination) ■ Lamination with a wafer for a support ■ Slicing ■ Wrapping, etching, polishing (A semiconductor substrate with a predetermined thickness (several tens of μm to several μm) and a predetermined surface finish for a device is completed.) The slicing surface of the Si single crystal ingot follows step (2).

Here, ■ is approximately 35 to 70 μm (less loss due to single-sided processing compared to conventional methods), and ■ is approximately 400 μm.
Only kerf loss of about 35 to 70 .mu.m in m and 2, totaling about 500 .mu.m, is generated, and the amount of semiconductor ingots thrown away can be halved compared to the conventional method.

Furthermore, since the ingot is bonded to the support wafer, the ingot is less likely to deform than the wafer, and almost no curvature or waviness occurs due to bonding.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

Dear Father, Figure 1 is a schematic cross-sectional view of the manufacturing process of a dielectric isolation substrate for a Si integrated circuit.

FIG. 1(a) shows a Si single crystal block serving as an active region and a Si wafer sealing serving as a support. The Si single crystal block 10 has a manufacturing method C7, an n-type conductivity, a dopant phosphorus, a resistivity of 30 to 35 Ω, a crystal plane orientation (100), and a diameter of 5'φ.

This is done by cutting off both ends of the ingot, grinding the outer periphery,
After forming the orientation flat, the end face 11 is given a super mirror finish. The Si wafer roof serving as the support was cut from the same block as above, the surface finish was super mirror finish on one side, and the thickness was 500±5 μm. Thereafter, it was oxidized in a steam stream at 1150° C. for 3.5 hours to form a 5iOz film 21 with a thickness of 1.5 μm on the surface.

In FIG. 1(b), both the ↓ stand and the main stand are brought into close contact with each other, and an infrared lamp 40 is used from the wafer side of the support stand.

The state is shown after being heated to about 650'C and bonded.

FIG. 1(c) shows a state in which a Si single crystal block is cut and then both sides of the cut are finished with a super mirror finish.

The Si single crystal block was sliced to a thickness of 600 μm, including the thickness of the support wafer, using an inner peripheral blade. In other words, the thickness of the Si single crystal that becomes the active region is 100μ.
It is m. Then wrap the cut surface in the usual way,
Etching with a mixture of hydrofluoric acid and nitric acid and mirror polishing were performed to reduce the thickness of the Si single crystal layer 12, which will become the active region, to 35 mm.
It was set to ±2 μm. At this time, the curvature of the bonded semiconductor substrate is 5 μm or less. Also, the cut surface 11' of the Si single crystal block is similarly lapped and etched.

Mirror polishing was performed to make it suitable for the next attachment of the support base.

GaAs on Si single crystal used in integrated optical devices
A substrate on which M was formed was created.

The GaAs single crystal ingot was grown using the three-temperature horizontal Bridgman method, and was square (D-shaped) with a cross-sectional area of 20 aJ.
Crystal orientation <111>, no dopant, etch pit density I x 10'ca-2. The end faces were polished with #4000 carborundum and then mechanochemically polished using a sulfuric acid-hydrogen peroxide mixture at 50 to 70°C.

The wafer for the support stand is a Si single crystal wafer manufactured by CZ, crystal orientation (100), diameter 2'φ, thickness 450 μm2, and has a super mirror finish surface.

Next, the polished end face of the GaAs single crystal ingot was brought into close contact with the Si single crystal wafer for the support stand, and the S
i The single crystal wafer was heated to about 600'C from the side using an infrared lamp and bonded.

For cutting the GaAs single crystal ingot, #4000 carborundum was used as the abrasive and a wire saw with a diameter of 0.08φ was used to reduce processing loss. At this time, Si
The thickness of the GaAs bonded to the single crystal wafer support is 60 μm.

The cut surface of the GaAs was mechanochemically polished in the same manner as the end face processing of the ingot described above. As a result, GaA
The thickness of s was 15±2 μm.

Ga As has an interfold plane at (110) and is very easy to break, so it is usually made into a wafer with a thickness of 500 to 700 μm.
The thickness of the material is required, and the utilization efficiency is poor.

According to the present invention, the utilization rate of expensive GaAs single crystal ingots can be significantly improved.

〔Effect of the invention〕

Dielectric isolation substrate for Si semiconductor integrated circuit, 5OI (Sil
icon on In5lator) -LSI
Bonded semiconductor substrates are widely used in applications such as , tertiary elements, power devices, and photo-electrical conversion transducers, and cost reduction is desired.

According to the present invention, the utilization rate of expensive semiconductor single crystal ingots can be increased by more than double, and it can greatly contribute to cost reduction of bonded semiconductor substrates. Moreover, curvature of the wafer in the bonding process can also be prevented.

In the embodiment of the present invention, a Si single crystal ingot (block), a Si single crystal wafer with an oxide film formed thereon, a GaA
Although we have given an example of direct bonding of an S single crystal ingot and a Si single crystal wafer, expensive compound semiconductors,
It is also possible to use a wafer partially formed with active elements as a support, and various inorganic/organic adhesives and metal solders as a bonding method.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing the steps of an embodiment of the present invention. 10... Semiconductor inboard 1~. 11... end surface, 20
... Wafer for support stand, 30... Bonded semiconductor substrate.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor substrate comprising bonding together a thin semiconductor serving as an active region and a thick wafer mainly functioning as a support for supporting the thin semiconductor, comprising: (1) an active region; (2) Processing one main surface of the wafer, which will mainly serve as a support base, to a surface condition suitable for bonding; A method for manufacturing a semiconductor substrate, comprising the steps of: 3) bonding the above two together; and (4) cutting the above ingot or block to a predetermined thickness and processing the cut surface.