JPH07249573A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To provide a method to flatten effectively a substrate, which is formed by growing a compound semiconductor layer on a semiconductor substrate, without changing the characteristics of the semiconductor substrate. CONSTITUTION:An Si substrate 1 is previously held processed into a projected form or a recessed form by an amount (b) to correspond to the amount of warpage of the substrate at the time when a GaAs layer is grown on this Si substrate and the GaAs layer 7 is grown on the substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate composed of a plurality of different types of semiconductor layers.

[0002]

2. Description of the Related Art Generally, when a material different from the substrate, for example, a compound semiconductor such as gallium arsenide (hereinafter referred to as GaAs) is grown on a semiconductor substrate such as silicon (hereinafter referred to as Si) (so-called heteroepitaxial growth), In general, as described in page 1, right column, line 18 to page 2, upper left column, line 6 of JP-A-62-196813, Ga is generally used.
Since the thermal expansion coefficient of the compound semiconductor such as As is larger than the thermal expansion coefficient of the semiconductor substrate such as Si, the growth temperature of the compound semiconductor (for example, 400 to 700 ° C.) to the room temperature (25
When the temperature is lowered to about (° C.), a strong tensile stress is applied to the compound semiconductor layer, which causes a problem that the manufactured substrate warps concavely in the direction of the growth surface. Taking the substrate (hereinafter referred to as GaAs / Si substrate) in which a GaAs layer is epitaxially grown on a Si substrate as an example, the degree of warpage is, for example, a 3-inch substrate (Si substrate thickness of about 400 μm).
m, the thickness of the GaAs layer is about 3 μm, about 50 μm, and the 4-inch substrate (the thickness of the Si substrate is about 600 μm, Ga
The thickness of the As layer is about 3 μm) and is about 100 μm. Since an integrated circuit or the like is formed on a substrate, especially when forming a large-scale integrated circuit on a large-area substrate with the rapid progress of semiconductor integrated circuit technology as in today's world, Si and G
There is a strong demand to reduce the warp of the wafer due to the difference in thermal expansion coefficient from aAs and to secure a high degree of flatness on the substrate surface.

Therefore, as a conventional method for flattening a substrate, for example, a method of forming a groove on the back surface of a semiconductor substrate of Si or the like and then growing a compound semiconductor layer of GaAs or the like on the surface of this semiconductor substrate (Japanese Patent Laid-Open No. Sho 61-96). 62-171112) or a method of growing a compound semiconductor layer such as GaAs on the surface of a semiconductor substrate such as Si after forming a back surface film such as a silicon oxide film (SiO ₂ ) on the back surface of the semiconductor substrate (see For example, see JP-A-62-196813).

[0004]

However, each of these conventional methods has the following drawbacks.
First, for example, in the method of forming a groove on the back surface of a Si substrate, the existence of the groove may reduce the strength of the substrate, and it is necessary to apply mechanical force to planarize the device when manufacturing it. It is not sufficient in terms of the effect of reducing the warp of the substrate. On the other hand, for example, on the back surface of the Si substrate, SiO
_In the method of forming the _two films, since the existence of the SiO ₂ film causes extra stress and the substrate is more likely to warp, the process of forming the SiO ₂ film (temperature and film thickness) so that the finished substrate becomes flat. ) Needs to be well controlled,
An error in the film thickness accuracy may occur due to etching or the like during the process of forming the SiO ₂ film, which may reduce the effect of reducing the warp of the substrate.

The present invention has been made in view of the above problems of the prior art, and effectively warps the substrate without deteriorating the strength of the substrate, increasing the stress in the substrate, and adding steps. An object of the present invention is to provide a method for manufacturing a semiconductor substrate that can be reduced.

[0006]

To achieve the above object, the present invention provides a first step of processing a semiconductor substrate into a convex shape or a concave shape, and a compound of a kind different from that of the semiconductor substrate on the surface of the semiconductor substrate. A second step of growing a semiconductor layer.

Preferably, in the first step, a step of preparing a semiconductor substrate having a thickness larger than a target thickness, a step of polishing one surface of the semiconductor substrate so that a central portion thereof is well shaved, and the semiconductor substrate And polishing the other surface so that the peripheral portion thereof can be shaved well.

The semiconductor substrate is processed into a convex shape when the compound semiconductor layer has a coefficient of thermal expansion larger than that of the semiconductor substrate, and the compound semiconductor layer has a coefficient of thermal expansion higher than that of the semiconductor substrate. If it is small, it is processed into a concave shape.

[0009]

According to the present invention, a semiconductor substrate having a predetermined thickness that is curved in a spherical shape is obtained by polishing one surface of each thicker semiconductor substrate in order so that the central portion and the peripheral portion can be scraped well. can get. When the thermal expansion coefficient of the compound semiconductor layer is larger than that of the semiconductor substrate, the convex surface is used as the surface, and when the thermal expansion coefficient of the compound semiconductor layer is smaller than that of the semiconductor substrate, the concave surface is used as the surface, and the compound semiconductor layer is formed on the surface. Therefore, when the temperature is lowered to about room temperature, in the former case, the stress that makes the semiconductor substrate concave due to the difference in the thermal expansion coefficient acts, and the force to return the semiconductor substrate curved in a convex shape to the original flat state is exerted. In the latter case, the stress which makes the semiconductor substrate convex due to the difference in the coefficient of thermal expansion acts and the force to return the concave semiconductor substrate to the original flat state works. Will result in a flat substrate.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method of the present invention will be described below with reference to the accompanying drawings. 1A to 1D and FIG.
(E) ~ (G) is a state diagram of the substrate for explaining the present embodiment. In this embodiment, S as a semiconductor substrate is used.
An example will be described in which a 3 inch GaAs / Si substrate is manufactured by epitaxially growing a GaAs layer as a compound semiconductor layer on an i substrate.

First, a process of processing a heteroepitaxial Si substrate for growing a GaAs layer will be described. First, as shown in FIG. 1A, in consideration of the polishing allowance, the thickness is thicker than the target thickness (400 μm) (600 to 5).
A Si epitaxial substrate 1 for heteroepitaxial growth is prepared. Specifically, according to a well-known semiconductor manufacturing technique, an ingot of a Si single crystal is manufactured by the Czochralski method (CZ method), etc., then both ends of the single crystal ingot are removed, and the outer periphery is ground to a predetermined diameter. Aligned with the orientation flat for position reference on the predetermined surface,
Then, it is cut (slicing) with a diamond inner peripheral blade to be processed into the above-mentioned thick wafer (600 to 500 μm).

Next, as shown in FIG. 1B, the back surface 2 of the Si substrate 1 is wrapped with a polishing table 3 and the back surface 2 of the Si substrate 1 is polished by lapping. Then, the surface 4 opposite to the back surface 2 (that is, the surface to be the front surface)
Is provided with a sticking jig 5 having a central portion protruding in a spherical shape, and the Si substrate 1 is relatively disposed through the sticking jig 5.
In the state in which is pressed against the polishing table 3, the Si substrate 1 and the polishing table 3 are relatively moved to polish the back surface 2 of the Si substrate 1. At this time, the Si substrate 1 is attached to the attachment jig 5 so as to be warped along its curved surface by applying a force,
As a result, the central portion of the back surface 2 is projected more than the peripheral portion, so that the central portion of the back surface 2 is polished so as to be scraped better than the peripheral portion. The protrusion amount a of the spherical surface of the sticking jig 5 is 40 in correspondence with the warp amount of the Si substrate described later.
It is preferably set to -60 μm. The result of this back surface polishing is as shown in FIG.

Then, as shown in FIG. 1D, the surface 4 of the Si substrate 1 is wrapped with a polishing table 3 and the surface 2 of the Si substrate 1 is polished by lapping. that time,
In the present embodiment, a sticking jig 6 having a flat surface is arranged on the back surface 2 side of the previously polished Si substrate 1, and the Si substrate 1 is relatively polished via the sticking jig 6. The surface 4 of the Si substrate 1 is polished by moving the Si substrate 1 and the polishing table 3 relative to each other while being pressed against the substrate 3. At this time, the Si substrate 1 is applied with force so that the back surface 2 is attached flat to the attachment jig 6, and as a result, the surface 4 is attached.
Since the peripheral part of the is projected more than the central part, the surface 4
The peripheral portion of is polished so as to be scraped better than the central portion.

The result of this surface polishing is as shown in FIG. That is, by the above steps, the Si substrate 1 for heteroepitaxial growth (thickness 400 μm) has a spherical shape, and the wafer central portion is lifted in the direction of the surface by about 50 μm (dimension b in the figure) above the peripheral portion. It is processed into a convex shape. Processing the Si substrate 1 into a convex shape in this way is
Coefficient of thermal expansion of GaAs layer to be grown later (about 6 × 10 ⁻⁶
/ deg) is the coefficient of thermal expansion of the Si substrate 1 (2.4 × 10 ^-6 / de
Since it is larger than g), when the temperature is lowered to about room temperature (25 ° C.), it becomes concave in the direction of the growth surface of the GaAs layer.
This is for obtaining the s / Si substrate. Therefore, the warp amount b of the Si substrate 1 to be processed is
It is set to a value corresponding to the amount of warpage of the GaAs / Si substrate when the substrate is used.

When the Si substrate 1 for heteroepitaxial processing is processed into a convex shape, as shown in FIG. 2F, a well-known semiconductor manufacturing technique is used to directly or on the surface 2 of the Si substrate 1. A GaAs layer 7 different from Si is grown by means of a vapor phase growth method (hereinafter referred to as MOCVD method) or a molecular beam epitaxial method (hereinafter referred to as MBE method) using an organometallic compound. Specifically, for example,
The hetero-epitaxial Si substrate 1 processed into a convex shape is put into an apparatus for growing a GaAs layer, and first about 900
After heat treating the Si substrate 1 at ℃ to clean the surface 4, MO
A thickness of 20 nm at a relatively low temperature of 400 to 450 ° C. for the CVD method and 150 to 400 ° C. for the MBE method.
About GaAs is deposited, the growth is temporarily stopped, and then the substrate temperature is set to the growth temperature of the GaAs layer of 650 to 750.
GaA with a thickness of about 3 μm
The s layer 7 is formed on the Si substrate 1 so that GaAs / Si
Make a substrate.

Then, when this substrate is cooled down to room temperature (25 ° C.), the convexly warped Si substrate 1 becomes concave due to the difference in thermal expansion coefficient between GaAs and Si. The force that cancels out, that is, the stress that becomes concave due to the difference in the coefficient of thermal expansion acts to return the Si substrate 1 that is warped in a convex shape to a flat surface, and finally becomes flat as shown in FIG. A GaAs / Si substrate will be obtained.

Therefore, according to this embodiment, GaAs
It becomes possible to effectively flatten the / Si substrate, and it becomes unnecessary to take special precautions and ingenuity (including a change in the device, etc.) against the warp of the substrate in various device processes.

Further, the Si substrate 1 for epitaxial use only needs to be processed into a convex shape in advance, and unnecessary processing is performed on the back surface or front surface of the Si substrate, such as forming grooves on the back surface of the Si substrate as in the prior art. Since there is no other film formed on the back surface of the Si substrate such as the formation of a SiO ₂ film on the back surface of the Si substrate, there is no increase in the stress inside the substrate and there is no flatness. GaAs /
The thickness of the Si substrate can be increased to the maximum determined by the mutual relationship between Si and GaAs. That is, flat Ga
The thickness of GaAs on the As / Si substrate is
The thickness can be increased up to a maximum thickness of 4 μm or more determined from the stress relationship with

Further, in terms of process easiness, the amount of warp of the Si substrate 1 is set to a predetermined value as in the present embodiment rather than controlling the film thickness of the SiO ₂ film on the back surface of the Si substrate as in the prior art. It is easier to process the Si substrate 1 to have a value, and in combination with the above-described flattening effect of the GaAs / Si substrate, the yield and reliability of the device can be improved.

In this embodiment, the warp amount of the Si substrate processed into a convex shape is 50 by taking a 3-inch Si substrate as an example.
.mu.m, but the Si substrate 1 to be processed as described above
The amount of warpage of GaAs when using a flat Si substrate
/ Si substrate is set to a value corresponding to the amount of warp. For example, a 4-inch Si substrate may be processed to have a warp amount of 100 μm and a 5-inch Si substrate may be processed to have a warp amount of 150 μm.

Further, in this embodiment, GaA is formed on the Si substrate.
Although the case of growing the s layer has been described, the present invention is not limited to this, and InP, GaP, A may be formed on the Si substrate.
It is also applicable when growing a compound semiconductor such as 1GaAs.

[0022]

According to the present invention, the semiconductor substrate is preliminarily processed into a convex shape or a concave shape by an amount corresponding to the amount of warpage of the substrate when the compound semiconductor layer is grown on the semiconductor substrate, and then the semiconductor substrate is processed into a convex shape or a concave shape. Since the compound semiconductor layer is grown, when the substrate is cooled down to room temperature, the substrate returns to a flat surface, and it is possible to effectively flatten the substrate without changing the characteristics of the substrate such as the strength and stress of the substrate. You can

Further, since it is only necessary to process the semiconductor substrate in advance, complicated process control is unnecessary,
A flat substrate can be obtained relatively easily.

Furthermore, since the stress in the substrate does not increase, the compound semiconductor layer can be grown to the maximum thickness on the semiconductor substrate.

[Brief description of drawings]

FIG. 1 is a state diagram of a substrate for explaining this embodiment.

FIG. 2 is a state diagram of a substrate for explaining the present embodiment as well.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Si substrate (semiconductor substrate) 2 ... Si substrate back surface 3 ... Polishing table 4 ... Si substrate surface 5, 6 ... Jig 7 for bonding GaAs layer (compound semiconductor layer)

Claims (3)

[Claims] 1. A first step of processing a semiconductor substrate into a convex shape or a concave shape, and a second step of growing a compound semiconductor layer of a kind different from that of the semiconductor substrate on a surface of the semiconductor substrate. And a method for manufacturing a semiconductor substrate. 2. The first step is a step of preparing a semiconductor substrate having a thickness larger than a target thickness, a step of polishing one surface of the semiconductor substrate so that a central portion thereof is well shaved, and a step of polishing the semiconductor substrate. 2. The method of manufacturing a semiconductor substrate according to claim 1, further comprising a step of polishing the other surface so that a peripheral portion thereof is well shaved. 3. When the thermal expansion coefficient of the compound semiconductor layer is larger than that of the semiconductor substrate, the semiconductor substrate is processed into a convex shape, and when the thermal expansion coefficient of the compound semiconductor layer is smaller than that of the semiconductor substrate. The method for manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor substrate is processed into a concave shape.