KR100511896B1 - Method of manufacturing soi substrate - Google Patents
Method of manufacturing soi substrate Download PDFInfo
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- KR100511896B1 KR100511896B1 KR10-1999-0024037A KR19990024037A KR100511896B1 KR 100511896 B1 KR100511896 B1 KR 100511896B1 KR 19990024037 A KR19990024037 A KR 19990024037A KR 100511896 B1 KR100511896 B1 KR 100511896B1
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- oxide film
- nitride film
- trench
- film
- semiconductor substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 51
- 150000004767 nitrides Chemical class 0.000 claims abstract description 44
- 238000005498 polishing Methods 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000007517 polishing process Methods 0.000 claims abstract 3
- 230000008569 process Effects 0.000 claims description 23
- 238000010438 heat treatment Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 238000000280 densification Methods 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000002002 slurry Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 238000002955 isolation Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 에스오아이(SOI) 기판의 제조방법에 관한 것으로, 특히, 균일한 두께의 반도체층을 얻을 수 있는 에스오아이 기판의 제조방법에 관한 것이다. 본 발명의 에스오아이 기판의 제조방법은, 벌크 실리콘으로 이루어진 반도체 기판을 제공하는 단계; 상기 반도체 기판 상에 제1열산화막 및 제1질화막을 순차적으로 형성하는 단계; 트렌치가 형성될 반도체 기판 부분이 노출되도록, 상기 제1질화막 및 제1열산화막을 패터닝하는 단계; 노출된 반도체 기판 부분을 식각하여, 소정 깊이의 트렌치를 형성하는 단계; 전체 상부에 소정 두께의 제2질화막을 형성하는 단계; 벽면에 제2질화막이 형성되어진 트렌치 내부에 산화막을 매립하는 단계; 노출된 제2질화막 부분과, 그 하부의 제1질화막 및 제1열산화막을 제거하는 단계; 전체 상부에 매몰산화막을 형성하는 단계; 상기 매몰산화막 상에 베이스 기판을 본딩하는 단계; 상기 트렌치 벽면에 잔류되어 있는 제2질화막을 연마정지층으로 하는 화학적기계연마 공정으로 상기 반도체 기판의 후면을 연마하는 단계; 및 잔류되어 있는 제2질화막을 제거하는 단계를 포함하여 이루어진다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a SOI substrate, and more particularly, to a method for manufacturing a SOH substrate capable of obtaining a semiconductor layer of uniform thickness. The method of manufacturing the SOH eye substrate of the present invention includes providing a semiconductor substrate made of bulk silicon; Sequentially forming a first thermal oxide film and a first nitride film on the semiconductor substrate; Patterning the first nitride film and the first thermal oxide film to expose a portion of the semiconductor substrate on which the trench is to be formed; Etching the exposed portion of the semiconductor substrate to form a trench of a predetermined depth; Forming a second nitride film having a predetermined thickness on the entire upper portion; Embedding an oxide film in the trench in which the second nitride film is formed on the wall surface; Removing the exposed second nitride film portion, the first nitride film and the first thermal oxide film under the exposed portion; Forming a buried oxide film over the entire surface; Bonding a base substrate on the investment oxide layer; Polishing a back surface of the semiconductor substrate by a chemical mechanical polishing process using the second nitride film remaining on the trench wall as a polishing stop layer; And removing the remaining second nitride film.
Description
본 발명은 에스오아이(SOI) 기판의 제조방법에 관한 것으로, 특히, 균일한 두께의 반도체층을 얻을 수 있는 에스오아이 기판의 제조방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a SOI substrate, and more particularly, to a method for manufacturing a SOH substrate capable of obtaining a semiconductor layer of uniform thickness.
반도체 소자의 고집적화 및 고성능화가 진행됨에 따라, 벌크 실리콘으로 이루어진 실리콘 기판을 대신하여 에스오아이(SOI : Silicon On Insulator) 기판을 이용한 반도체 집적 기술이 주목되고 있다. SOI 기판은 지지 수단인 베이스 기판과 소자가 형성될 반도체층 사이에 매몰산화막이 개재된 구조로서, 이러한 SOI 기판 상에 형성된 반도체 소자는 완전한 소자 분리와 기생 용량의 감소 및 고속 동작이 가능한 장점을 갖는다. As high integration and high performance of semiconductor devices have progressed, semiconductor integration technologies using a silicon on insulator (SOI) substrate have been attracting attention instead of a silicon substrate made of bulk silicon. The SOI substrate has a structure in which a buried oxide film is interposed between a base substrate, which is a supporting means, and a semiconductor layer, on which the device is to be formed. The semiconductor device formed on the SOI substrate has advantages of complete device isolation, parasitic capacitance reduction, and high speed operation. .
SOI 기판을 제조하기 위한 방법으로서는, 산소 이온주입을 이용하는 SIMOX(seperation by implanted oxygen)법과, 두장의 실리콘 기판을 매몰산화막의 개재하에 본딩시켜 제조하는 본딩법이 이용되어져 왔다. 그런데, SIMOX법을 이용한 SOI 기판의 제조방법은 소자가 형성될 반도체층의 두께 조절이 어렵고, 또한, 제조 시간이 길다는 단점이 있기 때문에, 최근에는 본딩법을 이용한 SOI 기판의 제조방법이 주로 이용되고 있다. As a method for producing an SOI substrate, a SIMOX (seperation by implanted oxygen) method using oxygen ion implantation and a bonding method in which two silicon substrates are bonded by interposing buried oxide films have been used. However, the method of manufacturing the SOI substrate using the SIMOX method has a disadvantage in that it is difficult to control the thickness of the semiconductor layer on which the device is to be formed, and the manufacturing time is long, so recently, the method of manufacturing the SOI substrate using the bonding method is mainly used. It is becoming.
본딩법을 이용한 SOI 기판의 제조방법을 간략하게 설명하면, 우선, 지지 수단인 베이스 기판, 또는, 반도체층을 얻기 위한 반도체 기판 중에서 어느 하나의 기판에 매몰산화막을 형성하고, 이어서, 매몰산화막의 개재하에 베이스 기판과 반도체 기판을 본딩시킨다. 그런다음, 반도체 기판 후면의 일부 두께를 공지된 기술인 화학적기계연마(Chemical Mechanical Polishing : 이하, CMP) 공정으로 제거하여, 소자가 형성될 반도체층을 얻는다. Briefly describing a method for manufacturing an SOI substrate using the bonding method, first, an investment oxide film is formed on any one of a base substrate as a support means or a semiconductor substrate for obtaining a semiconductor layer, and then intervening the investment oxide film. The base substrate and the semiconductor substrate are bonded together. Then, a part of the thickness of the back surface of the semiconductor substrate is removed by a known technique called Chemical Mechanical Polishing (CMP) to obtain a semiconductor layer on which the device is to be formed.
한편, 상기와 같은 본딩법을 이용한 SOI 기판의 제조방법에 있어서는, CMP 공정시에 연마정지층이 없기 때문에, 원하는 두께의 반도체층을 얻는데, 곤란함이 있었다. 따라서, 이러한 문제를 해결하기 위하여, 반도체 기판 내에 트렌치형 소자 분리막을 구비시키고, 이후, 상기 트렌치형 소자 분리막을 연마정지층으로 하는 CMP 공정을 수행하여, 원하는 두께의 반도체층이 얻어지도록 하는 방법이 제안되었다. On the other hand, in the manufacturing method of the SOI substrate using the above bonding method, since there was no polishing stop layer in the CMP process, it was difficult to obtain a semiconductor layer of desired thickness. Therefore, in order to solve such a problem, a method is provided in which a trench type device isolation film is provided in a semiconductor substrate, and thereafter, a CMP process using the trench type device isolation film as a polishing stop layer is performed to obtain a semiconductor layer having a desired thickness. Proposed.
도 1a 및 도 1b는 종래 기술에 따른 SOI 기판의 제조방법을 설명하기 위한 공정 단면도로서, 이를 참조해서 그 제조방법을 자세하게 설명하도록 한다. 1A and 1B are cross-sectional views illustrating a method of manufacturing a SOI substrate according to the prior art, and the method of manufacturing the SOI substrate will be described in detail with reference to the drawings.
우선, 도 1a에 도시된 바와 같이, 벌크 실리콘으로 이루어진 반도체 기판(1)을 마련하고, 상기 반도체 기판(1)의 표면에 소정 깊이의 트렌치(2)를 형성한다. 이때, 트랜치(2)는 소자가 형성될 반도체층의 두께와 유사한 깊이를 갖도록 형성한다. 그런다음, 트렌치(2) 내에 산화막(3)을 매립시키고, 전체 상부에 매몰산화막(4)를 형성한다. First, as shown in FIG. 1A, a semiconductor substrate 1 made of bulk silicon is provided, and a trench 2 having a predetermined depth is formed on the surface of the semiconductor substrate 1. At this time, the trench 2 is formed to have a depth similar to the thickness of the semiconductor layer on which the device is to be formed. Then, the oxide film 3 is embedded in the trench 2, and the buried oxide film 4 is formed over the whole.
다음으로, 도 1b에 도시된 바와 같이, 매몰산화막(4) 상에 베이스 기판(5)을 본딩시키고, 이어서, 반도체층(1a)이 얻어지도록, 트렌치(2)에 매립된 산화막(3)을 연마정지층으로 하는 CMP 공정으로 반도체 기판의 후면을 연마한다. 이 결과, 소자 분리막(6)을 갖는 SOI 기판(10)이 얻어진다.Next, as shown in FIG. 1B, the base substrate 5 is bonded onto the buried oxide film 4, and then the oxide film 3 embedded in the trench 2 is obtained so that the semiconductor layer 1a is obtained. The back surface of the semiconductor substrate is polished by a CMP process serving as a polishing stop layer. As a result, the SOI substrate 10 having the element isolation film 6 is obtained.
일반적으로, 상기와 같은 SOI 기판 상에 형성되는 반도체 소자의 특성은 소자가 형성될 반도체층의 두께 균일도에 크게 의존한다. 따라서, 본딩법을 이용하여 SOI 기판을 제조할 경우에는 반도체층의 두께 균일도를 확보하는 것이 무엇보다 중요하다. 그런데, 반도체 기판에 대한 CMP 공정시에는 산화막과 실리콘막, 즉, 반도체 기판간의 선택비가 크지 않는 것에 기인하여, 도 1b에 도시된 바와 같이, 반도체층(1a)의 표면에서 디싱(Dishing : D) 현상이 발생하게 되고, 이러한 디싱(D) 현상에 의해, 반도체층(1a)의 두께 균일도가 저하됨으로써, 소자 특성의 향상을 기대할 수 없고, 아울러, 후속 공정, 예컨데, 노광 공정 등의 어려움을 초래하게 되는 문제점이 있었다.In general, the characteristics of the semiconductor device formed on such an SOI substrate largely depend on the thickness uniformity of the semiconductor layer on which the device is to be formed. Therefore, when manufacturing the SOI substrate using the bonding method, it is most important to secure the thickness uniformity of the semiconductor layer. However, at the time of the CMP process with respect to the semiconductor substrate, the selection ratio between the oxide film and the silicon film, that is, the semiconductor substrate is not large, and as shown in FIG. 1B, dishing is performed on the surface of the semiconductor layer 1a (D). A phenomenon occurs, and the thickness uniformity of the semiconductor layer 1a is reduced by this dishing (D), so that improvement of device characteristics cannot be expected, and furthermore, difficulties in subsequent processes such as an exposure process are caused. There was a problem.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 균일한 두께의 반도체층을 얻을 수 있는 SOI 기판의 제조방법을 제공하는데, 그 목적이 있다. Accordingly, an object of the present invention is to provide a method of manufacturing an SOI substrate, which is devised to solve the above problems and to obtain a semiconductor layer having a uniform thickness.
상기와 같은 목적을 달성하기 위한 본 발명의 SOI 기판의 제조방법은, 벌크 실리콘으로 이루어진 반도체 기판을 제공하는 단계; 상기 반도체 기판 상에 제1열산화막 및 제1질화막을 순차적으로 형성하는 단계; 트렌치가 형성될 반도체 기판 부분이 노출되도록, 상기 제1질화막 및 제1열산화막을 패터닝하는 단계; 노출된 반도체 기판 부분을 식각하여, 소정 깊이의 트렌치를 형성하는 단계; 전체 상부에 소정 두께의 제2질화막을 형성하는 단계; 벽면에 제2질화막이 형성되어진 트렌치 내부에 산화막을 매립하는 단계; 노출된 제2질화막 부분과 그 하부의 제1질화막 및 제1열산화막을 제거하는 단계; 전체 상부에 매몰산화막을 형성하는 단계; 상기 매몰산화막 상에 베이스 기판을 본딩하는 단계; 상기 트렌치 벽면에 잔류되어 있는 제2질화막을 연마정지층으로 하는 CMP 공정으로 상기 반도체 기판의 후면을 연마하는 단계; 및 잔류되어 있는 제2질화막을 제거하는 단계를 포함하여 이루어진다. SOI substrate manufacturing method of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate made of bulk silicon; Sequentially forming a first thermal oxide film and a first nitride film on the semiconductor substrate; Patterning the first nitride film and the first thermal oxide film to expose a portion of the semiconductor substrate on which the trench is to be formed; Etching the exposed portion of the semiconductor substrate to form a trench of a predetermined depth; Forming a second nitride film having a predetermined thickness on the entire upper portion; Embedding an oxide film in the trench in which the second nitride film is formed on the wall surface; Removing the exposed second nitride film portion, the first nitride film and the first thermal oxide film under the exposed portion; Forming a buried oxide film over the entire surface; Bonding a base substrate on the investment oxide layer; Polishing a back surface of the semiconductor substrate by a CMP process using the second nitride film remaining on the trench wall as a polishing stop layer; And removing the remaining second nitride film.
본 발명에 따르면, 연마정지층으로서 실리콘막과 선택비가 우수한 질화막을 이용하기 때문에 반도체층의 표면에서 디싱 현상이 발생되는 것을 방지할 수 있으며, 이에 따라, 균일한 두께의 반도체층을 얻을 수 있다.According to the present invention, since the silicon film and the nitride film having excellent selectivity are used as the polishing stop layer, the dishing phenomenon can be prevented from occurring on the surface of the semiconductor layer, whereby a semiconductor layer having a uniform thickness can be obtained.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 SOI 기판의 제조방법을 설명하기 위한 공정 단면도이다. 우선, 도 2a에 도시된 바와 같이, 벌크 실리콘으로 이루어진 반도체 기판(11)을 마련하고, 상기 반도체 기판(11) 상에 20∼200Å의 제1열산화막(12) 및 700∼1,500Å의 제1질화막(13)을 순차적으로 형성한다. 그런다음, 트렌치가 형성될 반도체 기판 부분이 노출되도록, 공지된 식각 공정으로 제1질화막(13) 및 제1열산화막(12)을 패터닝한다. 2A to 2G are cross-sectional views illustrating a method of manufacturing an SOI substrate according to an exemplary embodiment of the present invention. First, as shown in FIG. 2A, a semiconductor substrate 11 made of bulk silicon is provided, and a first thermal oxide film 12 of 20 to 200 kPa and a first of 700 to 1,500 kPa are provided on the semiconductor substrate 11. The nitride film 13 is formed sequentially. Then, the first nitride film 13 and the first thermal oxide film 12 are patterned by a known etching process so that the portion of the semiconductor substrate on which the trench is to be formed is exposed.
그 다음, 도 2b에 도시된 바와 같이, 노출된 반도체 기판(11) 부분을 식각하여 트렌치(14)를 형성하고, 이어서, 상기 트렌치(14)를 형성하기 위한 식각 공정시에 발생된 트렌치(15) 벽면의 손상을 보상하고, 아울러, 트렌치(15)의 코너 부분의 라운딩(rounding)을 위하여, 열산화 공정으로 상기 트렌치 벽면에 50∼200Å 두께의 제2열산화막(15)을 형성한다. 여기서, 트렌치(14)는 최종적으로 얻고자하는 반도체층의 두께 만큼의 깊이, 예컨데, 1,000∼3,000Å의 깊이를 갖도록 형성한다. 또한, 제2열산화막(15)을 형성한 후에는, 트렌치(14) 벽면의 손상을 보다 완벽하게 보상하기 위하여, 상기 제2열산화막(15)을 제거한 상태에서, 재차 열산화막 공정을 수행하여 동일 두께의 열산화막을 형성하는 것도 가능하다. Next, as shown in FIG. 2B, the exposed portion of the semiconductor substrate 11 is etched to form the trench 14, and then the trench 15 generated during the etching process for forming the trench 14 is formed. A second thermal oxide film 15 having a thickness of 50 to 200 Å is formed on the trench wall surface by a thermal oxidation process in order to compensate for damage to the wall surface and to round the corners of the trench 15. In this case, the trench 14 is formed to have a depth equal to the thickness of the semiconductor layer to be finally obtained, for example, a depth of 1,000 to 3,000 Pa. In addition, after the second thermal oxide film 15 is formed, the thermal oxide film process is performed again while the second thermal oxide film 15 is removed in order to more completely compensate the damage of the trench 14 wall. It is also possible to form a thermal oxide film of the same thickness.
다음으로, 도 2c에 도시된 바와 같이, 전체 상부에 500Å 이하의 두께, 바람직하게는, 200∼500Å 두께를 갖는 제2질화막(16)을 형성하고, 트렌치(15)가 매립될 정도의 충분한 두께로 상기 제2질화막(16) 상에 O3 TEOS USG 산화막 또는 고밀도 플라즈마 화학기상증착(HDP CVD) 산화막 중에서 선택되는 하나의 산화막(17)을 형성한다. 여기서, 산화막(17)으로서 O3 TEOS USG 산화막을 형성할 경우에는 그 치밀화를 위해 열처리를 수행하며, HDP CVD 산화막을 형성할 경우에는 그 치밀화를 위해 950∼1,150℃ 및 N2 분위기하에서 30∼60분 동안 열처리를 수행한다.Next, as shown in FIG. 2C, a thickness sufficient to form a second nitride film 16 having a thickness of 500 kPa or less, preferably 200-500 kPa, in the entire upper portion, and the trench 15 is buried. One oxide film 17 selected from an O 3 TEOS USG oxide film or a high density plasma chemical vapor deposition (HDP CVD) oxide film is formed on the second nitride film 16. Here, when the O 3 TEOS USG oxide film is formed as the oxide film 17, heat treatment is performed for densification thereof, and when the HDP CVD oxide film is formed, it is 30 to 60 ° C at 950 to 1,150 ° C. and N 2 atmosphere for the densification. Heat treatment is performed for minutes.
그 다음, 도 2d에 도시된 바와 같이, 제2질화막(16)을 연마정지층으로 하는 CMP 공정으로 산화막(17)을 연마하여 표면 평탄화를 달성하고, 이어서, 인산을 이용한 습식 식각 공정으로 노출된 제2질화막(16) 및 그 하부의 제1질화막과 제1산화막을 제거한다. Next, as shown in FIG. 2D, the oxide film 17 is polished by a CMP process using the second nitride film 16 as a polishing stop layer, thereby achieving surface planarization, and then exposed by a wet etching process using phosphoric acid. The second nitride film 16 and the first nitride film and the first oxide film under the second nitride film 16 are removed.
다음으로, 도 2e에 도시된 바와 같이, 전체 상부에 HDP CVD 산화막, 또는, BPSG막 중에서 선택되는 하나의 막으로된 매몰산화막(18)을 2,000∼10,000Å 두께로 형성하고, 상기 매몰산화막(18) 상에 지지 수단인 베이스 기판(19)을 본딩시킨다. 또한, 베이스 기판(19)을 본딩시킨 후에는, 본딩 강도를 증진시키기 위하여, 800∼950℃의 온도 및 O2 또는 N2 분위기하에서 10∼60분 동안 열처리를 수행한다.Next, as shown in FIG. 2E, an investment buried oxide film 18 made of an HDP CVD oxide film or one film selected from a BPSG film is formed at a thickness of 2,000 to 10,000 Å on the whole, and the investment oxide film 18 is formed. Is bonded to the base substrate 19, which is a support means. In addition, after bonding the base substrate 19, heat treatment is performed for 10 to 60 minutes at a temperature of 800 to 950 ° C and an O 2 or N 2 atmosphere to enhance the bonding strength.
그 다음, 도 2f에 도시된 바와 같이, 트렌치의 저면에 잔류되어 있는 제2질화막(16)을 연마정지층으로 해서, 반도체 기판(11)의 후면을 CMP 공정으로 연마하여 소자가 형성될 반도체층(11a)를 얻는다. 이때, CMP 공정은 CeO2 또는 SiO3를 기본으로 하는 연마액, 즉, 슬러리(Slurry)를 이용하여 수행한다.Next, as shown in FIG. 2F, the semiconductor layer on which the device is formed by polishing the back surface of the semiconductor substrate 11 by the CMP process using the second nitride film 16 remaining on the bottom of the trench as a polishing stop layer. (11a) is obtained. In this case, the CMP process is performed using a polishing liquid based on CeO 2 or SiO 3 , that is, a slurry.
여기서, 반도체층(11a)을 얻기 위한 본 발명에 따른 CMP 공정은 실리콘막과 선택비가 우수한 질화막을 연마정지층으로해서 수행되기 때문에, 종래와 비교해서, 디싱의 발생없이 균일한 두께의 반도체층(11a)을 얻을 수 있다. Here, since the CMP process according to the present invention for obtaining the semiconductor layer 11a is performed using a silicon film and a nitride film having excellent selectivity as the polishing stop layer, a semiconductor layer having a uniform thickness without the occurrence of dishing (compared with the prior art) 11a) can be obtained.
한편, 도 2f는 도 2e를 뒤집어 배치시킨 도면이며, 이후에 설명될 도 2g도 마찬가지이다. 2F is a view in which FIG. 2E is disposed upside down, and FIG. 2G to be described later is also the same.
다음으로, 도 2g에 도시된 바와 같이, 습식 식각으로 제2질화막을 제거하여, 트렌치 내에 산화막이 매립되어 이루어진 트렌치형 소자 분리막(20)을 갖는 SOI 기판(30)을 얻는다. Next, as shown in FIG. 2G, the second nitride film is removed by wet etching to obtain an SOI substrate 30 having a trench type isolation layer 20 in which an oxide film is embedded in the trench.
이상에서와 같이, 본 발명은 실리콘막과 선택비가 우수한 질화막을 연마정지층으로해서 CMP 공정을 수행하기 때문에, 산화막을 연마정지층으로 이용하는 종래 기술과 비교해서, 반도체층 표면에서 디싱 현상이 발생되는 것을 방지할 수 있고, 이에 따라, 반도체층의 두께 균일성을 향상시킬 수 있다. As described above, in the present invention, since the CMP process is performed using a silicon film and a nitride film having an excellent selectivity as the polishing stop layer, dishing phenomenon occurs on the surface of the semiconductor layer as compared with the conventional technique using the oxide film as the polishing stop layer. Can be prevented, and accordingly, thickness uniformity of a semiconductor layer can be improved.
따라서, 후속 공정의 안정화를 도모할 수 있음은 물론, 이러한 SOI 기판 상에 형성되는 반도체 소자의 특성 향상을 기대할 수 있다. Therefore, not only the stabilization of subsequent processes can be achieved, but also the improvement of characteristics of the semiconductor device formed on such an SOI substrate can be expected.
한편, 여기에서는 본 발명의 특정 실시예에 대해서 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한, 모든 수정과 변형을 포함하는 것으로 이해할 수 있다. Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
도 1a 및 도 1b는 종래 기술에 따른 에스오아이 기판의 제조방법을 설명하기 위한 공정 단면도. 1A and 1B are cross-sectional views illustrating a method of manufacturing a S-OI substrate according to the prior art.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 에스오아이 기판의 제조방법을 설명하기 위한 공정 단면도. 2A to 2G are cross-sectional views illustrating a method of manufacturing an SOH substrate according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings
11 : 반도체 기판 12 : 제1열산화막11 semiconductor substrate 12 first thermal oxide film
13 : 제1질화막 14 : 트렌치13: first nitride film 14: trench
15 : 제2열산화막 16 : 제2질화막15: second thermal oxide film 16: second nitride film
17 : 산화막 18 : 매몰산화막17 oxide film 18 buried oxide film
19 : 베이스 기판 20 : 트렌치형 소자 분리막19: base substrate 20: trench type isolation film
30 : SOI 기판30: SOI substrate
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555357A (en) * | 1991-08-27 | 1993-03-05 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH09205072A (en) * | 1996-01-26 | 1997-08-05 | Sony Corp | Formation of soi substrate |
| JPH1131640A (en) * | 1997-07-11 | 1999-02-02 | Sony Corp | Method for manufacturing stuck soi substrate |
| KR20000042385A (en) * | 1998-12-24 | 2000-07-15 | 김영환 | Silicon on insulator device free from floating body effect and fabrication method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555357A (en) * | 1991-08-27 | 1993-03-05 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH09205072A (en) * | 1996-01-26 | 1997-08-05 | Sony Corp | Formation of soi substrate |
| JPH1131640A (en) * | 1997-07-11 | 1999-02-02 | Sony Corp | Method for manufacturing stuck soi substrate |
| KR20000042385A (en) * | 1998-12-24 | 2000-07-15 | 김영환 | Silicon on insulator device free from floating body effect and fabrication method thereof |
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