JP2762462B2 - Semiconductor substrate manufacturing method - Google Patents
Semiconductor substrate manufacturing methodInfo
- Publication number
- JP2762462B2 JP2762462B2 JP63133202A JP13320288A JP2762462B2 JP 2762462 B2 JP2762462 B2 JP 2762462B2 JP 63133202 A JP63133202 A JP 63133202A JP 13320288 A JP13320288 A JP 13320288A JP 2762462 B2 JP2762462 B2 JP 2762462B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- layer
- substrate
- semiconductor
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体基板の製造方法に関し、更に詳しく
薄膜ウエハをSOI（Silicon On Insulator）技術を用い
て作成する方法に係るものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly, to a method for forming a thin film wafer using SOI (Silicon On Insulator) technology.
［発明の概要］ 本発明は、半導体基板の製造方法において、 表面に凹凸を有する半導体基板の凹凸を埋めかつ所定
の厚みを有するように絶縁層を半導体基板上に堆積する
工程と、前記絶縁層上に表面が平坦な半導体層を形成す
る工程と、前記半導体層に基板を貼り合わせる工程と、
前記半導体基板を裏面から前記絶縁層が露出するまで除
去する工程とを備えたこととしたことにより、 選択ポリシングを行なうことが可能となる為、超薄膜
SOIを作成することが可能となり、また、平坦な素子間
分離を形成することが可能となる。[Summary of the Invention] The present invention relates to a method of manufacturing a semiconductor substrate, comprising: a step of filling an unevenness of a semiconductor substrate having an uneven surface and depositing an insulating layer on the semiconductor substrate so as to have a predetermined thickness; A step of forming a semiconductor layer having a flat surface thereon, and a step of bonding a substrate to the semiconductor layer,
A step of removing the semiconductor substrate from the back surface until the insulating layer is exposed, so that selective polishing can be performed.
An SOI can be formed, and a flat isolation between elements can be formed.
［従来の技術］ 従来、この種の超薄膜SOI基板を作成する方法として
は、張り合わせ法と選択ポリッシュ法を使う方法が行な
われている。即ち、貼り合わされたウエハをポリシング
パットに押圧して化学液を介して回転することによって
薄膜半導体層を形成しようとするものである。[Prior Art] Conventionally, as a method for producing an ultra-thin SOI substrate of this kind, a method using a bonding method and a selective polishing method has been used. That is, the bonded wafer is pressed against a polishing pad and rotated through a chemical liquid to form a thin film semiconductor layer.
［発明が解決しようとする課題］ しかしながら、従来においては、段差を有する基板を
貼り合わせるのに、通常の熱処理により貼り合わせるの
が困難であった。従って、貼り合わせを行なうには、平
坦な基板どうしを用いることが必要であった。[Problems to be Solved by the Invention] However, conventionally, it has been difficult to bond substrates having steps by normal heat treatment. Therefore, in order to perform the bonding, it is necessary to use flat substrates.
本発明は、このような従来の問題点に着目して創案さ
れたのもであって、段差を有する基板を容易に貼り合わ
せることが可能となると共に、平坦な素子間分離部も同
時に形成可能な半導体基板の製造方法を得んとするもの
である。The present invention has been made in view of such a conventional problem, and enables a substrate having a step to be easily bonded and a flat device isolation portion to be formed at the same time. It is intended to obtain a method for manufacturing a substrate.
［課題を解決するための手段］ そこで、本発明は、表面に凹凸を有する半導体基板の
凹凸を埋めかつ所定の厚みを有するように絶縁層を半導
体基板上に堆積する工程と、前記絶縁層上に表面が平坦
な半導体層を形成する工程と、前記半導体層に基板を貼
り合わせる工程と、前記半導体基板を裏面から前記絶縁
層が露出するまで除去する工程とを備えたことを、その
解決手段としている。Means for Solving the Problems In view of the above, the present invention provides a step of filling an unevenness of a semiconductor substrate having an unevenness on a surface and depositing an insulating layer on the semiconductor substrate so as to have a predetermined thickness; A step of forming a semiconductor layer having a flat front surface, a step of bonding a substrate to the semiconductor layer, and a step of removing the semiconductor substrate from the back surface until the insulating layer is exposed. And
［作用］ 半導体基板の凹凸部を有する表面側絶縁層を形成し、
その上に半導体層を設けた後、前記半導体基板を裏面か
ら除去（研削）して該絶縁層を露出させることにより、
絶縁層が例えば素子分離部となる薄膜SOI基板の形成が
可能となる。[Operation] A surface-side insulating layer having an uneven portion of a semiconductor substrate is formed,
After the semiconductor layer is provided thereon, the semiconductor substrate is removed (ground) from the back surface to expose the insulating layer.
For example, it is possible to form a thin film SOI substrate in which an insulating layer serves as an element isolation portion.
［実施例］ 以下、本発明に係る半導体基板の製造方法の詳細を図
面に示す実施例に基づいて説明する。EXAMPLES Hereinafter, details of a method of manufacturing a semiconductor substrate according to the present invention will be described based on examples shown in the drawings.
先ず、第１図に示すように、半導体基板としてのシリ
コン基板１の表面に凹凸（段差）を形成する溝1aを形成
する。なお、この溝1aは後記する素子分離部を形成する
ためのものであって、所定の幅，深さ（0.1μｍ程度）
寸法が予め設定されている。また、前記溝1aは、エッチ
ングにより形成される。First, as shown in FIG. 1, a groove 1a for forming irregularities (steps) is formed on the surface of a silicon substrate 1 as a semiconductor substrate. The groove 1a is for forming an element isolation portion described later, and has a predetermined width and depth (about 0.1 μm).
The dimensions are set in advance. Further, the groove 1a is formed by etching.
次に、シリコン基板１の表面に、例えばCVD法により
絶縁層としてのSiO2層２を堆積させる（第２図）。Next, an SiO 2 layer 2 as an insulating layer is deposited on the surface of the silicon substrate 1 by, for example, a CVD method (FIG. 2).
そして、第３図に示すように、前記SiO2層２の表面に
半導体層としての多結晶シリコン層３を形成し、さら
に、第４図に示すように、この多結晶シリコン層３の表
面にミラーポリッシュを行ない平坦にする。Then, as shown in FIG. 3, a polycrystalline silicon layer 3 as a semiconductor layer is formed on the surface of the SiO 2 layer 2, and further, as shown in FIG. Mirror polish and flatten.
次に、第５図に示すように、多結晶シリコン層３の表
面に、気体としての別のシリコンウエハ４を貼り合わせ
た後、シリコン基板１の裏面側より選択ポリッシュを前
記SiO2層２が露出するまで行なう。このようにして、第
６図に示すように、上記シリコン基板１の溝1a内のSiO2
層２が素子分離部2aとなり、素子分離部2aに画成された
シリコン基板１が素子形成領域1bとなる。Next, as shown in FIG. 5, after bonding another silicon wafer 4 as a gas to the surface of the polycrystalline silicon layer 3, the SiO 2 layer 2 is selectively polished from the back side of the silicon substrate 1. Repeat until exposed. In this manner, as shown in FIG. 6, the SiO 2 in the groove 1a of the silicon substrate 1 is formed.
The layer 2 becomes the element isolation part 2a, and the silicon substrate 1 defined in the element isolation part 2a becomes the element formation region 1b.
以上、実施例について説明したが、上記した選択ポリ
ッシュとは、例えばエチレンジアミン・ピロカテコール
を用いたSiのエッチングはSiとアミンと水が反応し、Si
表面に▲Si（OH）2- 6▼が形成され、それがピロカテコ
ールとキレートを生成し、液中に溶解していく反応によ
る２段階で行なわれるが、このピロカテコールによる▲
Si（OH）2- 6▼の除去作用を機械的除去作用に置き換え
た方法である。Although the embodiment has been described above, the above-mentioned selective polish refers to, for example, etching of Si using ethylenediamine / pyrocatechol, Si, amine and water react,
▲ Si (OH) 2- 6 ▼ is formed on the surface, but it generates the pyrocatechol and chelate, is performed in two stages by reaction going dissolved in the liquid, according to the pyrocatechol ▲
Si a (OH) 2- 6 ▼ removal action of a method of replacing the mechanical removal action.
また、上記した実施例にあっては、基体としてシリコ
ンウエハ４を貼り付けたが、これに限るものではない。In the above-described embodiment, the silicon wafer 4 is attached as the base, but the present invention is not limited to this.
［発明の効果］ 以上の説明から明らかなように、本発明に係る半導体
基板の製造方法にあっては、選択ポリッシュが用いられ
るため、超薄膜SOIを可能にする効果がある。[Effects of the Invention] As is clear from the above description, in the method of manufacturing a semiconductor substrate according to the present invention, since selective polishing is used, there is an effect of enabling an ultrathin SOI.
また、同時に平坦な素子分離部も形成出来るため、素
子製造工程を簡略化する効果がある。In addition, since a flat element isolation portion can be formed at the same time, there is an effect of simplifying the element manufacturing process.
第１図は〜第６図は本発明に係る半導体基板の製造方法
の実施例を示す断面図である。 １……シリコン基板、1a……溝、1b……素子形成領域、
２……SiO2層、2a……素子分離部、３……多結晶シリコ
ン層、４……シリコンウエハ。1 to 6 are sectional views showing an embodiment of a method for manufacturing a semiconductor substrate according to the present invention. 1 .... silicon substrate, 1a ... groove, 1b ... element formation region,
2 ... SiO 2 layer, 2a ... element isolation part, 3 ... polycrystalline silicon layer, 4 ... silicon wafer.
Claims (1)
めかつ所定の厚みを有するように絶縁層を半導体基板上
に堆積する工程と、前記絶縁層上に表面が平坦な半導体
層を形成する工程と、前記半導体層に基板を貼り合わせ
る工程と、前記半導体基板を裏面から前記絶縁層が露出
するまで除去する工程とを備えたことを特徴とする半導
体基板の製造方法。A step of depositing an insulating layer on the semiconductor substrate so as to fill the unevenness of the semiconductor substrate having an uneven surface and to have a predetermined thickness; and forming a semiconductor layer having a flat surface on the insulating layer. A method of manufacturing a semiconductor substrate, comprising: a step of bonding a substrate to the semiconductor layer; and a step of removing the semiconductor substrate from a back surface until the insulating layer is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63133202A JP2762462B2 (en) | 1988-05-31 | 1988-05-31 | Semiconductor substrate manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63133202A JP2762462B2 (en) | 1988-05-31 | 1988-05-31 | Semiconductor substrate manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01302837A JPH01302837A (en) | 1989-12-06 |
| JP2762462B2 true JP2762462B2 (en) | 1998-06-04 |
Family
ID=15099118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63133202A Expired - Fee Related JP2762462B2 (en) | 1988-05-31 | 1988-05-31 | Semiconductor substrate manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2762462B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH025545A (en) * | 1988-06-24 | 1990-01-10 | Nec Corp | Manufacture of semiconductor device |
| JP3192000B2 (en) * | 1992-08-25 | 2001-07-23 | キヤノン株式会社 | Semiconductor substrate and manufacturing method thereof |
| JP2806277B2 (en) * | 1994-10-13 | 1998-09-30 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JP2755185B2 (en) * | 1994-11-07 | 1998-05-20 | 日本電気株式会社 | SOI substrate |
| US6191007B1 (en) | 1997-04-28 | 2001-02-20 | Denso Corporation | Method for manufacturing a semiconductor substrate |
| US6251754B1 (en) | 1997-05-09 | 2001-06-26 | Denso Corporation | Semiconductor substrate manufacturing method |
| JP3431454B2 (en) | 1997-06-18 | 2003-07-28 | 株式会社東芝 | Method for manufacturing semiconductor device |
| US6534380B1 (en) | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57180148A (en) * | 1981-04-30 | 1982-11-06 | Fujitsu Ltd | Manufacture of semiconductor device having dielectric isolation structure |
| JPS60262438A (en) * | 1984-06-08 | 1985-12-25 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS61133641A (en) * | 1984-12-03 | 1986-06-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0783050B2 (en) * | 1985-06-21 | 1995-09-06 | 株式会社東芝 | Method for manufacturing semiconductor device |
-
1988
- 1988-05-31 JP JP63133202A patent/JP2762462B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01302837A (en) | 1989-12-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |