JPH025545A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH025545A JPH025545A JP15729988A JP15729988A JPH025545A JP H025545 A JPH025545 A JP H025545A JP 15729988 A JP15729988 A JP 15729988A JP 15729988 A JP15729988 A JP 15729988A JP H025545 A JPH025545 A JP H025545A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- substrate
- groove
- silicon substrate
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 61
- 239000010703 silicon Substances 0.000 claims abstract description 61
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 9
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 9
- 238000005498 polishing Methods 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 5
- 150000003376 silicon Chemical class 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 20
- 150000001412 amines Chemical class 0.000 abstract description 3
- 238000005299 abrasion Methods 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- YOSRLTNUOCHBEA-ATLBLLJHSA-N (2s,3s,4s,5r)-6-[[(3s,4ar,6ar,6bs,8as,12as,14ar,14br)-4,4,6a,6b,11,11,14b-heptamethyl-8a-[(3s,4r,5r,6s)-3,4,5-trihydroxy-6-(hydroxymethyl)oxan-2-yl]oxycarbonyl-1,2,3,4a,5,6,7,8,9,10,12,12a,14,14a-tetradecahydropicen-3-yl]oxy]-3,4,5-trihydroxyoxane-2-carbo Chemical compound O([C@H]1CC[C@]2(C)[C@H]3CC=C4[C@@]([C@@]3(CC[C@H]2C1(C)C)C)(C)CC[C@]1(CCC(C[C@H]14)(C)C)C(=O)OC1[C@H]([C@H](O)[C@@H](O)[C@H](CO)O1)O)C1O[C@H](C(O)=O)[C@@H](O)[C@H](O)[C@H]1O YOSRLTNUOCHBEA-ATLBLLJHSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 239000009664 saparal Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Landscapes
- Element Separation (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関l、2、特に。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
誘電体分離構造をもつ半導体装置の製造方法に関する。The present invention relates to a method of manufacturing a semiconductor device having a dielectric isolation structure.
従来、誘電体分離構造をもつ半導体装置の製造方法とし
ては、サファイア基板]二に設けられた島状シリコンを
用いて半導体素子を形成する方法(Silicon o
n 5apphire、SOSと略す)、シリコン基板
に酸素をイオン注入した後にシリコン層をエビクキシャ
ル成長し、このシリコン層を島状としてそこに半導体素
子を形成する方法(Saparal、ion byIm
planted Oxygen、 SIMOXと略す)
などが知られていた。しかしながら、SO3ではシリコ
ン層の結晶性が通常のバルク状シリコンに比べて悪く、
電子やホールの移動度が低いという欠点があり、S T
、M OXでは多量の酸素をイオン注入する必要があり
、基板の形状が困磐であるという欠点があった、最近、
二枚のシリコン基板を用い、少なくとも一方の基板の表
面に酸化膜を形成しlt@、酸化膜を間に介して両板を
張り合わせることにより誘電体分離構造をもつ半導体装
置が形成できることが報告されているやこの技術はりt
結晶シリコンを半導体素子の形成に用いることができる
ため、SO5にお目る移動度の低下はなく、また、張り
合わせの工程も熱処理や電圧をかけるだけでよ< SI
MOXにおける多量のイオン注入を必要としないという
利点をもっている。Conventionally, as a method for manufacturing a semiconductor device having a dielectric isolation structure, there has been a method of forming a semiconductor element using island-shaped silicon provided on a sapphire substrate.
n5apphire, abbreviated as SOS), a method in which oxygen ions are implanted into a silicon substrate, and then a silicon layer is evixtally grown, and this silicon layer is formed into an island shape to form a semiconductor element there (Saparal, ion by Im).
(abbreviated as SIMOX)
etc. were known. However, in SO3, the crystallinity of the silicon layer is poorer than that of normal bulk silicon;
It has the disadvantage of low mobility of electrons and holes, and S T
, MOX requires a large amount of oxygen to be ion-implanted, and the disadvantages are that the shape of the substrate is difficult.
It has been reported that a semiconductor device with a dielectric isolation structure can be formed by using two silicon substrates, forming an oxide film on the surface of at least one of the substrates, and bonding the two plates together with an oxide film in between. This technology is being used
Since crystalline silicon can be used to form semiconductor devices, there is no decrease in mobility as seen in SO5, and the bonding process requires only heat treatment and voltage application.
It has the advantage of not requiring a large amount of ion implantation in MOX.
しかし、この張り合わせ技術においては、半導体素子を
形成するためのシリコン層を薄く形成することが重要と
なるが、従来報告された方法ではコントロール良く容易
に薄いシリコン層を形成することが困難であった。例え
ば、研磨により薄11侍化する方法は、コストはかから
ないが、精度良く均一なシリコン層を得ることは困難で
ある。まブ辷、エピタキシャルウェーハを用い、選択エ
ツチングによりシリコンを薄くして半導体素子形成層を
作成する方法も知られているが、エピタキシャルウェー
ハのコス1−が高いという欠点があった7本発明の目的
は、ニれ1:′]の欠点をなくシ、大幅な工程の増加を
伴わないで、均一な厚さのシリコン層を精度良く形成で
きる半導体装置の製造方法を提供することj7こある。However, in this bonding technology, it is important to form a thin silicon layer to form a semiconductor element, but it has been difficult to easily form a thin silicon layer with good control using previously reported methods. . For example, a method of reducing the thickness by polishing is inexpensive, but it is difficult to obtain a uniform silicon layer with high precision. It is also known to create a semiconductor element forming layer by thinning silicon by selective etching using an epitaxial wafer, but this method has the drawback that the cost of the epitaxial wafer is high.7Objects of the present invention It is an object of the present invention to provide a method for manufacturing a semiconductor device, which eliminates the drawbacks of deviance 1:' and can form a silicon layer of uniform thickness with high precision without significantly increasing the number of steps.
前記目的を達成するため、本発明による半導体装lの製
造方法においては、第一のシリコン基板の一主面に講を
設Uた後このシリコンの表面に二酸化シリコンを形成す
る工程と、このシリコン基板の一主面4X′ポリシリコ
ンを形成し上記の溝を埋めた後このポリシリコンを研磨
して表面を平坦化する工程と、前記第一のシリコン基板
の一主面と第二のシリコン基板を密着し熱処理を施すこ
とにより画板を張り合わせる工程と、第一のシリコン基
板を他の主面から選択研磨を施して前記溝底に形成され
た二酸化シリコンが露出するまで研磨する工程と、前記
第一のシリコン基板の研磨面に半導体素子を形成する工
程とを含むものである。In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a silicon dioxide on the surface of the silicon after forming a groove on one main surface of the first silicon substrate, and a step of forming silicon dioxide on the surface of the silicon. a step of forming 4X' polysilicon on one main surface of the substrate, filling the above-mentioned grooves, and then polishing the polysilicon to flatten the surface; a step of laminating the drawing board by adhering the two silicon substrates closely and applying heat treatment; a step of selectively polishing the first silicon substrate from the other main surface until the silicon dioxide formed at the bottom of the groove is exposed; The method includes a step of forming a semiconductor element on the polished surface of the first silicon substrate.
本発明の半導体装置の製造方法に19いで、ウェーハの
研磨にアミン系の研磨液を使用すれば、シリコンの研磨
速度に比ベシリコン酸化膜の研m速度が100分の1以
下と小さく、酸化膜が露出した点で研磨が停止する。そ
のためシリコン中に酸化シリコンの領域を予め形成して
おくことによりシリコンを選択研磨した際、この酸化シ
リコンが露出した時点で研磨が停+h シ、酸化シリコ
ンによって囲まれたシリコンは一定の厚さに形成される
。If an amine-based polishing liquid is used for polishing the wafer in the method for manufacturing a semiconductor device of the present invention in step 19, the polishing speed of the silicon oxide film is as low as 1/100 or less compared to the polishing speed of silicon, and the oxide film Polishing stops at the point where is exposed. Therefore, when silicon is selectively polished by forming a silicon oxide region in advance in silicon, the polishing stops when this silicon oxide is exposed, and the silicon surrounded by silicon oxide has a constant thickness. It is formed.
したがって、研磨だけで精度良くシリコンを一定の厚さ
に研磨できる。Therefore, silicon can be polished to a constant thickness with high precision just by polishing.
以下本発明による半導体装置の製造方法の一実施例を第
1−図から第4図を利用して説明する。こ4]、らの図
は、各製造工程におけるウェーハの一部分の断面を示し
ている。An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. 1-4. Figures 4 and 4 show cross sections of a portion of the wafer in each manufacturing process.
まず、第1図に示すように第1.のシリコン基板1の主
面に二酸化シリコンfcよる酸化膜2で表面が覆われた
溝を形成する。具体的には、第1−のシリコン基板1の
主面に異方性ドライエツチングにより溝を設けた後、熱
酸化により溝の内部に酸化;摸2を形成するもので、そ
の後ポリシリコン3で溝を埋め込み、さらにこのポリシ
リコンを研磨して表面を平にする。次L:、第2図に示
すように、第1のシリコン基板1と第2のシリコン基板
4とを張り合わせ、熱処理により化学的に結合させる。First, as shown in FIG. A trench whose surface is covered with an oxide film 2 made of silicon dioxide fc is formed on the main surface of a silicon substrate 1. Specifically, after a groove is formed on the main surface of the first silicon substrate 1 by anisotropic dry etching, an oxidized pattern 2 is formed inside the groove by thermal oxidation, and then polysilicon 3 is etched. The grooves are filled and the polysilicon is polished to make the surface flat. Next L: As shown in FIG. 2, the first silicon substrate 1 and the second silicon substrate 4 are bonded together and chemically bonded by heat treatment.
この工程は、例えば上記の2枚のシリコン基板を親水性
処理した後、密着さ(士高い温度(例えば、1150℃
)で熱処理することによって行う。この方法はシラノ−
・ル接合と呼ばれ、例えば、応用物理、第56巻第3号
、373−376頁(1987)に報告されている。In this step, for example, after the two silicon substrates described above are subjected to hydrophilic treatment, the adhesion is maintained at a high temperature (for example, 1150°C
) by heat treatment. This method
- It is called a le junction and is reported, for example, in Oyoi Physics, Vol. 56, No. 3, pp. 373-376 (1987).
また、間に酸化膜を介して接合することも可能であり、
この方法は例えばアイイーイーイー、インターナショナ
ル エレン1−ロン デバイス ミーティングCIEE
E、 Hnternational El、eetro
n I)evic。It is also possible to bond with an oxide film in between,
This method can be used, for example, at International Ellen 1-Ron Device Meeting CIEE.
E, Hinternational El, eetro
n I)evic.
Meeti−nH)のテクニカル ダイジエスh (T
eehriieatDi(Hest)684−687頁
(1985年)に報告されている。また、同様の技術は
特公昭3947869号公報にも報告されている。第3
図において、次に、第1のシリコン基板1−を裏面から
選択研磨により、前記)pの底に設げられた醇化11λ
2が露出するまで研磨する。Technical Digest h (T
eehriieatDi (Hest) pp. 684-687 (1985). A similar technique is also reported in Japanese Patent Publication No. 3947869. Third
In the figure, next, by selectively polishing the first silicon substrate 1- from the back surface, the enamel 11λ provided at the bottom of the
Polish until 2 is exposed.
研磨液としてアミンを用いることにより、酸化膜2が露
出した時点で研磨が自動的に停止するため、第1のシリ
コン基板1−の研磨後の厚さは上記の溝の深ととほぼ等
り、 <なり、均一な厚さのシリコン層を精度良く形成
ずろことができる。その後、第3図のように誘電体分離
され、たシリコン基板1−の一部であるシリコン層11
に通常の集積回路プロセスにより第4図のように1シリ
コン7、n″′′シリコン8シリコン9.9シリコンl
Oを形成し、グー1−酸化膜5.ゲート電極6を付して
半導体素子を構成することにより、誘電体分離された半
導体装置が?()られろ。第71図はコンプリメンタリ
−HlFET(Ins ulated Gate
Fiel、d Effect Transj、5
tor)が形成された半導体装置を示し、ポリシリコン
からなるグー1−電極6をもつnチャネルIGFET
、1. pチャネルIGFETが互いに誘電体分離さオ
11て形成さ扛でいる。By using amine as the polishing liquid, polishing automatically stops when the oxide film 2 is exposed, so the thickness of the first silicon substrate 1- after polishing is approximately equal to the depth of the groove described above. , <, and a silicon layer of uniform thickness can be formed with high precision. Thereafter, as shown in FIG. 3, the silicon layer 11, which is part of the silicon substrate 1-, is dielectrically separated
As shown in Figure 4, 1 silicon 7, n'''' silicon 8 silicon 9.9 silicon 1
Form O, goo 1-oxide film 5. By attaching a gate electrode 6 and configuring a semiconductor element, a dielectrically isolated semiconductor device can be obtained. () Let it go. Figure 71 shows a complementary HlFET (Insulated Gate).
Field, d Effect Transj, 5
This is an n-channel IGFET with a 1-electrode 6 made of polysilicon.
, 1. P-channel IGFETs are formed dielectrically isolated from each other.
以−ヒ説明したように本発明によればポリシリコン使用
のため表面平坦化処理が容易であり、誘電体で分離され
た1こ導体基板にシリコンウェーハの張り合わせ技術を
使用して容易に製造でき、厚さが均一・で精度良くコン
l−D−ルされた誘電体分離シリコン、―を形成できる
という効果がある。As explained below, according to the present invention, surface flattening is easy due to the use of polysilicon, and it can be easily manufactured using the technique of bonding a silicon wafer to a single conductor substrate separated by a dielectric. This method has the advantage of being able to form dielectrically isolated silicon of uniform thickness and precisely contoured.
第1図から第4図は本発明の一実施例を工程順に示1ノ
だ半導体ウェーハの一部分の断面図である。
】−・・・第1のシリコン基板 2・・・酸化膜:う・
・・ポリシリコン 4・・・第2のシリコン基板5
・・・ゲート・酸化膜 6・・・ゲ・−1−電極
7・・・p0シリコン 8・・・n+シリコン
9・・・nシリコン 10・・・■)シリコン
】l・・・シリコン層1 to 4 are cross-sectional views of a portion of a first semiconductor wafer showing an embodiment of the present invention in the order of steps. ]--First silicon substrate 2...Oxide film: U-
...Polysilicon 4...Second silicon substrate 5
...Gate/oxide film 6...Ge-1-electrode 7...p0 silicon 8...n+silicon 9...n silicon 10...■) Silicon】l...Silicon layer
Claims (1)
シリコンの表面に二酸化シリコンを形成する工程と、こ
のシリコン基板の一主面にポリシリコンを形成し上記の
溝を埋めた後このポリシリコンを研磨して表面を平坦化
する工程と、前記第一のシリコン基板の一主面と第二の
シリコン基板を密着し熱処理を施すことにより両板を張
り合わせる工程と、第一のシリコン基板を他の主面から
選択研磨を施して前記溝底に形成された二酸化シリコン
が露出するまで研磨する工程と、前記第一のシリコン基
板の研磨面に半導体素子を形成する工程とを含むことを
特徴とする半導体装置の製造方法。(1) After forming a groove on one main surface of the first silicon substrate, forming silicon dioxide on the surface of this silicon, and forming polysilicon on one main surface of this silicon substrate to fill the above groove. Thereafter, a step of polishing the polysilicon to flatten the surface, a step of adhering one main surface of the first silicon substrate and a second silicon substrate to each other by applying heat treatment, and a first step. a step of selectively polishing the silicon substrate from the other main surface until silicon dioxide formed at the bottom of the groove is exposed; and a step of forming a semiconductor element on the polished surface of the first silicon substrate. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15729988A JPH025545A (en) | 1988-06-24 | 1988-06-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15729988A JPH025545A (en) | 1988-06-24 | 1988-06-24 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH025545A true JPH025545A (en) | 1990-01-10 |
Family
ID=15646629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15729988A Pending JPH025545A (en) | 1988-06-24 | 1988-06-24 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH025545A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05259268A (en) * | 1992-03-11 | 1993-10-08 | Nec Corp | Semiconductor device and its manufacture |
US5449638A (en) * | 1994-06-06 | 1995-09-12 | United Microelectronics Corporation | Process on thickness control for silicon-on-insulator technology |
US5496764A (en) * | 1994-07-05 | 1996-03-05 | Motorola, Inc. | Process for forming a semiconductor region adjacent to an insulating layer |
US5691231A (en) * | 1994-06-16 | 1997-11-25 | Nec Corporation | Method of manufacturing silicon on insulating substrate |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57180148A (en) * | 1981-04-30 | 1982-11-06 | Fujitsu Ltd | Manufacture of semiconductor device having dielectric isolation structure |
JPS60262438A (en) * | 1984-06-08 | 1985-12-25 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS61133641A (en) * | 1984-12-03 | 1986-06-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS61292934A (en) * | 1985-06-21 | 1986-12-23 | Toshiba Corp | Manufacture of semiconductor element |
JPH01302837A (en) * | 1988-05-31 | 1989-12-06 | Sony Corp | Manufacture of semiconductor substrate |
JPH01305534A (en) * | 1988-06-02 | 1989-12-08 | Fujitsu Ltd | Manufacture of semiconductor substrate |
-
1988
- 1988-06-24 JP JP15729988A patent/JPH025545A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57180148A (en) * | 1981-04-30 | 1982-11-06 | Fujitsu Ltd | Manufacture of semiconductor device having dielectric isolation structure |
JPS60262438A (en) * | 1984-06-08 | 1985-12-25 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS61133641A (en) * | 1984-12-03 | 1986-06-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS61292934A (en) * | 1985-06-21 | 1986-12-23 | Toshiba Corp | Manufacture of semiconductor element |
JPH01302837A (en) * | 1988-05-31 | 1989-12-06 | Sony Corp | Manufacture of semiconductor substrate |
JPH01305534A (en) * | 1988-06-02 | 1989-12-08 | Fujitsu Ltd | Manufacture of semiconductor substrate |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05259268A (en) * | 1992-03-11 | 1993-10-08 | Nec Corp | Semiconductor device and its manufacture |
US5449638A (en) * | 1994-06-06 | 1995-09-12 | United Microelectronics Corporation | Process on thickness control for silicon-on-insulator technology |
US5691231A (en) * | 1994-06-16 | 1997-11-25 | Nec Corporation | Method of manufacturing silicon on insulating substrate |
US5496764A (en) * | 1994-07-05 | 1996-03-05 | Motorola, Inc. | Process for forming a semiconductor region adjacent to an insulating layer |
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