JP3037934B2 - Improved Smart Cut process for the manufacture of semiconductor material thin film - Google Patents

Improved Smart Cut process for the manufacture of semiconductor material thin film

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JP3037934B2
JP3037934B2 JP23775198A JP23775198A JP3037934B2 JP 3037934 B2 JP3037934 B2 JP 3037934B2 JP 23775198 A JP23775198 A JP 23775198A JP 23775198 A JP23775198 A JP 23775198A JP 3037934 B2 JP3037934 B2 JP 3037934B2
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layer
wafer
step
bonding
method
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JPH11121377A (en
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クリス・ブイ・スリクリシュナン
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インターナショナル・ビジネス・マシーンズ・コーポレイション
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/05Etch and refill
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/977Thinning or removal of substrate

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、概して半導体薄膜の製造プロセスに関するものであり、具体的には単結晶フィルムの製造に適用可能なプロセスに関する。 BACKGROUND OF THE INVENTION The present invention generally relates to the manufacturing process of the semiconductor thin film, particularly to applicable process for the production of a single crystal film.

【0002】 [0002]

【従来の技術】単結晶半導体フィルムを製造するためには種々の方法及びプロセスがあるが、これらは複雑で高コストであることが多い。 Although in order to produce the Related Art Single-crystal semiconductor film there are a variety of methods and processes, which are often complicated and costly. 多結晶または非晶質フィルムを製造することは比較的容易であるが、単結晶フィルムを製造することはもっと困難である。 Polycrystalline or is relatively easy to produce an amorphous film, it is more difficult to produce a single crystal film. 単結晶フィルムを製造するのに用いられる方法の内には絶縁層上のシリコン(SOI)型の基体の製造に用いられるものがあるが、その目的はフィルムから電気的に絶縁された基体上に単結晶シリコン・フィルムを製造することにある。 Within the method used to produce the single crystal film is used in the manufacture of a substrate of the silicon (SOI) type on the insulating layer, but its purpose is electrically insulated on the substrate from the film It is to produce a single crystal silicon film.

【0003】従来型のSOIウエハーの断面が図1に示されている。 [0003] cross-section of a conventional SOI wafer is shown in FIG. 基体10の上に絶縁層15が形成される。 Insulating layer 15 is formed on a substrate 10.
絶縁層15の上にデバイス層20が形成される。 Device layer 20 is formed on the insulating layer 15. SOI SOI
ウエハーはマイクロエレクトロニクスの分野において知られており、放射線硬化デバイスを含む特別の用途、例えばスタティック・ランダム・アクセス・メモリ(RA Wafers are known in the field of microelectronics, special applications including radiation curing device, for example, static random access memory (RA
M)、および最近では高性能相補型金属酸化物半導体(CMOS)やダイナミック・ランダム・アクセス・メモリ(DRAM)の用途に用いられる。 M), and recently used in applications of high-performance complementary metal oxide semiconductor (CMOS) or a dynamic random access memory (DRAM). SOIウエハーは、1)酸素インプラント(SIMOX)(シリコンに酸素がインプラントされて2酸化シリコン(SiO 2 SOI wafers, 1) oxygen implant (SIMOX) (silicon oxygen implanted in which by silicon dioxide (SiO 2)
埋設層に変換される)、2)ウエハーボンディング−エッチ・バック(BESOI)(2枚のウエハーが酸化表面層で接合され1つの層が薄いデバイス層を残すために薄くされる)、により通常は製造される。 Is converted to buried layer), 2) Wafer Bonding - etched back (BESOI) (two sheets of wafers is thinned to leave the device layer one layer is bonded a thin oxide surface layer), usually by It is produced. 過去数年の間BESOIに基づくSOI材料技術への関心が高まってきている。 There has been a growing interest in SOI material technology that is based on the past few years BESOI. 従来のBESOIプロセスでは、均一性および許容誤差の問題を最小限にするために複数回エッチされた層が用いられている。 In conventional BESOI processes, uniformity and is several times the etch to minimize the tolerance problems layers are used.

【0004】SOI基体を製造するもう1つの最近のプロセスは、スマート・カット(登録商標)プロセスである。 [0004] Another recent process for manufacturing SOI substrates is a Smart Cut (registered trademark) process. スマート・カット・プロセスは米国特許第5,374,56 Smart Cut process is US Patent No. 5,374,56
4号に述べられている。 It is described in No. 4. これはBESOIプロセスと同じであるが、エッチングにより薄くする代わりに接合の前にインプラントされる水素層を用いており、これにより接合後バルクのシリコンが割れて薄い層を残す。 This is the same as BESOI process uses a hydrogen layer is implanted prior to the junction instead of thinning by etching, thereby leaving a thin layer silicon is cracking after bonding bulk. つまり、スマート・カット・プロセスでは接合されたウエハーからデバイス・ウエハーのバルクを割るために水素インプランテーションおよびアニーリングが用いられる。 In other words, the hydrogen implantation and annealing is used to divide the bulk of the device wafer from a wafer joined in SmartCut process.
切り取られた形のSOIウエハーを平面化し不均一性を最小にするために化学的機械的研磨(CMP)が用いられる。 Chemical mechanical polishing (CMP) is used to plan the truncated form of the SOI wafer to minimize non-uniformity.

【0005】スマート・カット・プロセスは次のステップから成る。 [0005] smart-cut process consists of the following steps. 1)デバイス・ウエハーがデバイス級品質の表面層を持つように処理され、デバイス層の上に酸化物層が設けられ、ある深さの所に水素が豊富な埋設層がインプラントされる。 1) Device wafer is processed to have a surface layer of the device class quality, oxide layer is provided on the device layer, hydrogen at a certain depth-rich buried layer is implanted. 2)酸化物表面を持つ“ハンドル・ウエハー”が与えられる。 2) having an oxide surface "handle wafer" is given. 3)デバイス・ウエハーがひっくり返されて酸化物表面が接合される。 3) oxide surface is bonded device wafer is flipped over. 4)構造体がアニールされ水素生成により接合空所が形成される。 4) the structure is bonded cavity by being annealed hydrogen generation is formed.
5)構造体が割れる。 5) structure is broken. 6)転写されたデバイス層がCM 6) transferred device layer CM
P研磨され清浄にされる。 Is in P polished clean.

【0006】図2はスマート・カット・プロセスを用いてSOI基体を形成するプロセス・ステップの流れ図である。 [0006] FIG. 2 is a flow diagram of process steps of forming a SOI substrate using SmartCut process. 図3ないし図5は図2のステップを示す図である。 3 to 5 are views showing the steps of FIG. デバイス級品質のウエハー200がステップ100 Wafer 200 of device-class quality is step 100
で与えられる。 It is given by. ウエハー表面はステップ105で酸化され、これにより熱的に成長したSiO 2層205(即ち誘電体層)により被せられる、即ち埋設される。 The wafer surface is oxidized in step 105, thereby overlaid by the SiO 2 layer 205 that is thermally grown (i.e. dielectric layer), i.e., is embedded. 誘電体層205はSIO構造の埋設された酸化物となる。 The dielectric layer 205 is a buried oxide SIO structure. 水素イオンがステップ110において50ないし150Ke It is 50 in step 110 the hydrogen ion 150Ke
V、2×10 16ないし1×10 17イオン/cm 2の濃度でインプラントされ、図3に示されるように上面の約0.5ないし1μm下に水素に富んだ層210を形成する。 V, 2 × 10 16 to be implanted at a concentration of 1 × 10 17 ions / cm 2, to form a layer 210 of hydrogen-rich from about 0.5 of an upper surface under 1μm as shown in Figure 3. デバイス層となる薄いシリコン層は層207で示されている。 Thin silicon layer serving as a device layer is indicated by the layer 207.

【0007】デバイス・ウエハー200および支持基体(インプラントされていないハンドル・ウエハー)22 [0007] The device wafer 200 and the supporting substrate (handle wafer not implant) 22
0がRCAウエハー・クリーニング手順などの通常のクリーニング手法を用いてステップ115でクリーニングされる。 0 is cleaned at step 115 using conventional cleaning methods such as RCA wafer cleaning procedure. デバイス・ウエハー200および支持基体22 The device wafer 200 and the supporting substrate 22
0の表面は親水性にされ、図4に示されるようにステップ120で室温において共に接合される。 Surface 0 are hydrophilic, are joined together at room temperature in step 120 as shown in FIG. 支持基体22 The support base 22
0は剛直性を与えるものとして働き、SOI構造中の埋設酸化物の下にバルク・シリコンを与える。 0 acts as providing rigidity to provide a bulk silicon under the buried oxide in the SOI structure.

【0008】親水性(または直接的)接合では、原子の電荷が存在するため材料表面に水酸基グループ(O [0008] The hydrophilic (or direct) the junction, a hydroxyl group on the surface of the material for the charge of atoms are present (O
- )が形成される。 H -) are formed. 更に、表面上に水分子の幾層かが水酸基グループの周りに形成される。 Furthermore, if several layers of water molecules is formed around the hydroxyl group on the surface. それぞれ十分に平らな面を有するこのような2つのイオン性物質が互いに付着すると、これらの物質は水酸基グループおよび水分子の間に形成される水素結合による親水性接合によって互いに強固に接合される。 When such two ionic materials having a sufficiently flat surface respectively are attached to each other, these materials are firmly joined together by the hydrophilic bonding by hydrogen bonds formed between the hydroxyl groups and water molecules. このようにしてイオン性物質の平らな面は接着剤を用いることなく互いに親水性接合で接合されうる。 In this way, the flat surface of the ionic material may be bonded to each other hydrophilic bonding without using an adhesive. その後のアニーリングは接合を更に強化する。 Subsequent annealing further strengthen the bonding.

【0009】接合された2つのウエハー200および2 [0009] The two joined wafers 200 and 2
20に2相の熱処理が加えられる。 20 to the two-phase heat treatment is applied. ステップ125において、接合されたウエハー200及び220は約400 In step 125, wafers 200 and 220 which are joined about 400
ないし600℃までアニールされ、これがもろいシリコン水酸化物の領域の形成およびリンクを促進する。 To be annealed to 600 ° C., which promotes the formation and link regions of brittle silicon hydroxide. 水酸化物領域が水を横切って完全にリンクされるとデバイス・ウエハー200は割れて水素が豊富な面にそって接合体から離れる。 Device wafer 200 when hydroxides region is fully linked across the water away from the assembly along the rich surface hydrogen cracking. 薄いシリコン層207は図5に示すように支持基体220に接合されたままとなる。 Thin silicon layer 207 remains bonded to the support substrate 220 as shown in FIG. 次に薄いシリコン層207(デバイス層)が依然接合されている支持基体220が高温(約1000℃)でアニールされて支持基体220とデバイス層207との間の接合をより強固にする。 Then a thin silicon layer 207 (device layer) is supporting substrate 220, which is still bonded to the stronger bonding between the supporting substrate 220 and the device layer 207 is annealed at a high temperature (about 1000 ° C.). 分離後、デバイスの分離面は数百オングストローム程度の粗さを持つのが普通である。 After separation, the separation surface of the device is normal to have a roughness of about several hundred angstroms. 表面の粗さを減らすためにステップ130でCMPが実施される。 CMP is performed at step 130 to reduce the roughness of the surface.
したがって、インプランテーション・プロセスによりその厚さが良好に決められるのにも関わらず、最終的な厚さの均一度および表面粗さは主としてCMPのパラメータに依存する。 Thus, despite its thickness by implantation process it is determined good, uniformity and surface roughness of the final thickness depends mainly on the parameters of the CMP.

【0010】スマート・カット・プロセスの1つの欠点はカットした状態の表面の粗さが表面平滑化のため研磨(例えばCMP)を必要とすると言うことである。 One disadvantage of the SmartCut process is to say that the surface roughness of a state of cut requires polishing for surface smoothing (e.g., CMP). この研磨はウエハー全体にわたってデバイス層の厚さの均一性に影響を与える。 The polishing affects the uniformity of the thickness of the device layer over the entire wafer. 従って、研磨プロセスは粗さを改善するけれども同時に厚さの変動を生じる。 Therefore, the polishing process produces a variation of the simultaneous thickness but improves roughness.

【0011】もう1つの欠点は、スマート・カット・プロセスを用いて非常に薄いデバイス層(約1000Åの厚さ程度)を得ることが容易でないと言うことである。 [0011] Another drawback is to say that it is not easy to obtain a very thin device layers (about a thickness of about 1000 Å) using a SmartCut process.
これは水素のインプラントおよび拡散が大きな不確実性を持ち、このためより厚い層の形成から出発してそれを薄くし、200Åの許容誤差の中に納めることを必要とするからである。 This has the implant and diffusion is a large uncertainty hydrogen, Thus starting from a thicker layer formed of thin it, because that requires that fit into 200Å tolerance. しかしながら、スマート・カット・プロセスにおいてカットされた状態のウエハーの粗さは約100ないし200Åの範囲にあるのが普通である。 However, the roughness of the wafer in a state of being cut in the Smart Cut process it is common to about 100 to the range of 200 Å. したがって、スマート・カット・プロセスはこのような薄層デバイスにうまく適合するものではない。 Therefore, the smart-cut process is not successfully adapted to such a thin layer device.

【0012】SOI構造を作るその他の方法はエッチング停止層またはエッチング選択性の層を用いる。 [0012] Other methods of making SOI structure using a layer of etch stop layer or etch selectivity. 例えば、BESOI処理の或る形では厚さおよび均一性の制御を改善するためにCMPと共にエッチング停止層が用いられる。 For example, the etch stop layer is used with CMP to improve the control of the thickness and uniformity at a certain form of BESOI process. しかしながら、従来のプロセスではエッチングおよびエッチング停止層がCMPに加えて用いられる。 However, the conventional processes etch and etch stop layer is used in addition to the CMP.

【0013】 [0013]

【発明が解決しようとする課題】単結晶フィルムを作る技術は十分に開発されているが、この技術につきまとう幾つかの問題が残されている。 Although technology to create a single crystal film [0008] has been well developed, some of the problems that beset this technology is left. 或る特定の問題は、表面粗さを除去するために研磨するので、デバイス層の最終的厚さおよび均一性が容易に制御されないことである。 Certain problems, since the polished to remove surface roughness, is that the final thickness and uniformity of the device layer is not easily controlled.
従って、スマート・カット・プロセスと同様であるが研磨による厚さの変動を受けないようなプロセスに対する必要性が存在する。 Therefore, it is similar to the Smart Cut process there is a need for a process that does not undergo variations in thickness due to polishing. また、シリコン製造と両立性があり,スマート・カット・プロセスとは関係なくSOIデバイス層の均一性及び厚さが選択及び制御可能であるようなプロセスに対する必要性がある。 There is also compatible with silicon manufacturing, the SmartCut process there is a need for processes such as uniformity and thickness of the regardless SOI device layer can be selected and controlled.

【0014】 [0014]

【課題を解決するための手段】本発明においては、エッチング停止層が出発基体のデバイス層の下に形成される。 In the present invention SUMMARY OF], the etch stop layer is formed under the device layer of the starting substrate. エッチング停止層を用いることにより、CMPの必要性が避けられ、最終的なデバイスの厚さ、均一性、および平滑性が付着されるフィルムによって決まることになる。 By using the etch stop layer, avoid the need CMP, a final device thickness will be determined by the film uniformity, and smoothness is deposited. このエッチング停止層は化学的蒸着(CVD)またはインプランテーションによって形成することができる。 The etch stop layer may be formed by chemical vapor deposition (CVD) or implantation.

【0015】本発明において、後で半導体構造が形成される実質的に均一な厚さの薄い半導体層は、半導体基体(この後シリコン(Si)基体と呼ばれる)から成る第1のウエハーを与え、第1のウエハーの上にエッチング停止層を形成し、エッチング停止層の上にエピタキシャル・デバイス層を形成し、デバイス層の上に接合層を形成し、埋設層をその中に形成するためにシリコン基体中にイオンをインプラントし、接合層を第2のウエハーに接合し、第1および第2ウエハーを加熱し、埋設層に沿って接合された第1および第2のウエハーを分離して第2のウエハーが第1のウエハーからのSiからなる最上部の表面層を持つようにし、最上部表面層およびエッチング停止層を取り除き、これによりエピタキシャル・デバイス層の下にあ [0015] In the present invention, later thin semiconductor layer of substantially uniform thickness that the semiconductor structure is formed, providing a first wafer comprising a semiconductor body (thereafter referred to as silicon (Si) substrate), silicon to the etch stop layer is formed on the first wafer, the epitaxial device layer is formed on the etch stop layer, forming a bonding layer over the device layer, forming a buried layer therein implanting ions into the substrate, bonding the bonding layer to the second wafer, and heating the first and second wafer, the second to separate the first and second wafer joined along a buried layer wafer is to have the uppermost surface layer of Si from the first wafer, the uppermost surface layer and removing the etch stop layer, located under the thereby epitaxial device layers 部分が第2のウエハーに残って薄い半導体層を形成するようにすることによって作られる。 Part is made by so as to form a thin semiconductor layer remaining on the second wafer.

【0016】本発明に含まれるもう1つの実施例は、エッチング停止層をそれ程侵さない第1のエッチング剤の中で最上部表面層をエッチングし、次にエピタキシャル・デバイス層の残存部分をそれ程侵さない第2のエッチング剤の中でエッチング停止層をエッチングすることを含む。 Another embodiment included in the [0016] present invention, the uppermost surface layer in the first etchant does not attack the etch stop layer so etched, then much affected the remaining portion of the epitaxial device layer no and etching the etch stop layer in a second etching agent.

【0017】本発明に含まれる更に別の実施例は、接合層およびエピタキシャル・デバイス層をフォトリトグラフによりパターン化してエッチングし、これによりイオン・インプラント・ステップの後にその中に開孔を形成することを含む。 Yet another embodiment included in the [0017] present invention, the bonding layer and the epitaxial device layer is patterned by photolithographic etching, thereby forming an opening therein after the ion implant step including.

【0018】本発明の上述の態様及びその他の態様は添付図面と共に以下の詳細な説明を考察することによって明らかとなるであろう。 The above and other aspects of the present invention will become apparent upon consideration of the following detailed description in conjunction with the accompanying drawings.

【0019】 [0019]

【発明の実施の形態】本発明はスマート・カット・プロセスにおいてエッチング停止層を用いることによりその改良を図る。 DETAILED DESCRIPTION OF THE INVENTION The present invention is achieved the improvement by using an etch stop layer in the SmartCut process. エッチング停止層があるのでウエハーが分離された後(図2のステップ125)化学的機械的研磨(CMP)が必要とされない。 After wafers have been separated because of the etch stop layer (step 125 in FIG. 2) is not a chemical mechanical polishing (CMP) is required. 従って、製造された絶縁体上のシリコン(SOI)型の基体におけるデバイス層の厚さおよび平滑度は、CMPのパラメータではなく、 Accordingly, the thickness and smoothness of the device layer in silicon (SOI) type substrate on fabricated insulator is not a parameter CMP, a
蒸着層の均一度および平滑度、並びに湿式エッチングの選択性によって決まる。 Uniformity and smoothness of the deposited layer, as well as determined by the selectivity of the wet etching. これによりデバイス層の平滑度および均一度が改善される。 Thus smoothness and uniformity of the device layer is improved.

【0020】図6は本発明による製造プロセスの例示的1実施例の流れ図である。 [0020] FIG. 6 is a flow diagram of an exemplary first embodiment of a manufacturing process according to the present invention. 図7ないし図13は、図6のプロセス流れ図から選ばれたステップの対応する断面図を示す。 7 to 13 shows the corresponding cross-sectional view of a step selected from the process flow diagram of FIG. 所望の配位を有する好適にはシリコンの単結晶半導体ウエハー500がステップ400における出発点として用いられる。 Suitable having the desired coordination single crystal semiconductor wafer 500 of silicon is used as the starting point in step 400. 出発ウエハー500のどの部分も最終的SOI構造において残らないので、ウエハー500 Since part of the starting wafer 500 throat also it does not remain in the final SOI structure, the wafer 500
はデバイス級の品質を持つ必要はない。 There is no need to have the quality of the device-class. ウエハー500 Wafer 500
は10 15ないし10 18不純物/cm 3の範囲の低いドープ濃度を有するのが普通である。 Typically have an low doping concentration in the range to 10 18 impurities / cm 3 10 15 no. 所定の組成および厚さの薄いエッチング停止層505がウエハー表面にエピタキシャルに成長される。 Thin etch stop layer 505 of a given composition and thickness is grown epitaxially on the wafer surface. エッチング停止層505は3. Etch stop layer 505 is 3.
9×10 -7ないし7.8×10 -5インチ(100ないし2000Å)の範囲の厚さであることが好ましく、特に約9.8×10 -7インチ(250Å)の厚さであることが最も好ましい。 It is preferably a thickness in the range of 9 × 10 -7 to 7.8 × 10 -5 inch (100 to 2000 Å), to be particularly thickness of about 9.8 × 10 -7 inches (250 Å) The most preferred. エッチング停止材料は基体材料に比べてそのエッチングの振る舞いが選択性であるように選ばれる。 Etch stop material is chosen to be the selectivity behavior of the etching than the substrate material. 例えば、高濃度にドープされた(p +またはp - For example, heavily doped (p + or p -)
シリコン層、シリコンーゲルマニウム(SiGe)層、 Silicon layer, silicon over germanium (SiGe) layer,
応力歪みSi−Ge層、またはGe層をエッチング停止層として用いることができる。 Stress strain Si-Ge layer, or Ge layer may be used as an etch stop layer. エッチング停止層505 Etch stop layer 505
は高濃度にドープされたSi−GeのGe補償層であることが好ましい。 Preferably is Ge compensation layer doped Si-Ge at high concentration. ドーパント濃度は10 20ないし10 21 Dopant concentration to 10 20 to 10 21
原子/cm 3の範囲の硼素であることが好ましい。 It is preferable that boron in the range of atoms / cm 3. この層は化学的蒸着(CVD)プロセスを用いて付着されるのが好ましい。 This layer preferably is deposited using chemical vapor deposition (CVD) process.

【0021】次に図7に示すように、選択された厚さおよびドーパント濃度の薄いデバイス層510がエッチング停止層505の上にエピタキシャルに付着される。 [0021] Next, as shown in FIG. 7, the thin device layer 510 having a thickness and dopant concentration selected is attached epitaxially on the etch stop layer 505. エッチング停止層505の選択は、高品質の格子位置の狂いが少ないデバイス層510が付着されるようにエッチング停止層505とデバイス層510との間の応力の不整合を考慮に入れる必要がある。 Selection of the etch stop layer 505, it is necessary to take into account the stress mismatch between the etch stop layer 505 and device layer 510 such that the device layer 510 deviations with less lattice positions of high quality is deposited. デバイス層510はS Device layer 510 S
i、Si−Ge、Ge、またはその他任意の化合物半導体であって良い。 i, Si-Ge, Ge or other may be any compound semiconductor. この用途に用いられるSi−Ge層は5ないし30原子パーセントのGeを含んでよい。 Si-Ge layer used in this application may comprise a Ge of 5 to 30 atomic percent. デバイス層510の厚さは約3.9×10 -6インチ(100 The thickness of the device layer 510 is approximately 3.9 × 10 -6 inches (100
0Å)であることが好ましく、デバイスの応用上の必要に応じて2×10 -6ないし2×10 -5インチ(500ないし5000Å)の範囲であって良い。 Is preferably 0 Å), to 2 × 10 -6 not as required by the applications of the device may range from 2 × 10 -5 inch (500 to 5000 Å).

【0022】ステップ405でデバイス層510の表面上に酸化物層515(即ち、接合層または誘電体層)が形成される。 The oxide layer 515 on the surface of the device layer 510 at step 405 (i.e., bonding layer or dielectric layer) is formed. 接合層515はデバイス層510の一部を熱的に酸化することによって形成されるのが好ましいが、高品質の付着酸化物(熱酸化物と同様なもの)を用いることもできる。 Bonding layer 515 is preferably formed by oxidizing a portion of the device layer 510 thermally, it is also possible to use a high-quality adhesion oxides (those similar to the thermal oxide). 図8はデバイス層510の一部が熱的に酸化物層515に変換されており、層510の厚さが対応して減少していることを示す。 Figure 8 is converted portion of the device layer 510 is thermally oxide layer 515, indicating that the thickness of layer 510 is reduced correspondingly. 厚さが減少したデバイス層を510'で示す。 Thick device layers with reduced illustrated at 510 '. 2酸化シリコンを付着するためには種々のCVDおよび物理的付着プロセスを用いることができる。 To attach the silicon dioxide can be used various CVD and physical deposition processes. 熱酸化によりデバイス層510をその場で酸化物に変換するには炉での酸化または急速熱酸化によって行うことができる。 To convert the oxide to device layer 510 in situ by thermal oxidation may be carried out by oxidation or rapid thermal oxidation in a furnace. 層505、510及び51 Layers 505, 510 and 51
5の合計厚さは約0.8×10 -5ないし4×10 -5インチ(2000Åないし1μm)の範囲であるのが普通である。 The total thickness of 5 is usually in the range of about 0.8 × 10 -5 to 4 × 10 -5 inch (2000 Å to 1 [mu] m).

【0023】ステップ410で、10 -16ないし2×1 [0023] In step 410, 10 -16 to 2 × 1
-17イオン/cm 2の濃度、50ないし150KeV 0 -17 concentration of ions / cm 2, 50 to 150KeV
のインプランテーション・エネルギで基体500に水素イオンがインプラントされる。 The substrate 500 in the implantation energy of the hydrogen ions are implanted into. より大きな基体ではより高い濃度を用いることができる。 It can be used in higher concentrations with larger substrates. 水素インプランテーションは酸化物層515の最上部表面から約4×10 -5ないし8×10 -5インチ(1ないし2μm)の深さの所に水素が豊富な層520を形成する。 Hydrogen implantation to form hydrogen at the depth of about 4 × 10 -5 missing from the top surface to 8 × 10 -5 inch (1 to 2 [mu] m) rich layer 520 of the oxide layer 515. エッチング停止層5 Etch stop layer 5
05、デバイス層510及び表面酸化物層515の厚さは判っているので、インプラントされる水素のピークがエッチング停止層の下の所望の深さの所に生じるように適正なインプランテーション電圧を選択することができる。 05, since the thickness of the device layer 510 and the surface oxide layer 515 is known, select the proper implantation voltage such that the peak of hydrogen implant occurs at the desired depth below the etch stop layer can do.

【0024】表面酸化物層535を有する支持ウエハー基体530が与えられ、ステップ415で基体500及び530の両方ともRCAクリーニング・プロセスのような普通の湿式処理を用いてクリーニングされる。 [0024] Given a support wafer substrate 530 having a surface oxide layer 535 is cleaned using conventional wet processing, such as RCA cleaning process both substrates 500 and 530 in step 415. クリーニングにより層515及び535の表面から表面不純物および粒子が取り除かれる。 Surface impurities and particles are removed from the surface of the layer 515 and 535 by the cleaning. クリーニングその他の処理は、層515及び535の表面に舞い落ちる粒子の数を最小にするためクリーン・ルームで行われることが好ましいことに留意されたい。 Cleaning other processes, it should be noted that it is preferably carried out in a clean room for the number of particles falling dance on the surface of the layer 515 and 535 to a minimum.

【0025】図9に示されるようにステップ420で、 [0025] In step 420 as shown in FIG. 9,
層515及び535の表面は親水性により接合される。 Surface of layer 515 and 535 are joined by a hydrophilic.
親水性接合は露呈された表面をクリーニングし、表面を濡らし、表面同士を互いに接触させ、そして表面同士を押しつけ合うことにより行われる。 Hydrophilic bonding to clean the exposed surface, wet the surface, the surfaces on each brought into contact with each other, and is performed by mutually pressing surfaces together. 親水性による接合は室温で行われることが好ましい。 Bonding with the hydrophilic is preferably performed at room temperature.

【0026】引き続きステップ425で、約400ないし600℃の間の温度まで加熱することにより、接合されたウエハーがアニールされる。 [0026] Continuing at step 425, by heating to a temperature between from about 400 to 600 ° C., bonded wafers are annealed. この温度は約500℃ This temperature is about 500 ℃
で約30ないし120分の間であることが好ましい。 It is preferred in from about 30 to between 120 minutes. アニールすることにより水酸化物相が形成され、水酸化物相がリンクされ、この結果、図9に示すように基体50 Hydroxide phase is formed by annealing, hydroxides phase is linked, as a result, the substrate 50 as shown in FIG. 9
0の層520に沿って接合されたウエハーが割れたり、 Wafers cracked joined along the layer 520 of 0,
または劈開されたりすることになる。 Or will or is cleaved. これは2つの別個の構造体をもたらす。 This results in two separate structures. 1つは基体500'で有り、これは本質的にウエハー500である。 One is an base 500 ', which is essentially a wafer 500. もう1つは基体53 Another is the substrate 53
0であり、これは層505、510'および515と共に薄い最上部表面層500”を有する。図11は分離ステップの後のSOIウエハーの構造を示す。層500” 0, which is a thin top surface layer 500 with a layer 505, 510 'and 515 "having. Figure 11. Layer 500 shows the structure of an SOI wafer after the separation step"
はインプラントの深さおよびデバイス、エッチング停止層および酸化物層の厚さに基づいて約1×10 -5ないし4×10 -5インチ(2500Åないし1μm)の範囲の厚さである。 Is the thickness in the range of about 1 × 10 -5 to 4 × 10 -5 inches based on the thickness of the depth of the implants and devices, etch stop layer and the oxide layer (2500 Å to 1 [mu] m).

【0027】次に、薄いシリコン層510'(デバイス層)がまだ接合されている支持基体530を高温度(約1000℃)で約30分ないし8時間の間アニールして支持基体530及びデバイス層510'の間の接合を強化することが好ましい。 Next, a thin silicon layer 510 '(the device layer) are still supporting substrate 530 and device layer supporting substrate 530 are bonded by annealing during high temperature (about 1000 ° C.) for about 30 minutes to 8 hours it is preferred to strengthen the bond between the 510 '.

【0028】ステップ430で薄い最上部表面層50 [0028] The top surface layer 50 thin in step 430
0”を除去するため選択的な湿式エッチングが行われる。エッチングはエッチング停止層505によって停止される。層500”の形状または粗さおよび非均一性はエッチングの選択性に応じて十分に低減される。 0 "is selective wet etching for removing is performed. Etching is stopped by the etching stop layer 505. Layer 500" shape or roughness and non-uniformity of sufficiently reduced depending on the etch selectivity that. 10倍の中庸の選択性はエッチング停止層505の上で10倍だけ層500”の粗さおよび非均一性を低減する。例えば、7.8×10 -7ないし1.2×10 -6インチ(20 10 times moderate selectivity reduces the roughness and non-uniformity of only the layer 500 "10 times over the etch stop layer 505. For example, 7.8 × 10 -7 to 1.2 × 10 -6 inch (20
0ないし300Å)の粗さはエッチング停止表面の上で7.8×10 -7インチ(20Å)以下まで低減されるであろう。 0 to 300 Å) of the roughness will be reduced to 7.8 × 10 -7 inches (20 Å) or less on the etching stop surface. 水酸化カリウム(KOH)または水酸化アンモニウム(NH4OH)などの腐食性のエッチング溶液は高濃度にドープされたSiまたはSi−Geに比べて低濃度にドープされたシリコンを100対1またはそれ以上の比率でエッチする(即ち、低濃度にドープされた基体対エッチング停止層のエッチングの選択性は100対1である)。 Potassium hydroxide (KOH) or corrosive etching solution such as ammonium hydroxide (NH4 OH) is high-concentration silicon lightly doped compared to the doped Si or Si-Ge in a 100-to-1 or more etched in a ratio (i.e., the etching selectivity of the base pairs etch stop layer doped to a low concentration is 100 to 1). その後残存するエッチング停止層505はステップ435で湿式または乾式エッチングにより除去される。 Etch stop layer 505 which then remaining is removed by wet or dry etching in step 435. 選択性プロセスは好ましく、2倍と言う低い選択性であっても有益である。 Selectivity process is preferably beneficial even at low selectivity to say twice. 図13は例示的プロセスから得られる完成SOIウエハーを研磨していない状態で示す。 Figure 13 shows a state in which no polishing the finished SOI wafer obtained from an exemplary process. またここでデバイス層の厚さはデバイス層の付着の均一性およびエッチング停止層によって正確に制御されている。 The thickness of the case in the device layer is precisely controlled by the uniformity and the etch stop layer deposition of device layers.

【0029】結果として得られるデバイス層510'は蒸着された状態のデバイス層510の平滑度とほぼ同じ平滑度を有し、仕上げを必要としない。 The resulting device layer 510 obtained 'has almost the same smoothness as the smoothness of the device layer 510 of the state of being deposited, does not require finishing. エッチング停止層505及びデバイス層510は蒸着層であるから、ウエハー全体にわたって非常に良好な均一度及び厚さの制御が可能であり、これはこの例示的プロセスにおいても当てはまる。 Since the etching stop layer 505 and device layer 510 is deposited layer, it is possible to control the very good uniformity and thickness throughout the wafer, which is true in this exemplary process.

【0030】図14は本発明による製造プロセスの別の例示的実施例のプロセス流れ図を示す。 [0030] Figure 14 shows a process flow diagram of another exemplary embodiment of a manufacturing process according to the present invention. 図14において、プロセス・ステップは図6に関して述べたものと同じであるが、接合における問題を除くために追加のプロセス・ステップが用いられている点だけが異なる。 14, process steps are the same as that described with respect to FIG. 6, only in that additional process steps to eliminate the problems in the joint is used is different. 物理的接合の品質は接合面にある粒子の存在および局部的なウエハーの歪みにより不利な影響を受ける。 Quality of the physical junction adversely affected by distortion of the presence and local wafer particles in the bonding surface. 物理的接合を作り上げるために相当な力でもってこれらの面を密に接触させる場合でも高品質の表面が必要である。 Requires a high quality surface even when the physical is intimate contact of these surfaces bonded to each other with a considerable force in order to make up the. 例えば、ウエハーの上に3、4個の粒子があってもウエハーの大面積の密な接触が妨げられることがある。 For example, it may intimate contact a large area of ​​the wafer even if three or four particles on the wafer is prevented.

【0031】この問題を最小にする1つの方法はフォトリトグラフィおよびエッチング・プロセスを用いて酸化物層515及びデバイス層510を、ここのチップ・サイズに相当する大きな表面アイランドまたは溝の形にパターン化することである。 The pattern of the oxide layer 515 and device layer 510 using one of the methods photolithographic and etching processes to minimize this problem, in the form of large surface islands or grooves corresponding to the individual chip size it is to reduction. これはウエハー上の個々の粒子がそれが置かれた個々のアイランドに影響を与えるが隣のアイランドには影響を与えないようにする。 This affects the individual islands individual particles it is placed on the wafer but so as not to affect the next island. これは、1つの大きな領域の代わりに複数のより小さな領域が取り付けられ、接合されると言う利点を与える。 This multiple smaller areas instead of one large area is attached, giving the advantage that the junction. このようにして、デバイス・アイランドの大きな領域が首尾良く転写されデバイスをつくるために使用できるようになる。 In this way, it becomes possible to use for large areas of the device islands make successfully transferred device.

【0032】更に、窪んだ領域はクリーニングの間に粒子のトラップとして働いて接合プロセスからの歩留まりを高めるのに役立つ。 Furthermore, recessed regions serve to increase the yield from the bonding process works as a trap particles during cleaning. 更に、ウエハーの1つに局部的な歪みがあると個々のチップの場所が失われることになるが、デバイス層全体で場所が失われるわけではない。 Furthermore, if there is localized strain to one of the wafer is so that the location of the individual chips is lost, not the location is lost throughout the device layer. 図14はプロセス・ステップについて図6と同じであるが、ステップ410がステップ600と置き換えられる点だけが異なる。 Figure 14 is the same as FIG. 6, process steps, only in that step 410 is replaced with step 600 are different. ステップ600において、追加のパターン化ステップが含まれている。 In step 600, it contains additional patterning step. アイランドまたは溝は4×10 -5ないし8×10 -5インチ(1ないし2μm) Islands or grooves 4 × 10 -5 to 8 × 10 -5 inch (1 to 2 [mu] m)
の深さにエッチングされるのが好ましい。 It is preferably etched to a depth of. 溝は酸化物層およびデバイス層を通り越してエッチングされることが好ましいが、エッチング停止層505に入り込んでも良い。 While grooves are preferably etched past the oxide layer and the device layer may penetrate the etch stop layer 505.

【0033】本発明は、シリコン−ゲルマニウム(Si [0033] The present invention is, silicon - germanium (Si
−Ge)、Ge、およびSiの薄層を層が蒸着されるにつれて絶縁性基体上のサンドイッチ構造として形成する有利な方法を提供する。 -Ge), Ge, and a layer a thin layer of Si to provide an advantageous method of forming a sandwich structure on the insulating substrate as it is deposited. 例えば、Si/SiGe/Si For example, Si / SiGe / Si
/SiO 2の最終的構造を形成することを望むならば、 If / desired to form the final structure of SiO 2,
デバイス・ウエハーの上に高濃度にドープされたSiG SiG that has been doped at a high concentration on top of the device wafer
eエッチング停止層を付着し、これに続いてSi/Si Adhering the e etch stop layer, following which Si / Si
Ge/Si層を付着する。 Depositing a Ge / Si layer. 最上部のシリコン層の一部が接合を与えるために酸化されうる。 Some of the top silicon layer may be oxidized to give the joint. その他のプロセス・ Other Process
ステップは図6および図14に関して述べたのと同じである。 Steps are the same as described with respect to FIG. 6 and FIG. 14. SiGeデバイス層は高周波トランジスタを形成するのに望ましい。 SiGe device layer desirable to form the high-frequency transistor.

【0034】本発明はスマート・カット・プロセスおよびBESOIプロセスの望ましい面を組み合わせてこれらプロセス単独で得られるものより均一性の優れた薄いデバイスSOI層を実現する。 The present invention provides excellent thin device SOI layer uniformity than that obtained with these processes alone in combination the desired surface of the SmartCut process and BESOI process. 本発明はCMPの必要性を除くためにエッチング停止層を使用してデバイス層の厚さの正確な制御を実現する。 The present invention realizes precise control of the thickness of the device layer using the etch stop layer in order to eliminate the need for CMP. デバイス層の均一性はスマート・カット・プロセスまたはCMPプロセスとは無関係である。 Uniformity of the device layer is independent of the SmartCut process or CMP process. 本発明はスマート・カット・プロセスのコスト的な利点を保って、それを均一な薄いデバイス層をより容易にかつ高い信頼度で得るように拡張するものである。 The present invention maintains the cost benefits of Smart Cut process, to extend it to a uniform thin device layers so as to obtain more easily and reliably. 本発明は平滑で均一なデバイス層を有するSOI The invention SOI having a smooth and uniform device layer
ウエハーを得るために分離後の研磨を何ら必要としない。 It does not require any grinding after separation in order to obtain a wafer. 本発明はスマート・カット・プロセスの限界を超えてより良好な歩留まりを可能にし、デバイス層の厚さに対してより良い制御を与える。 The present invention allows a better yield beyond the limits of the Smart Cut process, giving a better control of the thickness of the device layer.

【0035】本発明はある種の特定の実施例を参照して説明されたが、本発明はここで示されたものに限定されることを意図するものではない。 The present invention has been described with reference to a particular embodiment certain, the present invention is not intended to be limited to those shown here. 本発明の精神から逸脱することなく、特許請求の範囲の均等物の範囲において種々の変更が細部において加えられ得ることは言うまでもない。 Without departing from the spirit of the present invention, it is needless to say that various modifications may be added in the details within the scope of equivalency of the claims.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】従来型のSOIウエハーの側面図を示す。 1 shows a side view of a conventional SOI wafer.

【図2】従来のスマート・カット・プロセスのプロセス・ステップの流れ図を示す。 Figure 2 illustrates a flow diagram of process steps of a conventional Smart Cut process.

【図3】図2のプロセスに従って製造される従来のウエハーの側面図である。 3 is a side view of a conventional wafer produced according to the process of FIG.

【図4】図2のプロセスに従って製造される従来のウエハーの側面図である。 4 is a side view of a conventional wafer produced according to the process of FIG.

【図5】図2のプロセスに従って製造される従来のウエハーの側面図である。 5 is a side view of a conventional wafer produced according to the process of FIG.

【図6】本発明による例示的製造プロセスのプロセス流れ図を示す。 6 shows a process flow diagram of an exemplary manufacturing process according to the present invention.

【図7】図6のプロセスに従って製造されるウエハーの側面図である。 7 is a side view of a wafer manufactured according to the process of FIG.

【図8】図6のプロセスに従って製造されるウエハーの側面図である。 8 is a side view of a wafer manufactured according to the process of FIG.

【図9】図6のプロセスに従って製造されるウエハーの側面図である。 9 is a side view of a wafer manufactured according to the process of FIG.

【図10】図6のプロセスに従って製造されるウエハーの側面図である。 10 is a side view of a wafer manufactured according to the process of FIG.

【図11】図6のプロセスに従って製造されるウエハーの側面図である。 11 is a side view of a wafer manufactured according to the process of FIG.

【図12】図6のプロセスに従って製造されるウエハーの側面図である。 12 is a side view of a wafer manufactured according to the process of FIG.

【図13】図6のプロセスに従って製造されるウエハーの側面図である。 13 is a side view of a wafer manufactured according to the process of FIG.

【図14】本発明による別の例示的製造プロセスのプロセス流れ図を示す。 14 shows a process flow diagram of another exemplary manufacturing process according to the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

500:ウエハー 505:エッチング停止層 510:デバイス層 515:接合層 520:水素が豊富な層 530:支持ウエハー基体 535:酸化物層 500: Wafer 505: etch stop layer 510: a device layer 515: bonding layer 520: a hydrogen-rich layer 530: supporting the wafer substrate 535: oxide layer

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平7−142502(JP,A) 特開 平9−162090(JP,A) 特開 昭62−122148(JP,A) 特開 平8−139297(JP,A) 特開 平4−302160(JP,A) 特開 平10−335616(JP,A) 特表 平4−506587(JP,A) 米国特許5374564(US,A) (58)調査した分野(Int.Cl. 7 ,DB名) H01L 21/02 H01L 27/12 H01L 21/265 ────────────────────────────────────────────────── ─── continued (56) references of the front page Patent flat 7-142502 (JP, a) JP flat 9-162090 (JP, a) JP Akira 62-122148 (JP, a) JP flat 8- 139297 (JP, A) JP flat 4-302160 (JP, A) JP flat 10-335616 (JP, A) JP-T flat 4-506587 (JP, A) United States Patent 5374564 (US, A) (58) survey the field (Int.Cl. 7, DB name) H01L 21/02 H01L 27/12 H01L 21/265

Claims (25)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】後で半導体構造が形成される実質的に均一な厚さの薄い半導体層を形成する方法であって、 半導体基体から成る第1のウエハーを与えるステップと、 第1のウエハーの上にエッチング停止層を形成するステップと、 エッチング停止層の上にデバイス層を形成するステップと、 デバイス層の上に接合層を形成するステップと、 埋設層をその中に形成するために前記半導体基体中にイオンをインプラントするステップと、 接合層を第2のウエハーに接合するステップと、 第1および第2ウエハーを第1の温度に加熱するステップと、 接合された第1および第2のウエハーを埋設層に沿って分離して第2のウエハーが最上部の表面層を持つようにする分離ステップと、 最上部の表面層およびエッチング停止層を取り除くステップ 1. A method of later forming a thin semiconductor layer of substantially uniform thickness that the semiconductor structure is formed, and providing a first wafer comprising a semiconductor body, the first wafer forming an etch stop layer above the semiconductor forming a device layer on the etch stop layer, forming a bonding layer over the device layer, a buried layer to form therein a step of implanting ions into the substrate, a step of bonding the bonding layer to the second wafer, and heating the first and second wafer to the first temperature, the first and second wafer joined step of removing the separating step, the surface layer and the etching stop layer at the top of the second wafer is separated along the buried layer is made to have a surface layer of the top of the 、 を含み、これによりデバイス層の下にある部分が第2のウエハーに残って薄い半導体層を形成するようにすることを特徴とする方法。 It includes, thereby method, wherein a portion of the underlying device layer to form the remaining thin semiconductor layer on the second wafer.
  2. 【請求項2】前記分離ステップの後、前記最上部の表面層を有する前記第2のウエハーを第2の温度まで加熱するステップを更に含む請求項1の方法。 Wherein after said separating step, the method of claim 1, further comprising the step of heating the second wafer to a second temperature with the uppermost surface layer.
  3. 【請求項3】第2のウエハーを加熱する前記ステップは30分ないし8時間の範囲にわたって1000℃でアニールすることを含む請求項2の方法。 3. A method according to claim 2 wherein the step of including an annealing at 1000 ° C. over a range of 30 minutes to 8 hours of heating the second wafer.
  4. 【請求項4】前記半導体基体はシリコン(Si)基体であり、前記イオンは水素イオンであり、前記埋設層は水素およびシリコンから成る請求項1の方法。 Wherein said semiconductor body is a silicon (Si) substrate, the ions are hydrogen ions, the buried layer The method of claim 1 consisting of hydrogen and silicon.
  5. 【請求項5】前記水素イオンは50ないし150KeV Wherein said hydrogen ions to free 50 150 KeV
    の範囲のエネルギ、および2×10 16ないし1×10 17 Energy range, and 2 × to 10 16 to 1 × 10 17
    イオン/cm 2の範囲の濃度でインプラントされる請求項4の方法。 The method of claim 4, which is implanted in a concentration range of the ion / cm 2.
  6. 【請求項6】前記埋設層は前記接合層の最上部の表面の1ないし2μmの深さの所に形成される請求項1の方法。 6. The method of claim 1 wherein the buried layer is formed at the 1 to 2μm depth of the uppermost surface of the bonding layer.
  7. 【請求項7】前記加熱するステップは30分ないし12 7. A to step to 30 minutes for the heating 12
    0分の範囲の間400℃ないし600℃の範囲の温度でアニールすることを含む請求項1の方法。 400 no ° C. during the range of 0 minutes to the method of claim 1, comprising annealing at a temperature in the range of 600 ° C..
  8. 【請求項8】前記接合層を前記第2のウエハーに接合する前記ステップは親水性接合である請求項1の方法。 Wherein said step of bonding the bonding layer to said second wafer process according to claim 1 which is hydrophilic bonding.
  9. 【請求項9】前記半導体基体はSi基体であり、前記接合層を前記第2のウエハーに接合する前記ステップは、 前記第2のウエハーの露呈された表面上に2酸化シリコンの層を形成するステップと、 前記接合層および前記2酸化シリコン層を濡らすステップと、 前記接合層および前記2酸化シリコン層を接触させるステップと、 前記接合層および前記2酸化シリコン層を互いに押圧してその間に接合を形成するステップと、 を含む、請求項1の方法。 Wherein said semiconductor body is a Si substrate, said step of bonding the bonding layer to said second wafer to form a layer of silicon dioxide on said second exposed surface of the wafer a step, a step of wetting the bonding layer and the silicon dioxide layer, contacting said bonding layer and said silicon dioxide layer, a bonding therebetween by pressing together the bonding layer and the silicon dioxide layer and forming, a method of claim 1.
  10. 【請求項10】前記最上部の表面層および前記エッチング停止層を取り除く前記ステップは、 前記エッチング停止層をそれ程侵さない第1のエッチング剤で前記最上部の表面層をエッチングするステップと、 前記デバイス層の残存部をそれ程侵さない第2のエッチング剤で前記エッチング停止層をエッチングするステップと、 を含む請求項1の方法。 Step 10. removing the surface layer and the etching stop layer of the uppermost, etching the surface layer of the top in a first etchant which does not significantly affected the etch stop layer, the device the method of claim 1 including the steps of etching the etch stop layer with a second etchant which does not significantly affected the remaining portion of the layer, the.
  11. 【請求項11】前記第1のエッチング剤は水酸化カリウムまたは水酸化アンモニウムの溶液から成る請求項10 Wherein said first etchant claim consisting of a solution of potassium hydroxide or ammonium hydroxide 10
    の方法。 the method of.
  12. 【請求項12】前記最上部の表面層および前記エッチング停止層を取り除く前記ステップは、10対1以下の選択性を持つ低い選択性のエッチング剤で前記最上部の表面層を取り除き、続いて10対1以下の選択性のエッチング剤で前記エッチング停止層を取り除くことを含む請求項1の方法。 Step 12. removing the surface layer and the etching stop layer of the uppermost removes the surface layer of the top at a low selectivity of the etchant with 10: 1 or less selectivity, followed by 10 the method of claim 1, comprising removing the etch stop layer in-one following selective etchant.
  13. 【請求項13】前記半導体基体はSi基体であり、前記エッチング停止層は高濃度にドープされたSi層、シリコン−ゲルマニウム(Si−Ge)層、応力歪みSi− Wherein said semiconductor body is a Si substrate, the etch stop layer is Si layer doped in a high concentration, silicon - germanium (Si-Ge) layer, stress strain Si-
    Ge層、Ge層、およびSi−GeのGeで補償された層の何れかである請求項1の方法。 Ge layer, Ge layer, and Si-Ge method of claim 1 Ge is either compensated layers in the.
  14. 【請求項14】前記エッチング停止層は10 20ないし1 14. The etch stop layer 10 20 to 1
    21原子/cm 3の範囲の濃度の硼素でドープされる請求項1の方法。 0 21 The method of claim 1 which is doped with boron at concentrations ranging atoms / cm 3.
  15. 【請求項15】前記エッチング停止層の厚さは100ないし2000Åの範囲である請求項1の方法。 15. The method of claim 1, the thickness of the etching stop layer is in the range of 100 to 2000 Å.
  16. 【請求項16】前記エッチング停止層の厚さは250Å 16. The thickness of the etch stop layer is 250Å
    である請求項15の方法。 The method of claim 15 is.
  17. 【請求項17】前記エッチング停止層を形成する前記ステップは化学的蒸着を用いる請求項1の方法。 17. wherein said step of forming said etch stop layer The method of claim 1 using a chemical vapor deposition.
  18. 【請求項18】前記半導体基体はSi基体であり、前記デバイス層はSi、Ge、またはSi−Geの1つである請求項1の方法。 18. The semiconductor substrate is Si substrate, the device layer is Si, Ge or Si-Ge 1 one by method according to claim 1 which is a.
  19. 【請求項19】前記デバイス層は5ないし30パーセントの範囲内の原子パーセントのGeを含むSi−Geである請求項18の方法。 19. The device layer is 5 to 19. The method of claim 18, a Si-Ge containing atomic percent Ge in the range of 30%.
  20. 【請求項20】前記半導体基体はSi基体であり、前記デバイス層はSi、Ge、およびSi−Geの内の少なくとも1つである請求項1の方法。 20. The semiconductor substrate is Si substrate, the device layer is Si, Ge, and at least one a method according to claim 1 which is of the Si-Ge.
  21. 【請求項21】前記デバイス層の厚さは500ないし5 21. It is 500 thickness of the device layer 5
    000Åの範囲内である請求項1の方法。 The method of claim 1 in the range of 000A.
  22. 【請求項22】前記デバイス層の厚さは1000Åである請求項21の方法。 22. The method of claim 21 the thickness of the device layer is 1000 Å.
  23. 【請求項23】前記接合層およびデバイス層をフォトリトグラフによりパターン化してエッチングし、これにより前記接合するステップの前に開孔を形成するステップを更に含む請求項1の方法。 23. etched and patterned by photolithographic the bonding layer and the device layer, The method of claim 1, which further comprises a step of forming an opening before the step of bonding.
  24. 【請求項24】前記半導体基体はシリコンである請求項1の方法。 24. The method of claim 1 wherein the semiconductor substrate is silicon.
  25. 【請求項25】絶縁性構造体の上に薄いシリコン層を形成する方法であって、 シリコン基体から成る第1のウエハーを与えるステップと、 第1のウエハーの上にエッチング停止層を形成するステップと、 エッチング停止層の上にデバイス層を形成するステップと、 デバイス層の上に接合層を形成するステップと、 水素が豊富な埋設層をその中に形成するために前記シリコン基体中に水素イオンをインプラントするステップと、 第2のウエハーの露呈された表面上に2酸化シリコンの層を形成するステップと、 前記接合層および前記2酸化シリコン層を濡らすステップと、 前記接合層及び前記2酸化シリコン層を互いに接触させるステップと、 前記接合層及び前記2酸化シリコン層の間に親水性接合を形成するために前記接合層及び前記 25. A method of forming a thin silicon layer on an insulating structure, and providing a first wafer made of silicon substrate, forming an etch stop layer on the first wafer When, step a, forming a bonding layer over the device layer, hydrogen ions into the silicon substrate in the hydrogen form rich buried layer therein to form a device layer on the etch stop layer a step of implanting, forming a layer of silicon dioxide on the exposed surface of the second wafer, the steps of wetting the bonding layer and the silicon dioxide layer, the bonding layer and the silicon dioxide contacting the layers together, said bonding layer and said to form a hydrophilic bonding between the bonding layer and the silicon dioxide layer 酸化シリコン層を互いに押しつけるステップと、 前記接合された第1および第2ウエハーを第1の温度でアニールするステップと、 接合された第1および第2のウエハーを前記埋設層に沿って分離して第2のウエハーが前記第1のウエハーからのSiから成る最上部の表面を有するようにする分離ステップと、 前記最上部の表面を有する前記第2のウエハーを第2の温度でアニールするステップと、 前記エッチング停止層の残存部分をそれ程侵さない第1 A step of pressing the silicon oxide layer to each other, the first and second wafer which is the bonding and annealing at a first temperature and a first and a second wafer joined to separate along said buried layer a separation step of the second wafer to have a top surface consisting of Si from the first wafer, a step of annealing said second wafer having a top surface at a second temperature first not so affected the remaining portion of said etch stop layer
    のエッチング剤で前記最上部の表面層をエッチングするステップと、 前記デバイス層の残存部分をそれ程侵さない第2のエッチング剤で前記エッチング停止層をエッチングするステップと、 を含み、これによりデバイス層の下にある部分が第2のウエハーに残って、前記絶縁性構造体の上に薄いシリコン層を形成するようにすることを特徴とする方法。 Of etching the surface layer of the top in the etching agent includes a step of etching the etch stop layer with a second etchant which does not significantly affected the remaining portion of the device layer, thereby the device layer how the underlying portions remaining in the second wafer, characterized in that to form a thin silicon layer on the insulating structure.
JP23775198A 1997-08-26 1998-08-24 Improved Smart Cut process for the manufacture of semiconductor material thin film Expired - Lifetime JP3037934B2 (en)

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