KR100676827B1 - Semiconductor wafer having strained silicon layer, method of fabricating the same and semiconductor device using the same - Google Patents

Semiconductor wafer having strained silicon layer, method of fabricating the same and semiconductor device using the same Download PDF

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KR100676827B1
KR100676827B1 KR1020050081846A KR20050081846A KR100676827B1 KR 100676827 B1 KR100676827 B1 KR 100676827B1 KR 1020050081846 A KR1020050081846 A KR 1020050081846A KR 20050081846 A KR20050081846 A KR 20050081846A KR 100676827 B1 KR100676827 B1 KR 100676827B1
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substrate
layer
silicon layer
method
silicon
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Korean (ko)
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박재근
이곤섭
이상현
이재춘
홍진균
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박재근
주식회사 실트론
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

A semiconductor wafer having a strained silicon layer, a method for fabricating the same, and a semiconductor device using the same are provided to form the strained silicon layer only by executing a thinning process. A first substrate having a single crystal silicon layer and a second substrate with an insulating layer(62) formed thereon are prepared. A relaxed silicon germanium layer(52) is formed on the silicon layer of the first substrate. The first substrate is implanted with an impurity ion at a specific depth from a surface thereof to form an impurity ion implanted region. The first substrate and the second substrate are bonded so that the silicon germanium layer and the insulating layer come in contact with each other. The substrates are subjected to an annealing process, and the silicon layer is subjected to a thinning process to form a strained silicon layer(50c).

Description

Semiconductor wafer having strained silicon layer, method of fabricating the same and semiconductor device using the same}

1 to 5 are process cross-sectional views illustrating a process step of manufacturing a conventional strained SGOI wafer.

6 to 8 are AFM photographs showing the surface state of a buffered silicon germanium layer according to the concentration of germanium in a conventional strained SGOI wafer.

FIG. 9 is a graph showing threading dislocation density versus removal thickness of a buffered silicon germanium layer in a conventional strained SGOI wafer. FIG.

10 to 14 are process cross-sectional views illustrating a process step of manufacturing a strained SGOI wafer according to an embodiment of the present invention.

15 to 18 are graphs showing concentrations of germanium according to depth in a strained SGOI wafer according to an embodiment of the present invention.

 19 to 22 are micrographs showing the surface state of a relaxed silicon germanium layer in a strained SGOI wafer according to an embodiment of the present invention.

23 to 26 are AFM photographs showing a surface state of a relaxed silicon germanium layer in a strained SGOI wafer according to an embodiment of the present invention.

FIG. 27 illustrates a strained silicon layer formed on a silicon germanium layer in a strained SGOI wafer according to an embodiment of the present invention.

29 is a graph showing a germanium concentration and thickness relationship for forming a strained silicon layer in a strained SGOI wafer according to an embodiment of the present invention.

30 is a cross-sectional view illustrating an example of a MOS transistor manufactured using a strained SGOI wafer according to an embodiment of the present invention.

※ Explanation of codes for main parts of drawing

50; First substrate 52; Relaxed silicon germanium layer

50c; Strained silicon layer 60; Second substrate

62; Insulation layer

The present invention relates to a semiconductor wafer, and more particularly, to a method of manufacturing a strained SGOI (Silicon Germanium On Insulator) wafer comprising a strained silicon layer, and a semiconductor wafer and a semiconductor device manufactured accordingly will be.

Junction isolation in bulk silicon substrates used to fabricate conventional silicon integrated circuits is difficult because of junction breakdown under supply voltages of ± 30 V under moderate doping levels and dimensions. Not only are they unsuitable for pressure applications, but junction separation is not effective under high radioactivity due to transient photocurrent generated at pn junctions by gamma rays. Therefore, SOI technology, which is a separation technology that completely surrounds the device as an insulator instead of a pn junction, has been developed, and the circuit fabricated in such an SOI substrate has a simpler fabrication process and result structure compared to the circuit fabricated in a bulk silicon substrate. Since the size can be reduced and the parasitic capacitance is reduced along with the reduction of the chip size, the operation speed of the circuit is high.

Such SOI technology includes SOS (Silicon On Sapphire) technology that grows a heteroepitaxial silicon layer on sapphire, and SIMOX (Separation by IMplaneted OXygen) technology that forms an buried silicon oxide layer by injecting oxygen ions into a silicon substrate and then annealing them. Bonding SOI (Bonding SOI) technology is known in which at least one wafer having an insulating layer formed on its surface and another wafer are bonded together.

As an example using this bonding SOI technology, the so-called "Smart-Cut" process technology used to make so-called UNIIBOND wafers is well known. The smart-cut process technology is a technique of implanting hydrogen ions into one of the wafers bonded to form a fine bubble layer, and then cleaving the wafer around the bubble layer by heat treatment.

On the other hand, remarkable developments have been made in optoelectronic devices and electronic devices having a strained layer heterostructure in group III-V compound semiconductors and group IV mixtures Si-Ge. The excellent optoelectronic properties and high speed performance of Si 1 - x Ge x / Si strained layer devices such as heterojunction bipolar transistors (HBTs), resonant tunneling diodes, and light emitting diodes (LEDs) provide structural integrity during epitaxial growth and thermal processes. Strongly influenced by retention. For heterogeneous applications, these heterostructures are generally metastable and attempt to relax through the introduction of incompatible dislocations at the Si 1 - x Ge x / Si interface during exposure to high temperatures. (See DC Houghton's article "Strain relaxaion kinetics in Si 1- x Ge x / Si heterostructures" (J. Appl. Phys. Vol. 70, No 4, 15 August 1991, pages 2136-2151).

1 to 5 are process cross-sectional views illustrating a process step of manufacturing a strained silicon germanium on insulator (SGI) wafer by the smart-cut process described above.

Referring to FIG. 1, a first substrate on which a graded SiGe layer 12 and a buffered SiGe layer 14 are formed is formed on one surface of the silicon substrate 10. The graded silicon germanium layer 12 is formed to a thickness of about 1.0 to 1.5 μm or less, and the buffered silicon germanium layer starts at 0% at a portion where the concentration of germanium is in contact with the surface of the silicon substrate 10. In the part in contact with (14), it is provided in the form of a constant increase to a set value, for example, 10%, 20%, 30%. The buffered silicon germanium layer 14 is formed to a thickness of about 0.4 μm or less, and the germanium concentration therein is provided to be kept constant.

Referring to FIG. 2, hydrogen ions are implanted from the upper surface of the buffered silicon germanium layer 14 to form a hydrogen ion implanted region 15 in the buffered silicon germanium layer 14. The portion of the hydrogen ion implantation region 15 exposed upwardly is in contact with the first buffered silicon germanium layer 14a and the graded silicon germanium layer 12 as the second buffered silicon germanium layer 14b. Separate.

Referring to FIG. 3, after preparing a second substrate having a silicon oxide layer 22 formed on one surface of a silicon substrate 20, the first buffered silicon germanium layer 14b and the first substrate of the first substrate are prepared. The first substrate and the second substrate are bonded to the silicon oxide layer 22 of the second substrate.

Referring to FIG. 4, the hydrogen ion implantation region 15 is cleaved by performing a heat treatment to separate the first substrate and the second substrate. Therefore, the first buffered silicon germanium layer 14a remains on the silicon oxide layer 22 by the separation process.

Referring to FIG. 5, after the cleaved surface of the cleaved first buffered silicon germanium layer 14a is flattened, a strained SGOI wafer including a strained silicon layer is grown by growing a strained silicon layer 16 on the surface thereof. To prepare.

6 to 8 are AFM photographs showing the surface state of the buffered silicon germanium layer 14a according to the concentration of germanium in the conventional strained SGOI wafer of FIG. 5.

Fig. 6 is an AFM photograph showing the surface of the buffered silicon germanium layer 14a having a concentration of 10% germanium, and is relatively good in that no threading dislocations or cross-hatch patterns are formed. It shows the state, but the rms value of surface roughness is about 0.38 nm.

FIG. 7 is an AFM photograph showing the surface of the buffered silicon germanium layer 14a having a concentration of germanium of 20%, and a threading dislocation is formed at a position that looks like a hole, and has a crosshatch pattern having horizontal and vertical patterns. Is formed, which shows an unfavorable state, and the rms value, which is the surface roughness, is about 4.1 nm.

Fig. 8 is an AFM photograph showing the surface of the buffered silicon germanium layer 14a having a concentration of germanium of 30%. The threading dislocation is formed at a position that also looks like a hole, and a cross hatch pattern is formed. The surface roughness rms value is about 4.6 nm.

FIG. 9 is a graph showing the threading dislocation density according to the removal thickness of the buffered silicon germanium layer 14a in a conventional strained SGOI wafer. The removal thickness of the buffered silicon germanium layer 14a represents a thickness removed from the surface of the buffered silicon germanium layer 14a through secco etching at room temperature, and the concentration of germanium in the silicon germanium layer is 10, respectively. The case was carried out for%, 15% and 20%.

Referring to FIG. 9, when the germanium concentration is 10%, almost no threading dislocation occurs in the buffered silicon germanium layer 14a. However, when the germanium concentration is 15% and 20%, the buffered silicon germanium layer is formed. It can be seen that there is a significant amount of threading dislocation within.

As described above, in the conventional strained SGOI wafer, the surface state is very poor because there is a significant density of threading dislocations and cross-hatch patterns in the buffered silicon germanium layer 14a in contact with the strained silicon layer 16. In addition, there is a problem that the strained silicon layer 16 grown by the epitaxial method is also formed very poorly thereon.

Further, the buffered silicon germanium layer 14a and the second substrate of the first substrate at the time of bonding with the second substrate due to the threading dislocations and cross-hatch patterns present in the buffered silicon germanium layer 14a of the conventional first substrate. There is a problem that the bonding with the silicon oxide layer 22 of the substrate is not good.

An object of the present invention is to overcome the problems of the prior art, to provide a method of manufacturing a semiconductor wafer that can easily form a strained silicon layer without using a separate process for growing a strained silicon layer have.

It is another object of the present invention to provide a method of manufacturing a semiconductor wafer comprising a strained silicon layer free of defects such as threading dislocations or cross-hatch patterns.

Another object of the present invention is to provide a semiconductor wafer including a strained silicon layer produced by the manufacturing method of the present invention.

Another object of the present invention is to provide a semiconductor device using the wafer manufactured by the present invention.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a semiconductor wafer including a strained silicon layer, the method including preparing a first substrate including a single crystal silicon layer and a second substrate having an insulating layer formed on one surface thereof. step; Forming a layer of relaxed silicon germanium on the silicon layer of the first substrate; Implanting impurity ions to a predetermined depth from a surface of the first substrate to form an impurity ion implantation region; Coupling the first substrate and the second substrate to contact the relaxed silicon germanium layer formed on the first substrate and the insulating layer formed on the second substrate; Cleaving the impurity ion implantation region in the first substrate by performing a heat treatment; And thinning the silicon layer remaining on the relaxed silicon germanium layer to form a strained silicon layer.

The insulating layer formed on the second substrate may be a silicon oxide layer, and for example, may be formed by a thermal oxidation process.

On the other hand, the thickness of the relaxed silicon germanium layer formed on the first substrate is preferably in the range of 10 nm to 200 nm, the concentration of germanium in the relaxed silicon germanium layer formed on the first substrate is 10 to 40 It is preferable to be in the atomic% range, the temperature of forming the relaxed silicon germanium layer on the first substrate is preferably in the range of 500 to 900 ℃, the relaxed silicon germanium layer is grown by epitaxy method, It may be formed of a strained silicon germanium layer from the surface of the single crystal silicon layer to a predetermined height. In addition, the impurity ions are hydrogen ions, preferably implanted at a low voltage of 30 KeV or less.

In the joining of the first substrate and the second substrate, at least a portion of the first substrate and the second substrate may be contacted at edges of the first substrate and the second substrate, and the contact area may be sequentially changed. Joining while increasing, preferably, the first substrate and the second substrate is in contact with at least a portion of the lower side in the vertical direction, and then pressurized while sequentially increasing the contact area in the upper direction.

On the other hand, in the step of cleaving the impurity ion implantation region, it is preferable that the heat treatment is performed at a low temperature of 400 ° C. or lower in view of thermal insulation to the semiconductor wafer.

The forming of the strained silicon layer may include performing a first hydrogen heat treatment on the surface of the cleaved silicon layer, and wet etching the surface of the cleaved silicon layer, for example, NH 4 OH. , Wet etching using a mixed solution of H 2 O 2 and H 2 0 as an etchant, and after the wet etching step, further includes performing a second hydrogen heat treatment on the surface of the etched silicon layer. You may.

The semiconductor wafer according to the present invention for achieving another object of the present invention may be a semiconductor wafer manufactured by the method for manufacturing a semiconductor wafer comprising a strained silicon layer according to the present invention described above.

In the semiconductor wafer of the present invention, the insulating layer formed on the second substrate is a silicon oxide layer, preferably, the thickness of the relaxed silicon germanium layer formed on the first substrate is in the range of 10 nm to 200 nm. The concentration of germanium in the relaxed silicon germanium layer formed on the first substrate is in the range of 10 to 40 atomic%, the thickness of the strained silicon layer is in the range of 10 to 50 nm, and the surface roughness of the strained silicon layer Is in the range of 0,1 to 0.5 nm. On the other hand, the relaxed silicon germanium layer in contact with the strained silicon layer may be a strained silicon germanium layer to a predetermined thickness from the contact portion.

According to another aspect of the present invention, there is provided a semiconductor device including: a semiconductor wafer including a strained silicon layer manufactured according to the above-described manufacturing method of the present invention; A gate electrode formed on the strained silicon layer of the semiconductor wafer via a gate insulating layer; And a source / drain region formed on the semiconductor wafer corresponding to both sidewalls of the gate electrode.

Preferably, the thickness of the relaxed silicon germanium layer formed on the first substrate is in the range of 10 nm to 200 nm, and the concentration of germanium in the relaxed silicon germanium layer formed on the first substrate is 10 to 40 atoms. %, The thickness of the strained silicon layer is in the range of 10 to 50 nm, the relaxed silicon germanium layer in contact with the strained silicon layer is composed of a strained silicon germanium layer from the contact portion to a constant thickness The source / drain region may extend to the relaxed silicon germanium layer.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments described below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings illustrating embodiments of the present invention, the thicknesses of certain layers or regions are exaggerated for clarity of specification, and like numerals in the drawings refer to like elements. In addition, where a layer is described as being "top" of another layer or substrate, the layer may be present directly on top of the other layer or substrate, with a third layer intervening therebetween.

10 to 14 are process cross-sectional views illustrating a process step of manufacturing a strained SGOI wafer according to an embodiment of the present invention.

Referring to FIG. 10, a first substrate on which the relaxed silicon germanium layer 52 is formed is prepared on the first silicon substrate 50. The first substrate is also called a bonding wafer or a device wafer. The first silicon substrate 50 is a single crystal silicon substrate, and the relaxed silicon germanium layer 52 is grown by an epitaxial growth method. Since the lattice constant of single crystal silicon is 5.431 Å and the lattice constant of silicon germanium is 5.646 Å, the mismatch between silicon and silicon germanium is about 4.1%. Therefore, from the surface of the first silicon substrate 50 to the predetermined critical thickness (critical thickness) due to the mismatch between the silicon and silicon germanium, the strained silicon germanium region, the strain at the thickness above the critical thickness is eliminated and the parallel grating It becomes the relaxed silicon germanium region which is in a state. In the present embodiment, the concentration of germanium is varied in the relaxed silicon germanium layer 52. For example, when the concentration of germanium is about 20%, the strained silicon germanium region is about 30 nm. In this embodiment, the thickness of the relaxed silicon germanium layer 52 is about 200 nm, because it is preferable that the strain be maintained in the relaxed state beyond the strained state. It was set as follows.

Referring to FIG. 11, impurity ions of low voltage, for example, hydrogen ions, are implanted into the first substrate. In the present embodiment, the implantation energy of hydrogen ions was about 25 KeV low voltage energy, and the hydrogen dose was about 6 x 10 16 cm -2 . Accordingly, a hydrogen ion implantation region 54 having a projection specific distance Rp is formed at a predetermined position under the relaxed silicon germanium layer 52, that is, at a predetermined depth from the surface of the first silicon substrate 50. As a boundary, the first silicon substrate 50 is divided into a removal silicon substrate 50a and a remaining residual silicon substrate 50b which are removed from the final wafer.

In FIG. 11, the hydrogen ion implantation region 54 is indicated by a dotted line, but the hydrogen ion implantation region means a region where hydrogen ions are distributed with a constant width. The hydrogen ion implantation energy used in this embodiment is exemplary, and the ΔRp value also increases as the hydrogen ion implantation energy increases, and cleaved when the hydrogen ion implantation region is cleaved by a subsequent heat treatment process as described below. The Rms value indicating the surface roughness of the surface is also increased.

Referring to FIG. 12, a second substrate having at least an insulating layer, for example, a silicon oxide layer 62, is prepared on a surface of the second silicon substrate 60. The second substrate may also be referred to as a reference wafer or a handling wafer. The insulating layer may be formed by various conventional methods, and for example, a thermal oxidation process is performed to form an oxide film, that is, a silicon oxide layer 62 on the surface of the second silicon substrate 60. The silicon oxide layer 62 serves as a buried oxide layer (BOX layer) in the strained SGOI wafer and may be formed to a thickness of about several tens to thousands of micrometers as needed.

Subsequently, the surface of the relaxed silicon germanium layer 52 of the first substrate and the surface of the silicon oxide layer 62 of the second substrate, which will be in contact with each other, are cleaned with a standard cleaning solution such as SCI to remove contaminants on the surfaces. The substrate is bonded to the wafer. In FIG. 12, the first substrate and the second substrate are positioned vertically to be bonded to each other horizontally, but in addition to the horizontal type, the first substrate and the second substrate may be preferably bonded vertically.

The bonding method allows the relaxed silicon germanium layer 52 and at least a portion of the silicon oxide layer 62 to be contacted first, and the contact area thereof is bonded while increasing in one direction (vertically upward in vertical bonding). This is because the lattice is contacted by pressing in one direction in consideration of the fact that both the surface of the silicon germanium layer 52 and the surface of the silicon oxide layer 62 are curved and that the silicon substrates 50 and 60 are elastic bodies. As the surface is flattened, the voids such as moisture, which may be formed therebetween, are pushed out to remove the adhesive, and thus the voids on the adhesive surface are significantly reduced, thereby improving adhesion. In this embodiment, the adhesion is preferably carried out at room temperature, wherein the two wafers may be bonded to each other by hydrogen bonding under hydrophillic conditions.

Referring to FIG. 13, heat treatment is performed at a low temperature to cleavage the hydrogen ion implanted region 54 to remove the removed silicon substrate 50a and transfer the remaining silicon substrate 50b to the second substrate. In this embodiment, the cleavage heat treatment is performed at least about 1 minute at a temperature of about 400 ℃ or less. The cleavage process takes place during the heat treatment, as bubbles in the hydrogen ion implantation region interact to form sufficient blisters and propagate as they flake.

The inventors have found that there is a constant correlation between the heat treatment temperature for cleavage and the Rms value of the cleavage surface. For example, when the heat treatment temperature is 450 ° C., the Rms value is about 3.15 nm, and when the heat treatment temperature is 550 ° C. The value is about 10.9 nm, the Rms value is about 14.5 nm when the heat treatment temperature is 650 ° C, and the Rms value is about 25.0 nm or more when the heat treatment temperature is 750 ° C. It can be seen that the location occurs and the dislocation grows and aggregates with increasing heat treatment temperature. This dislocation on the cleaved surface acts as an inhibitory factor in the subsequent wet etching of the cleaved surface. In consideration of the occurrence of dislocation and the Rms value at the cleaved surface, it is preferable to maintain the heat treatment temperature at a low temperature of 450 ° C. or lower during the cleavage process.

The inventors of the present application actively out-diffusion of hydrogen ions as the heat treatment temperature increases during the cleaving process, and thus, in order to maintain a sufficient amount of hydrogen ion dose to generate sufficient blister and flake phenomenon during the cleaving process, As the heat treatment temperature increases during the process, the hydrogen ion dose must be increased, resulting in higher production cost and lower Rms. However, when the heat treatment is performed at low temperature, out-diffusion of hydrogen ions is low, resulting in a small amount of hydrogen ion dose. It was also found that cleavage could occur sufficiently.

13 and 14, after the hydrogen ion implantation region 54 is cleaved by low temperature heat treatment, the cleaved residual silicon substrate 50b is thinned to a predetermined thickness. As a result of the thinning, as the residual silicon substrate 50b becomes thinner below a predetermined threshold thickness, strain is generated in the residual silicon substrate 50b, so that the strained silicon layer 50c is formed. That is, in the portion of the relaxed silicon germanium layer 52 that is grown on the silicon substrate 50 on the first substrate and in contact with the silicon substrate 50, the silicon polymer that is epitaxially grown due to mismatch of lattice constant between silicon and silicon germanium is deposited. Strain is generated in the nium layer, and the strain generated in this way causes strain on the residual silicon substrate when the thickness of the residual silicon substrate 50b becomes less than the critical thickness, as shown in FIGS. 13 and 14, and thus the strained silicon layer 50c ) Will be formed.

The thinning process may be performed through a chemical mechanical polishing (CMP) process, but in this embodiment, a combination of hydrogen heat treatment and wet etching is performed to simplify the process and maintain a good surface roughness.

That is, as a step of performing the first hydrogen heat treatment on the surface of the cleaved surface, the heat treatment temperature was performed at least 1 minute at 1100 ℃ or more under hydrogen atmosphere. According to the hydrogen heat treatment, the Rms value of the residual silicon substrate 50b is significantly lowered.

Subsequently, after performing the first hydrogen heat treatment, wet etching is performed on the surface of the cleaved residual silicon substrate 50b. The etchant used NH 4 OH: H 2 O 2 : H 2 0 = 0.5: 1: 5 etching solution, the etching temperature was carried out in the range of 65 ~ 100 ℃, the etching time and the thickness of the etching is the final device formation desired The thickness was set in consideration of the thickness of the strained silicon layer 50c to be a region. The reason why the etchant of the present invention is selected is because it is very advantageous to form a very thin strained silicon layer 50c because the etching rate is low and the uniformity of the etching thickness after etching is excellent.

Subsequently, the surface of the wet etched strained silicon layer 50c (herein, the residual silicon substrate and the strained silicon layer is used in combination according to the thickness of the silicon layer) is subjected to a second hydrogen heat treatment process. The roughness is very good. The secondary heat treatment process is performed in the same manner as the primary heat treatment process described above.

15 to 18 illustrate SIMS profiles of germanium for the relaxed silicon germanium layer 52 grown on the silicon substrate 50 in FIG. 13 during the fabrication of the strained SGOI wafer according to the embodiment of the present invention. Indicates.

FIG. 15 shows a case where the concentration of germanium is 8% (hereinafter at%), FIG. 16 shows 10%, FIG. 17 shows 14%, and FIG. 18 shows 18%. It can be seen from each graph that the concentration of germanium is constant depending on the thickness.

19 to 22 are micrographs showing the surface state of a relaxed silicon germanium layer 52 in a strained SGOI wafer according to an embodiment of the present invention. 19 is a case where the concentration of germanium is 8%, FIG. 20 is a case where the concentration of germanium is 10%, FIG. 21 is a case where the concentration of germanium is 14%, and FIG. 22 is the concentration of germanium 18% of the case is shown, and in all cases the surface condition is very good. That is, it can be seen that in the conventional strained SGOI wafer shown in FIGS. 7 and 8, the threading dislocations exhibited in the buffered silicon layer do not occur, and the cross-hatch pattern does not occur.

23 to 26 are AFM photographs showing a surface state of a relaxed silicon germanium layer in a strained SGOI wafer according to an embodiment of the present invention. Fig. 23 shows the rms value of surface roughness of 0.15 nm when the concentration of germanium is 8%, and Fig. 24 shows the rms value of 0.19 nm of the surface roughness when the concentration of germanium is 10%. Denotes a case where the concentration of germanium is 14%, and the rms value of surface roughness is 0.21 nm, and FIG. 26 shows an rms value of surface roughness of 0.455 nm when the concentration of germanium is 18%. That is, it can be seen from FIGS. 6 to 8 that the surface roughness is very good in all cases of the present invention compared to the surface roughness in the conventional strained SGOI wafer.

FIG. 27 is a view for explaining a mechanism in which the strained silicon layer 50c is formed on the relaxed silicon germanium layer 52 in the strained SGOI wafer (see FIG. 14) according to an embodiment of the present invention. In Fig. 27, (a) shows a silicon lattice and lattice constant, the lattice constant of silicon is 5.431Å, (c) shows a lattice constant and lattice constant of germanium, and its lattice constant is 5.646Å, and (b) The lattice containing germanium and its lattice constant in the silicon lattice are shown, and the mismatch between silicon and silicon germanium is about 4.1%. (d) shows that since the silicon layer formed on the silicon germanium layer is smaller than the lattice constant of the silicon germanium layer, tensile strain occurs in both the X and Y directions at the junction between the silicon germanium layer and the silicon layer. That is, it will be explained in FIG. 14 that the strained silicon layer 50c in which strain is generated from the surface of the relaxed silicon germanium layer 52 to a predetermined critical thickness can be formed.

FIG. 28 is a graph cited for determining a germanium concentration and a critical thickness relationship for forming a strained silicon layer 50c in a strained SGOI wafer according to an embodiment of the present invention. This graph as the critical thickness for forming a strained silicon layer on a silicon germanium layer at different temperatures, the above-mentioned article by Mr. DC Houghton "Strain relaxaion kinetics in Si 1 - x Ge x / Si heterostructures" (J. Appl. Phys. Vol. 70, No. 4, 15 August 1991, pages 2136-2151. In each graph (theoretical value or experimental value) of FIG. 13, the upper right corner shows a relaxed state and the lower left corner shows a strained state. Therefore, in order to form the strained silicon layer 50c on the relaxed silicon germanium layer 52, the thickness of the silicon layer must be kept below the critical thickness depending on the concentration of germanium (or considering the growth temperature) in the silicon germanium layer. do. .

29 is a photograph showing a cross section of a strained SGOI wafer manufactured according to one embodiment of the present invention. That is, the silicon oxide layer 62 is formed at about 200 nm on the second silicon substrate 60 and the relaxed silicon germanium layer 52 is formed at about 110 nm on the silicon oxide layer 62. The strained silicon layer 50c is formed on the relaxed silicon germanium layer 52 to a thickness of about 50 nm. It can be seen from FIG. 29 that defects such as threading dislocations do not occur in the relaxed silicon germanium layer 52, and a good strained silicon layer is formed thereon.

30 is a cross-sectional view illustrating an example of a MOS transistor as a semiconductor device to which a strained SGOI wafer according to an embodiment of the present invention may be applied. That is, after forming the isolation region 76, for example, a trench isolation region for the strained SGOI wafer of the present invention, a gate oxide film 70 is formed, a gate electrode material is formed and then patterned to form a gate electrode 72. ) And impurity ions are implanted into the gate electrode pattern using an ion implantation mask to form source / drain regions 74. The depth of the source / drain regions 74 may be deeply implanted to reach the surface of the silicon oxide layer 62, as designed. Fig. 30 shows a basic MOS transistor which can be manufactured using the strained SGOI of the present invention, but the present invention can of course be used for the manufacture of various semiconductor devices.

Although preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications may be made by those skilled in the art within the scope of the technical idea of the appended claims.

According to the present invention, since the strained silicon layer can be formed by performing only a thinning process without performing a process of separately growing the strained silicon layer on the silicon germanium layer, the process can be greatly simplified.

According to the present invention, a strained SGOI wafer having excellent characteristics can be manufactured because the quality and surface state of the relaxed silicon germanium layer are very good.

Claims (28)

  1. Preparing a first substrate including a single crystal silicon layer and a second substrate having an insulating layer formed on one surface thereof;
    Forming a layer of relaxed silicon germanium on the silicon layer of the first substrate;
    Implanting impurity ions to a predetermined depth from a surface of the first substrate to form an impurity ion implantation region;
    Coupling the first substrate and the second substrate to contact the relaxed silicon germanium layer formed on the first substrate and the insulating layer formed on the second substrate;
    Cleaving the impurity ion implantation region in the first substrate by performing a heat treatment; And
    Thinning the silicon layer remaining on the relaxed silicon germanium layer to form a strained silicon layer.
  2. The method of claim 1, wherein the insulating layer formed on the second substrate is a silicon oxide layer.
  3. The method of claim 1, wherein a thickness of the relaxed silicon germanium layer formed on the first substrate is in a range of about 10 nm to about 200 nm.
  4. The method of claim 1, wherein the concentration of germanium in the relaxed silicon germanium layer formed on the first substrate is in a range of 10 to 40 atomic%.
  5. The method of claim 1, wherein the temperature of forming the relaxed silicon germanium layer on the first substrate is in a range of 500 to 900 ° C. 3.
  6. 2. The method of claim 1, wherein the impurity ions are hydrogen ions and implanted at a low voltage of 30 KeV or less.
  7. The method of claim 1, wherein the forming of the relaxed silicon germanium layer is performed by an epitaxy method.
  8. The method of claim 1, wherein the joining of the first substrate and the second substrate is performed after contacting at least a portion of the first substrate and the second substrate at an edge of the first substrate and the second substrate. Method of manufacturing a semiconductor wafer comprising a strained silicon layer characterized in that the bonding while increasing the contact area.
  9. The method of claim 8, wherein the bonding of the first substrate and the second substrate comprises contacting the first substrate and the second substrate with at least a portion of the lower side in the vertical direction, and then sequentially increasing the contact area in the upward direction. A method of manufacturing a semiconductor wafer comprising a strained silicon layer characterized in that the bonding by pressing while increasing.
  10. The method of claim 1, wherein in the cleaving the impurity ion implantation region, the heat treatment is performed at a low temperature of 400 ° C. or less.
  11. The method of claim 1, wherein the forming of the strained silicon layer comprises:
    A method of manufacturing a semiconductor wafer comprising a strained silicon layer, characterized in that it comprises the step of primary hydrogen heat treatment of the surface of the cleaved silicon layer.
  12. The method of claim 1, wherein the forming of the strained silicon layer comprises:
    Wet etching the surface of the cleaved silicon layer comprising the step of manufacturing a semiconductor wafer comprising a strained silicon layer.
  13. The method of claim 12, wherein forming the strained silicon layer comprises:
    After the wet etching step, the method of manufacturing a semiconductor wafer comprising a strained silicon layer further comprising the step of secondary hydrogen heat treatment of the surface of the etched silicon layer.
  14. The semiconductor wafer of claim 12, wherein the wet etching is performed by using a mixed solution of NH 4 OH, H 2 O 2, and H 2 0 as an etchant. Way.
  15. The method of claim 1, wherein a thickness of the strained silicon layer is in a range of 10 to 50 nm.
  16. A semiconductor wafer comprising a strained silicon layer prepared according to the method of claim 1.
  17. The semiconductor wafer of claim 16, wherein the insulating layer formed on the second substrate is a silicon oxide layer.
  18. The semiconductor wafer of claim 16, wherein a thickness of the relaxed silicon germanium layer formed on the first substrate is in a range of 10 nm to 200 nm.
  19. 17. The semiconductor wafer of claim 16, wherein the concentration of germanium in the relaxed silicon germanium layer formed on the first substrate is in the range of 10 to 40 atomic percent.
  20. The semiconductor wafer of claim 16, wherein the strained silicon layer has a thickness in the range of 10 to 50 nm.
  21. 17. The semiconductor wafer of claim 16, wherein the surface roughness of the strained silicon layer is in the range of 0.1 to 0.5 nm.
  22. 17. The semiconductor wafer of claim 16, wherein said relaxed silicon germanium layer in contact with said strained silicon layer is a strained silicon germanium layer from a contact portion thereof to a predetermined thickness.
  23. A semiconductor wafer comprising a strained silicon layer prepared according to the method of claim 1;
    A gate electrode formed on the strained silicon layer of the semiconductor wafer via a gate insulating layer;
    And a source / drain region formed on the semiconductor wafer corresponding to both sidewalls of the gate electrode.
  24. 24. The semiconductor device of claim 23, wherein the thickness of the relaxed silicon germanium layer formed on the first substrate is in the range of 10 nm to 200 nm.
  25. 24. The semiconductor device of claim 23, wherein the concentration of germanium in the relaxed silicon germanium layer formed on the first substrate is in the range of 10 to 40 atomic percent.
  26. 24. The semiconductor device of claim 23, wherein the strained silicon layer has a thickness in the range of 10 to 50 nm.
  27. 24. The semiconductor device according to claim 23, wherein said relaxed silicon germanium layer in contact with said strained silicon layer is a strained silicon germanium layer from its contact portion to a predetermined thickness.
  28. 24. The semiconductor device of claim 23, wherein the source / drain region extends to the relaxed silicon germanium layer.
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Publication number Priority date Publication date Assignee Title
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5882987A (en) 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
KR20020011318A (en) * 2000-08-01 2002-02-08 티엔-흐시 리 Manufacturing method of a thin film on a substrate
KR20020079498A (en) * 2001-04-06 2002-10-19 캐논 가부시끼가이샤 Semiconductor member manufacturing method and semiconductor device manufacturing method
KR20050060982A (en) * 2003-12-17 2005-06-22 주식회사 실트론 A method of fabricating soi wafer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5882987A (en) 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
KR20020011318A (en) * 2000-08-01 2002-02-08 티엔-흐시 리 Manufacturing method of a thin film on a substrate
KR20020079498A (en) * 2001-04-06 2002-10-19 캐논 가부시끼가이샤 Semiconductor member manufacturing method and semiconductor device manufacturing method
KR20050060982A (en) * 2003-12-17 2005-06-22 주식회사 실트론 A method of fabricating soi wafer

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