JP2001320033A - Semiconductor member and method for manufacturing the same and semiconductor device using the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form semiconductor regions between plural insulating regions, in an SOI substrate formed by a sticking method. SOLUTION: This method is provided with a process for preparing a first member having the plural insulating regions 17 and the plural semiconductor regions 12 formed between the plural insulating regions, a process for sticking the first member to a second member 14 as semiconductor base material in such a manner that a structure body in which the plural insulating regions and the plural semiconductor regions are positioned inside is obtained, and a process for transferring the plural insulating regions and the plural semiconductor regions to the second member 14 side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor member, a semiconductor member and a semiconductor device using the same, and more particularly, to a method for manufacturing an SOI substrate having a semiconductor layer on a semiconductor surface via an insulating layer, and a method for manufacturing the same. Semiconductor members used,
The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art SOI (Semiconductor On Insulator)
The substrate has a structure in which an underlying semiconductor substrate and an active layer of a semiconductor such as Si for forming an element are separated via an insulating layer such as an oxide film. FIG. 10 is a sectional view showing the structure of the SOI substrate. In FIG. 10, 101 is a semiconductor substrate, 10
Reference numeral 2 denotes an insulating layer, and 103 denotes a semiconductor active layer.

FIG. 11 is a sectional view showing a case where a MOS transistor is formed on the SOI substrate. Compared to those formed on the bulk substrate, the bottom of the source / drain (S, D) of the MOS transistor 104 has an insulating layer 10 such as an oxide film.
2, the parasitic capacitance such as the diffusion layer capacitance can be reduced, and the semiconductor device can be operated at high speed and driven with low power consumption. Further, since each element is separated by the insulating layer 102, there is an effect of reducing noise.

[0004]

However, due to the presence of the insulating layer, excess carriers generated from the high electric field near the drain lose their escape fields and accumulate at the bottom of the MOS channel, and the "kink" peculiar to the MOS transistor on the SOI substrate is lost. This may cause a "phenomenon" or "parasitic bipolar effect" and degrade device characteristics. In addition, ESD (Electrosta
tic Discharge)
Due to the presence of the insulating layer, excess charges due to the surge cannot be released to the base substrate side unlike the bulk substrate, and it becomes difficult to form an effective protection circuit. As a result, there has been a problem that the protection circuit of the element formed on the SOI substrate has a much larger area than the bulk substrate, resulting in a layout configuration that is not desirable for miniaturization.

[0005]

SUMMARY OF THE INVENTION A method of manufacturing a semiconductor member according to the present invention comprises the steps of providing a first member having a plurality of insulating regions and a plurality of semiconductor regions provided between the plurality of insulating regions. Laminating the first member and a second member that is a semiconductor substrate so that a multilayer structure in which the plurality of insulating regions and the plurality of semiconductor regions are located inside is obtained; Transferring the plurality of insulating regions and the plurality of semiconductor regions to the second member side.

Further, according to the method of manufacturing a semiconductor member of the present invention, a plurality of insulating regions and a plurality of semiconductor regions provided between the plurality of insulating regions are formed on the semiconductor substrate or on the semiconductor layer of the substrate having the semiconductor layer. A step of preparing a first member having: a first member and a second member that is a semiconductor substrate, a multilayer structure in which the plurality of insulating regions and the plurality of semiconductor regions are located inside; And a step of transferring the plurality of insulating regions, the plurality of semiconductor regions, and a part of the semiconductor substrate or the semiconductor layer to the second member side. .

[0007] A method of manufacturing a semiconductor member according to the present invention includes a step of preparing a first member having a plurality of insulating regions and a plurality of semiconductor regions provided between the plurality of insulating regions; Providing a second member;
The first member and the second member so that a multilayer structure in which the plurality of insulating regions and the plurality of semiconductor regions of the member are located inside the semiconductor layer of the second member is obtained. A step of bonding the member to a member and a step of transferring the semiconductor layer to the first member.

The method of manufacturing a semiconductor member according to the present invention further comprises the steps of: preparing a first member having a plurality of insulating regions and a plurality of semiconductor regions provided between the plurality of insulating regions; To obtain a multilayer structure in which the plurality of insulating regions and the plurality of semiconductor regions of the member are located inside,
A step of bonding the first member to a second member which is a semiconductor substrate; and a step of transferring a part of the semiconductor substrate of the second member to the first member. .

The semiconductor member of the present invention is manufactured by the manufacturing method of the present invention.

A semiconductor device according to the present invention uses the semiconductor member according to the present invention, wherein at least a part of a semiconductor circuit is provided on a part of a semiconductor layer or a semiconductor base on a semiconductor region. .

[0011]

According to the present invention, as shown in FIG. 9, a semiconductor island layer 9 for connecting an upper semiconductor layer 94 and an underlying semiconductor layer (or semiconductor substrate) 91 between insulating regions 92 such as a buried oxide film.
3 is provided.

As a result, when forming a MOS transistor and a protection circuit against ESD as shown in FIG.
The element can be formed such that the semiconductor island region is located immediately below the MOS channel region or directly below the protection circuit.

As a result, surplus carriers generated by the high electric field at the drain are collected at the bottom of the channel of the MOS, and can escape to the base substrate 81 through the semiconductor eyelet. For this reason, it is possible to suppress the deterioration of the element peculiar to the MOS transistor on the SOI, such as the generation of the kink current and the parasitic bipolar effect caused by the accumulation of the carrier at the bottom of the channel.

[0014] In addition, a protection diode for ESD measures can be formed vertically in the same manner as for a bulk substrate. Excessive charge generated by static electricity
The light can be diffused to the underlying substrate through the semiconductor ilide region between the buried oxide films 82. Therefore, the bulk protection circuit can be used as it is.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view showing steps of a method for manufacturing an SOI substrate according to the present invention.

First, as shown in FIG. 1A, a semiconductor such as a Si layer corresponding to an active layer of SOI is formed on an isolation layer 15 of an undersubstrate 13 in order to produce one substrate before bonding two substrates. A layer 16 is provided, and a silicon oxide film 17 corresponding to an insulating film is stacked thereon.

The Si layer, which is the active layer of the SOI substrate, may be Si formed by epitaxial growth, or may be a part of a Si wafer formed by the CZ method or the like. In addition, the present invention is not limited to the case of the bonding type using a separation layer such as porous silicon, but also bonding the wafers via an insulating layer such as an oxide film, and bonding without using a separation layer such as porous silicon. In some cases, it may be a combination type.

There are roughly two methods of forming a member having a semiconductor layer on a semiconductor substrate via a separation layer. One is to form a porous layer on a semiconductor substrate and then form a non-porous layer on the surface thereof. It is a method of forming. The non-porous layer can be formed by a method of epitaxial growth on the porous layer or a method of heat-treating the surface of the porous layer in an atmosphere containing hydrogen. The other is to implant a different element such as hydrogen ion, rare gas ion or nitrogen ion into the semiconductor substrate to form a layer containing microscopic voids or a layer containing potential microscopic voids that can generate microscopic voids by subsequent heat treatment. Is formed at a position at a predetermined depth from the surface of the substrate.

Next, as shown in FIG. 1B, dry etching is performed using a photomask 11, and FIG.
As shown in FIG. 5, a desired region 18 in which the semiconductor surface free of SiO ₂ is exposed is formed.

Next, as shown in FIG. 1D, after the photomask 11 is removed, a desired region 1 where the semiconductor surface is exposed is formed.
8, selective epitaxial is performed to form an epitaxial Si layer 12 as shown in FIG. For this selective epitaxial growth, selectivity is obtained by using, for example, a silane-based gas in a CVD method and setting the growth temperature to a high temperature of 1000 ° C. or higher. Specifically, in the CVD method, H ₂ gas 150 (l / mi) is applied at 1100 ° C. and normal pressure.
n), HCl gas (400 sccm), trichlorosilane SiHCl (liquid) 36.2 (g / min), 30
Laminate for seconds. Or, by gas source molecular beam growth method,
There is a method in which disilane (Si ₂ H ₆ ) or SiH ₄ is used as a source gas to grow at a molecular beam region vacuum. Furthermore, selective growth can also be performed using a SiH ₂ Cl ₂ / H ₂ system.

Thus, the Si region 12 can be selectively provided in a layer corresponding to the oxide film (insulating layer) of the SOI substrate.

Next, since the Si region 12 formed by such selective epitaxial growth grows in a pyramid shape, immediately after generation, as shown in FIG. 1E, a facet (Facet) having poor surface flatness with the SiO ₂ layer. Appears. For this reason, before bonding with another substrate, selective polishing is performed, and FIG.
It is required to improve the surface flatness as shown in FIG.

Various methods have been already proposed for selective polishing, such as polishing using an oxide film as a stopper, using a "nitride film" having a higher strength than an oxide film as a stopper, or using CMP (chemical mechanical polishing). And so on. Using these methods, the flatness of the surface of the oxide film including the Si region 12, which is the surface of the substrate 13, is ensured. Thus, a silicon oxide film 17 serving as a plurality of insulating regions and a Si region 12 serving as a plurality of semiconductor regions are formed.

Thereafter, as shown in FIG. 1 (g), the flattened surface of the substrate 13 is bonded to the substrate surface of another substrate 14 such as a wafer to form a multilayer structure. Is separated by a separation layer, so that the semiconductor layer 16 and the silicon oxide film 17 are transferred to the substrate 14 side, as shown in FIG.

The separation method using the separation layer is roughly classified into two types. One is a method of generating energy for separation inside the multilayer structure by heating the multilayer structure from the outside or irradiating light to the multilayer structure to absorb light. Specifically, a layer including minute voids or a layer including potential minute voids formed by implanting hydrogen ions, rare gas ions, nitrogen ions, or the like into a position of a predetermined depth in the first wafer has thermal energy As a result, the density decreases while the minute voids increase. This causes a peeling phenomenon of the multilayer structure in the layer.
This is a method for generating energy for separation inside the multilayer structure. Alternatively, a method of oxidizing the separation layer and / or its vicinity from the side surface by heat treatment and separating the separation layer by using a stress due to oxide film growth may be used.

The other is a method in which energy for separation is directly applied to the multilayer structure from the outside. In particular,
A method of inserting and removing a wedge on a side surface of a multilayer structure, a method of spraying a fluid composed of a liquid and / or a gas on the side surface of the multilayer structure, and a method of applying opposite tensions to the front and back surfaces of the multilayer structure In addition, a method of peeling, a method of applying a pressing force in opposite directions to the front and back surfaces of the multilayer structure to break and separate the separation layer, and applying a shear force to the side surface of the multilayer structure to break the separation layer. There are a method of peeling, a method of slicing using an inner peripheral blade and a wire saw, and a method of breaking the separation layer by applying ultrasonic vibration. The liquid or gas to be sprayed is not particularly limited, and examples thereof include water and nitrogen gas. Of course, the above-described separation methods may be used in combination.

Further, when a MOS transistor or a protection circuit is manufactured on the SOI substrate thus manufactured, alignment of the mask is performed by, for example, irradiating infrared light from below the substrate, and irradiating the infrared light from above the substrate with an IR camera. By monitoring, the distribution of SiO ₂ and Si in the oxide film can be identified. As a result, the Si region 12 immediately below the channel region of the MOS transistor and the ESD protection diode is formed.
Can be located.

In this embodiment, an example is shown in which the separation layer 15, the semiconductor layer 16, and the semiconductor region 12 are formed on one substrate, and the semiconductor layer 16 and the semiconductor region 12 are transferred to the other substrate. As shown in (1), a semiconductor region can be formed on one substrate, a separation layer and a semiconductor layer can be formed on the other substrate, and the semiconductor layer can be transferred to the one substrate.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 In this example, after a porous layer was formed on a first single-crystal semiconductor substrate, a non-porous layer was formed on the surface thereof and bonded to a second single-crystal semiconductor substrate. This is an example in which the present invention is implemented using a method in which a non-porous layer is transferred to a second single-crystal semiconductor substrate by separating a porous layer with a separation layer later.

Prior to the description of the present embodiment, the above-mentioned method used in the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 2A, a porous Si layer 21 is formed on a first bulk wafer 20, and an epitaxial Si layer 22 serving as an active layer is grown thereon.
Further, as shown in FIG. 2B, after the silicon oxide film 24 is formed by thermal oxidation, the silicon oxide film 24 is bonded to the handle wafer 23 shown in FIG. 2C to form the multilayer structure shown in FIG. 2D. Make it. Further, separation is performed in the porous layer or at the interface between the porous layer and the wafer 20 and at the interface between the porous layer and the semiconductor layer 22.
At this time, a silicon oxide film 24 is formed on the handle wafer 23 side.
And the epitaxial Si layer 22 are transferred. FIG. 2 (e)
As shown in FIG. 2, when a part of the porous layer separated on the epitaxial Si layer 22 remains, it is removed by grinding, etching, or the like to obtain the SOI substrate shown in FIG.

The porous Si layer is subjected to an oxidation treatment before the growth of the epitaxial layer, and is further subjected to a hydrogen treatment to remove the oxide film on the surface of the layer, thereby preventing the porous Si layer from being altered by the heat treatment temperature. The bonding annealing temperature can be increased until a sufficient bonding strength is obtained, and separation at the bonding surface can be prevented.

For selectively etching the porous Si with respect to the epitaxial Si layer, an HF + H ₂ O ₂ liquid can be used.

The above method is described in, for example,
As described in detail in Japanese Patent No. 1338, here, as an example, a method for obtaining a semiconductor substrate by making the P-type substrate 20 porous and epitaxially growing a single crystal layer is described.
This will be described in more detail below with reference to FIGS.

First, as shown in FIG.
A single crystal substrate 20 is prepared and a part thereof is made porous to form a porous Si layer 21.

Next, as shown in FIG. 2B, a thin film single crystal layer 22 is formed by epitaxial growth on the surface of the porous substrate by the aforementioned crystal growth method capable of low temperature growth. The P-type Si single crystal substrate 20 is made porous by an anodizing method using an HF solution. This porous Si layer 2
1 is compared with the density of single crystal Si of 2.33 g / cm ³ ,
The density can be changed in the range of 1.1 to 0.6 g / cm ³ by changing the HF solution concentration to 50 to 20%. Further, an oxide layer 24 is formed on the surface.

Next, as shown in FIG. 2C, another Si substrate 23 is prepared, and a single crystal Si layer 22 is formed on the Si substrate 23 and the porous Si substrate 21 shown in FIG. ,
FIG. 2D shows the Si substrate on which the oxide layer 24 is formed.
To form a multilayer structure.

Thereafter, as shown in FIG. 2E, the entire porous Si layer 21 is removed by etching or the porous Si layer 2 is removed.
After dividing by 1, the remaining porous Si layer 21 is removed by etching, and the thinned single-crystal silicon layer 22 is left on the SiO ₂ layer 24 to form. Here, since the porous semiconductor layer is etched away without performing the oxidation treatment on the porous semiconductor layer, oxidation expansion of the porous semiconductor layer can be prevented, and the influence of distortion on the epitaxially grown single crystal layer can be prevented. According to this method, a single-crystal Si layer 22 having a crystallinity equivalent to that of a silicon wafer is formed into a flat and uniform thin film on a silicon oxide layer 24 which is an insulator, and is formed over a large area over the entire wafer. Is done. The semiconductor substrate thus obtained can be suitably used also in the production of an insulated and separated electronic element.

The thickness of the non-porous semiconductor crystal layer formed on the porous semiconductor substrate is preferably 50 μm or less, more preferably 20 μm or less, in order to form the semiconductor single crystal layer in a thin film semiconductor device. desirable.

The non-porous semiconductor single crystal and the substrate having the surface of the insulating material are attached to each other in an atmosphere of nitrogen, an inert gas or a mixture of these, or in an atmosphere containing an inert gas or nitrogen. It is preferable that the heat treatment be performed.

Examples of etchants for selectively etching a porous semiconductor substrate while leaving a non-porous semiconductor single crystal layer bonded on a substrate having an insulating material surface include, for example, aqueous sodium hydroxide and potassium hydroxide. An etchant such as an aqueous solution, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid may be used.

As described above, the method used in the present embodiment for transferring the non-porous layer to another substrate by separating the porous layer with the separation layer is used. A method for manufacturing a substrate will be described with reference to FIGS.

First, as shown in FIG. 1A, a porous Si layer 15 is formed on a first bulk wafer 13 and an epitaxial Si layer 16 serving as an active layer is grown thereon. The process up to the point where the silicon oxide film 17 is formed is performed in the same manner as the method described with reference to FIG.

Next, in the same manner as used in the above-described embodiment, SiO ₂ uniformly formed on one surface is
Dry etching is performed using the photomask 11 as shown in FIG. It is desirable that the size of the photomask is at most equivalent to the channel region of the MOS transistor and the protection diode. As shown in FIG. 1C, a desired region 18 free of SiO ₂ is formed by dry etching, the photomask 11 is removed as shown in FIG. 1D, and selective epitaxial growth is performed on the region 18. Then, the epitaxial S as shown in FIG.
An i region 12 is formed. Then, after selective polishing is performed as shown in FIG. 1 (f) to ensure surface flatness, as shown in FIG. 1 (g), the wafer is bonded to a handle wafer 14 as a second wafer.

Subsequently, as shown in FIG. 1 (h), a porous Si
The SOI structure can be obtained by grinding the Si bonded to the Si and removing the porous Si layer by etching.

For the alignment, the method described in the embodiment can be used, but the method described below can also be used.

At the stage of manufacturing an SOI substrate, first, FIG.
As shown in (a), a porous layer 32 is formed on a p-substrate 31. Next, as shown in FIG. 3B, the porous layer 3 is formed in order to form an uneven area serving as a reference for mask alignment.
2, a concave region 33 is provided.

Next, as shown in FIG.
2 is epitaxially grown on the Si layer 2, and an oxide film 35 is formed thereon as shown in FIG. At this time, since irregularities corresponding to the porous layer appear on the oxide film layer 35 on the surface, CMP (chemical mechanical polishing) is performed.
The surface flatness is secured as shown in FIG.

Then, as shown in FIG. 3 (f), after the flattened oxide film surface and the handle wafer 36 are bonded together, as shown in FIG. 3 (g), they are separated by the porous layer 32.
Further, when a part of the porous layer 32 remaining on the substrate is etched, a concave / convex region 33 serving as a reference for mask alignment remains in the epitaxial Si on the surface. After the unnecessary Si region 31 is ground, the porous layer 32 may be removed by etching. The following steps are performed in the uneven region 3
By performing the alignment with reference to 3, the device can be built at a desired position.

On the other hand, conventionally, for example, there has been a method in which a buried oxide film is formed intermittently by using a SIMOX wafer and implanting high energy of oxygen using the gate electrode as a mask. In this case, the Si active layer can be made of epitaxial Si in this embodiment, as opposed to the Si active layer made of CZ. In epitaxial Si, a high-quality Si active layer capable of extremely lowering the concentrations of impurity oxygen and carbon that cause crystal defects can be obtained, and the characteristics of a semiconductor device formed therein can be improved.

[Embodiment 2] In Embodiment 1, a buried oxide film having an island-shaped semiconductor region therebetween and an active layer for forming an SOI device are formed on a first single crystal base before bonding. Although this is bonded to the second single crystal substrate, a buried oxide film having an island-shaped semiconductor region between the first single crystal substrate and the second single crystal substrate
An active layer for forming the device I may be formed, and the first single crystal substrate and the second single crystal substrate may be bonded to each other.

The manufacturing method according to the present embodiment will be described with reference to FIG.

FIG. 4A shows the first single crystal substrate before bonding. After an oxide film 42 is formed on the bulk wafer 41, dry etching is performed using a photomask 43 (FIG. 4).
(B), (c)), and the Si active layer 43 is generated by selective epitaxial growth in the same manner as in the first embodiment (FIG. 4 (d)).
The surface is polished (FIG. 4E).

On the other hand, as a second single-crystal substrate, a porous Si layer 45 is formed on a bulk wafer 44, and a Si active layer 46 is formed thereon by epitaxial growth.

Next, the first single crystal substrate and the second single crystal substrate are bonded together (FIGS. 4 (f) and 4 (g)). After removing the quality Si by etching or the like, or grinding and removing the bulk wafer 44, the porous Si layer 45 is removed to obtain the desired SOI structure shown in FIG. 4H.

[Embodiment 3] In this embodiment, a separation layer is formed in a first single-crystal semiconductor substrate, bonded to a second single-crystal semiconductor substrate, and then separated by a separation layer. This is an example in which the present invention is implemented by using a method of transferring a part of the first single crystal semiconductor substrate to the second single crystal semiconductor substrate. The manufacturing method according to the present embodiment will be described with reference to FIG.

As shown in FIG. 5A, in the first wafer 51 before bonding, up to the step of forming a silicon oxide film 52 corresponding to a buried oxide film on the surface, an ordinary SOI substrate generation method is used. Is the same as In the present embodiment, a process for cutting a substrate region that becomes unnecessary after bonding is performed. For example, the area 5 you want to cut
A hydrogen injection 53 is performed on 3. By injecting hydrogen into the semiconductor substrate, a layer including microscopic voids or a layer including potential microscopic voids which can generate microscopic voids by a subsequent heat treatment can be formed at a position at a predetermined depth from the surface of the semiconductor substrate.

Next, in the same manner as used in the embodiment,
As shown in FIGS. 5B and 5C, the SiO ₂ layer 52 uniformly formed on one surface is etched using a photomask 54 to form a desired region where no SiO ₂ exists. After the photoresist 54 is removed as shown in FIG.
An epitaxial Si region 54 as shown in FIG. Then, as shown in FIG. 5F, selective polishing is performed to secure the surface flatness, and then the wafer is bonded to the second wafer 55 as shown in FIG. 5G.

After the bonding, as shown in FIG. 5H, a process for removing an unnecessary substrate region is performed on the region 53 to which a predetermined process has been performed, and the unnecessary region is cut. I do. For example, if a hydrogen injection layer is annealed at an appropriate temperature, it will be cut therefrom.

In this embodiment, an active layer for forming an SOI device is provided on the first single crystal base before bonding.
A buried oxide film layer is formed, but in addition to this, only a buried oxide film layer is formed on the first single crystal base, and an active layer for forming an SOI device is formed on the second single crystal base. After forming an island-shaped silicon layer in the buried oxide film by a method according to the present embodiment, the first single-crystal substrate and the second
May be bonded to the single crystal substrate.

For the mask alignment when a device is formed on the SOI substrate thus manufactured, the method described in the embodiment can be used, but the method described below can also be used.

This method will be described with reference to FIG.

As shown in FIG. 6A, first, an oxide film 62 is laminated on a Si wafer 61, and then an SiO ₂ oxide film 62 is formed.
Is provided with a concave region 63, and hydrogen is implanted from above to form a hydrogen implanted region 65 as shown in FIG. 6B.

Then, after passing through a step for obtaining a predetermined SOI structure, the bonding surface is flattened and bonded to the second substrate 64 as shown in FIG. Is performed, the alignment reference of the protrusion remains on the surface of the Si active layer as shown in FIG. 6D.

[Embodiment 4] In Embodiments 1, 2, and 3,
When performing selective epitaxial growth, facets (F
As a result, the facet must be selectively polished, which complicates the process steps. In this embodiment, a method for implementing the present invention without using selective epitaxial growth will be described.

FIG. 7 is a diagram showing the manufacturing process of this embodiment.

As shown in FIG. 7A, the first wafer 71
After the formation of the porous Si layer 72, the Si layer 73 is epitaxially grown as shown in FIG. At this time, the thickness of the epitaxial Si layer 73 is set to (SOI active layer) + (buried oxide film layer).

As an example, specifically, in a CVD method, H ₂ gas is 150 l / min at 1100 ° C. and normal pressure.
HCL 400sccm, trichlorosilane SiHCl
(Liquid) Lamination at 36.2 g / min for 40 seconds.

Next, a nitride film 74 is formed only on a desired region as shown in FIG. 7C, and is thermally oxidized. Alternatively, oxygen is implanted from above using the nitride film 74 as a mask.

As a result, as shown in FIG. 7D, a fragmentary SiO ₂ island 75 is formed inside the epitaxial Si layer 73. Then, as shown in FIG. 7E, the surface is flattened by CMP.

Thereafter, as shown in FIG. 7F, the substrate is bonded to the second wafer 76, and then, as in the first embodiment,
As shown in FIG. 7G, the substrate is divided by the porous Si layer 72, and FIG.
As shown in FIG. 7F, the remaining porous Si layer 72 is removed by etching to obtain the structure shown in FIG. The structure shown in FIG. 7H can also be obtained by grinding the first wafer 71 bonded to the porous Si layer 72 and removing the porous Si layer 72 by etching.

[Example 5] An SOI substrate having a thickness of 2000 mm of a Si active layer and a thickness of 2000 mm of a buried oxide film layer was manufactured by the method described in the embodiment. Then, using this SOI substrate, as shown in FIG. 8, a MOS transistor is formed just above the Si island between the buried oxide films 82 so that the channel region is located. A protection diode for preventing static electricity connected to the gate of the MOS transistor was manufactured.

Thus, the drain current-drain voltage characteristics of the MOS transistor were measured.

When the source is set to GND and the gate voltage is kept constant at 3 V, and the drain voltage is raised from 0 V to every 0.1 V, the kink current which appears from 3 V in the conventional MOS transistor on SOI is reduced by the present embodiment. S by example
No longer observed for MOS transistors on OI.

In addition, as a result of adopting the same protection circuit as that usually used for a bulk wafer, the protection circuit area, which conventionally occupies 20% of the total area of the SOI chip, can be reduced to 5%. did it.

The SOI according to the present invention as shown in FIG.
As an example of the semiconductor device formed immediately above the Si island region 93 on the substrate, or a predetermined region of the semiconductor device, a high withstand voltage element may be used. For a semiconductor device or a predetermined region of the semiconductor device built thereon, the Si active layer 94 and the underlying Si substrate 91 are
It is not limited to those described in the above embodiments as long as the effect of the connection at 93 is exhibited.

[0079]

As described above, according to the present invention,
An SOI substrate by a bonding method in which a semiconductor region which connects an upper semiconductor layer and a base semiconductor layer (or a semiconductor substrate) between insulating regions is provided can be provided.

When forming a field-effect transistor such as a MOS transistor and a protection circuit for ESD protection, the elements were formed so that the semiconductor region provided between the insulating regions was located immediately below the channel region or immediately below the protection circuit. .

As a result, excess carriers can be dissipated from the active layer to the underlying substrate side. If the channel of the field-effect transistor is formed above the conductive region, the kink current is reduced. And the suppression of the bipolar effect.

When an ESD protection diode is formed so as to be provided, the protection effect is the same as that of the bulk protection diode, so that a special protection circuit for SOI is not required.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor member according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a basic manufacturing process of an SOI substrate by a bonding method using a porous layer as a separation layer.

FIG. 3 is a cross-sectional view showing a mask alignment manufacturing step of the SOI according to the first embodiment of the present invention.

FIG. 4 is a sectional view illustrating a manufacturing process of a semiconductor member according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a manufacturing process of a semiconductor member according to a third embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a mask alignment manufacturing step of an SOI according to a third embodiment of the present invention.

FIG. 7 is a sectional view illustrating a manufacturing process of a semiconductor member according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a device configuration of an SOI substrate provided by the present invention.

FIG. 9 is a cross-sectional view showing an SOI structure manufactured by a method provided by the present invention.

FIG. 10 is a sectional view showing an SOI structure.

FIG. 11 is a schematic sectional view showing a MOS transistor on an SOI.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Photomask 12 Epitaxial Si layer 13 Base substrate 14 Other substrate 15 Separation layer 16 Semiconductor layer 17 Silicon oxide film 18 Area

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/08 331 H01L 27/08 102F 29/786 29/78 627D 21/336

Claims (16)

[Claims] A step of preparing a first member having a plurality of insulating regions and a plurality of semiconductor regions provided between the plurality of insulating regions; and a step of preparing the first member and a second semiconductor substrate. Bonding a member and a multilayer structure in which the plurality of insulating regions and the plurality of semiconductor regions are located inside; and forming the plurality of insulating regions and the plurality of the plurality of insulating regions on the second member side. Transferring a semiconductor region to the semiconductor member. 2. A first member having a plurality of insulating regions and a plurality of semiconductor regions provided between the plurality of insulating regions is provided on the semiconductor substrate or on the semiconductor layer of the substrate having a semiconductor layer. A step of bonding the first member and a second member that is a semiconductor substrate such that a multilayer structure in which the plurality of insulating regions and the plurality of semiconductor regions are located inside is obtained; Transferring the plurality of insulating regions, the plurality of semiconductor regions, and a part of the semiconductor substrate or the semiconductor layer to the second member side. 3. The semiconductor member according to claim 1, wherein the transfer step is performed by separating the first member with a separation layer provided below the plurality of insulating regions and the plurality of semiconductor regions. Production method. 4. The semiconductor member according to claim 2, wherein the transfer step is performed by separating the first member within a semiconductor substrate or a separation layer provided below the semiconductor layer of the substrate. Production method. 5. A step of preparing a first member having a plurality of insulating regions and a plurality of semiconductor regions provided between the plurality of insulating regions; and a step of preparing a second member having a semiconductor layer. The first member and the plurality of insulating regions and the plurality of semiconductor regions of the first member, and the first member so that a multilayer structure in which the semiconductor layer of the second member is located inside is obtained. A method of manufacturing a semiconductor member, comprising: a step of bonding the second member; and a step of transferring the semiconductor layer to the first member. 6. A step of preparing a first member having a plurality of insulating regions and a plurality of semiconductor regions provided between the plurality of insulating regions; and providing the plurality of insulating regions of the first member and the plurality of semiconductor regions. Bonding the first member and a second member that is a semiconductor base so that a multilayer structure in which a plurality of semiconductor regions are located inside is obtained; and a step of bonding the second member on the first member side. Transferring a part of the semiconductor substrate of the member. 7. The method according to claim 5, wherein the transfer step is performed by separating the second member with a separation layer provided below the semiconductor layer of the second member. 8. The semiconductor device according to claim 2, wherein the semiconductor layer is formed by epitaxial growth.
3. The method for manufacturing a semiconductor member according to item 1. 9. The method for manufacturing a semiconductor member according to claim 6, wherein the transfer step is performed by separating the second member with a separation layer provided in a semiconductor substrate of the second member. 10. The plurality of insulating regions and the plurality of semiconductor regions are formed by forming an insulating layer on a semiconductor surface, opening the insulating layer, and depositing the semiconductor region in the opening. 10. The method according to claim 1, wherein
13. The method for manufacturing a semiconductor member according to the above item. 11. The semiconductor device according to claim 1, wherein the plurality of insulating regions and the plurality of semiconductor regions are formed by selectively providing an insulating region in a semiconductor substrate or a semiconductor layer.
10. The method for manufacturing a semiconductor member according to any one of items 9 to 9. 12. A semiconductor member manufactured by the manufacturing method according to claim 1. Description: 13. A semiconductor device using a semiconductor member manufactured by the manufacturing method according to claim 2, wherein the semiconductor device is located immediately above the semiconductor region. A semiconductor device in which at least a part of a semiconductor circuit is provided in a region in the semiconductor layer or a region in a part of the semiconductor base. 14. The semiconductor device according to claim 13, wherein said semiconductor circuit is a protection circuit against external overvoltage and overcurrent. 15. The semiconductor device according to claim 13, wherein said semiconductor circuit is a protection circuit against overvoltage and overcurrent from outside and a channel region of a field effect transistor. 16. The semiconductor device according to claim 13, wherein said semiconductor circuit is a protection circuit against an external overvoltage or overcurrent, and a high breakdown voltage semiconductor element.