JP2001320033A5 - Manufacturing method of semiconductor members - Google Patents
Manufacturing method of semiconductor members Download PDFInfo
- Publication number
- JP2001320033A5 JP2001320033A5 JP2000137214A JP2000137214A JP2001320033A5 JP 2001320033 A5 JP2001320033 A5 JP 2001320033A5 JP 2000137214 A JP2000137214 A JP 2000137214A JP 2000137214 A JP2000137214 A JP 2000137214A JP 2001320033 A5 JP2001320033 A5 JP 2001320033A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- manufacturing
- regions
- layer
- semiconductor members
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Description
【特許請求の範囲】
【請求項１】 分離層と、該分離層の上に複数の絶縁領域と該複数の絶縁領域間に設けられた複数の半導体領域とを有する第１の部材を用意する工程と、
前記第１の部材と半導体基体である第２の部材とを、前記複数の絶縁領域と前記複数の半導体領域とが内側に位置する多層構造体が得られるように貼り合わせる工程と、
前記多層構造体を前記分離層で分離することで、前記第２の部材側に前記複数の絶縁領域と前記複数の半導体領域とを移設する工程と、を有する半導体部材の製造方法。
【請求項２】 前記複数の絶縁領域と前記複数の半導体領域は、半導体面上に絶縁層を形成し、該絶縁層を開口した後に、開口部に前記半導体領域を堆積することで形成されることを特徴とする請求項１に記載の半導体部材の製造方法。
【請求項３】 前記複数の絶縁領域と前記複数の半導体領域は、半導体基体又は半導体層に選択的に絶縁領域を設けることで形成されることを特徴とする請求項１に記載の半導体部材の製造方法。
【請求項４】 前記分離層は、陽極化成法により形成された多孔質層であることを特徴とする請求項１に記載の半導体部材の製造方法。
【請求項５】 前記分離層は、イオン注入により形成されたイオン注入層であることを特徴とする請求項１に記載の半導体部材の製造方法。
【請求項６】 前記第１の部材を用意する工程は、前記分離層の上に半導体層を形成し、該半導体層の上に前記複数の絶縁領域と前記複数の半導体領域とを形成する工程を含むことを特徴とする請求項１に記載の半導体部材の製造方法。
[Claims]
[Claim 1] On the separation layer and on top of the separation layerA step of preparing a first member having a plurality of insulating regions and a plurality of semiconductor regions provided between the plurality of insulating regions, and a step of preparing the first member.
A step of bonding the first member and the second member, which is a semiconductor substrate, so as to obtain a multilayer structure in which the plurality of insulating regions and the plurality of semiconductor regions are located inside.
By separating the multilayer structure with the separation layer,A method for manufacturing a semiconductor member, comprising a step of relocating the plurality of insulating regions and the plurality of semiconductor regions to the second member side.
2. The plurality of insulating regions and the plurality of semiconductor regions are characterized in that an insulating layer is formed on a semiconductor surface, the insulating layer is opened, and then the semiconductor region is deposited in the openings. Claim1The method for manufacturing a semiconductor member according to.
3. A claim, wherein the plurality of insulating regions and the plurality of semiconductor regions are formed by selectively providing insulating regions on a semiconductor substrate or a semiconductor layer.1The method for manufacturing a semiconductor member according to.
4. The method for manufacturing a semiconductor member according to claim 1, wherein the separation layer is a porous layer formed by an anodization method.
5. The method for manufacturing a semiconductor member according to claim 1, wherein the separation layer is an ion-implanted layer formed by ion implantation.
6. The step of preparing the first member includes a step of forming a semiconductor layer on the separation layer and forming the plurality of insulating regions and the plurality of semiconductor regions on the semiconductor layer. The method for manufacturing a semiconductor member according to claim 1.
【０００１】
【発明の属する技術分野】
本発明は半導体部材の製造方法に係わり、特に半導体面上に絶縁層を介して半導体層を有するＳＯＩ基板の製造方法に関する。
[0001]
[Technical field to which the invention belongs]
The present invention relates to a method for manufacturing a semiconductor member, and more particularly to a method for manufacturing an SOI substrate having a semiconductor layer on a semiconductor surface via an insulating layer.
【０００５】
【課題を解決するための手段】
本発明の半導体部材の製造方法は、分離層と、該分離層の上に複数の絶縁領域と該複数の絶縁領域間に設けられた複数の半導体領域とを有する第１の部材を用意する工程と、
前記第１の部材と半導体基体である第２の部材とを、前記複数の絶縁領域と前記複数の半導体領域とが内側に位置する多層構造体が得られるように貼り合わせる工程と、
前記多層構造体を前記分離層で分離することで、前記第２の部材側に前記複数の絶縁領域と前記複数の半導体領域とを移設する工程と、を有するものである。
0005
[Means for solving problems]
The method for manufacturing a semiconductor member of the present invention is a step of preparing a first member having a separation layer and a plurality of insulating regions and a plurality of semiconductor regions provided between the plurality of insulating regions on the separating layer. When,
A step of bonding the first member and the second member, which is a semiconductor substrate, so as to obtain a multilayer structure in which the plurality of insulating regions and the plurality of semiconductor regions are located inside.
By separating the multilayer structure by the separation layer, the process includes a step of transferring the plurality of insulating regions and the plurality of semiconductor regions to the second member side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000137214A JP2001320033A (en) | 2000-05-10 | 2000-05-10 | Semiconductor member and method for manufacturing the same and semiconductor device using the method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000137214A JP2001320033A (en) | 2000-05-10 | 2000-05-10 | Semiconductor member and method for manufacturing the same and semiconductor device using the method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001320033A JP2001320033A (en) | 2001-11-16 |
| JP2001320033A5 true JP2001320033A5 (en) | 2005-11-04 |
Family
ID=18645023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000137214A Pending JP2001320033A (en) | 2000-05-10 | 2000-05-10 | Semiconductor member and method for manufacturing the same and semiconductor device using the method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001320033A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7611928B2 (en) | 2002-04-16 | 2009-11-03 | Infineon Technologies Ag | Method for producing a substrate |
| TWI242796B (en) | 2002-09-04 | 2005-11-01 | Canon Kk | Substrate and manufacturing method therefor |
| JP2004103855A (en) | 2002-09-10 | 2004-04-02 | Canon Inc | Substrate and its manufacturing method |
| JP5433990B2 (en) * | 2008-06-19 | 2014-03-05 | セイコーエプソン株式会社 | Thin film device transfer method |
| KR102204732B1 (en) * | 2019-11-11 | 2021-01-19 | (주)더숨 | Producing method of silicon on insulator substrate |
-
2000
- 2000-05-10 JP JP2000137214A patent/JP2001320033A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2233096A1 (en) | Substrate and production method thereof | |
| JP2000223681A5 (en) | Substrate manufacturing method | |
| EP1026728A3 (en) | Substrate and method of manufacturing the same | |
| CA2221100A1 (en) | Process for producing semiconductor article | |
| JP2000223682A5 (en) | ||
| IL201926A0 (en) | Semiconductor structure implementing sacrificial material and methods for making and implementing the same | |
| JP2000223683A5 (en) | Method for separating composite members, method for transferring transfer layer, and method for manufacturing SOI substrate | |
| WO2001020647A3 (en) | Novel chip interconnect and packaging deposition methods and structures | |
| TW200805479A (en) | Method of manufacturing a semiconductor device | |
| JP2002334973A5 (en) | ||
| CA2536431A1 (en) | Process for fabricating a micro-electro-mechanical system with movable components | |
| WO2005122284A3 (en) | Semiconductor-on-diamond devices and methods of forming | |
| WO2006037933A3 (en) | Method for providing mixed stacked structures, with various insulating zones and/or electrically conducting zones vertically localized | |
| EP1398829A3 (en) | Substrate and manufacturing method therefor | |
| JP2001186725A (en) | Press-molded v-shape groove pancake type slip ring | |
| TW372366B (en) | Method of manufacturing semiconductor article | |
| TW200713420A (en) | Method of fabricating shallow trench isolation structure | |
| EP1396883A3 (en) | Substrate and manufacturing method therefor | |
| JP2005347302A5 (en) | ||
| TW200608459A (en) | Method for fabricating semiconductor device and semiconductor device | |
| WO2002101818A3 (en) | Method for isolating semiconductor devices | |
| JP2001320033A5 (en) | Manufacturing method of semiconductor members | |
| TWI264766B (en) | Method for fabricating recessed gate structure | |
| JPS60176265A (en) | Semiconductor memory device | |
| KR20030026838A (en) | Method of producing semiconductor device |