KR100609367B1 - Manufacturing method of silicon on insulator wafer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon on insulator (hereinafter, referred to as a 'SOI') substrate. Forming a semiconductor epitaxial layer and a semiconductor layer sequentially on the exposed upper surface of the first wafer after removing the first oxide layer on the first wafer so that the upper surface of the first wafer is exposed; Bonding a second wafer on which a second oxide film having a predetermined thickness is formed on the semiconductor layer, a first oxide film below the first wafer, a first wafer below the buried oxide layer, and the buried oxide film to expose the semiconductor layer; Sequentially removing the layer, the first wafer and the semiconductor epitaxial layer between the semiconductor epitaxial layer and the buried oxide layer, thereby comparing the process. Simple, and easy implementation, high uniformity and there is an effect that it is possible to manufacture the SOI substrate having the characteristics of ultra-thin film.

Nano device, semiconductor, SOI, silicon wafer, buried oxide layer, oxygen ion, semiconductor epitaxial layer

Description

Manufacturing method of SOI substrate {Manufacturing method of silicon on insulator wafer}

1A to 1J are cross-sectional views illustrating a method of manufacturing an SOI substrate according to an embodiment of the present invention.

*** Explanation of symbols on main parts of drawing ***

100: first silicon wafer, 110: buried oxide film layer,

120: first oxide film, 130: semiconductor epitaxial film layer,

140: semiconductor layer, 200: second silicon wafer,

210: second oxide film, 300: silicon nitride film

The present invention relates to a method for manufacturing a silicon on insulator (SOI) substrate having an ultra-thin upper silicon film, which is the key to the implementation of ultra-high integration, ultra-fast, and low-power semiconductor integrated circuits. The present invention relates to a method for manufacturing an ultra-thin SOI substrate having uniform thickness and high quality and good interfacial properties, which are essential for fabricating nanoscale semiconductor devices.

In general, SOI substrates have been developed as substrates of next-generation electronic devices that can solve problems such as incomplete insulation and generation of parasitic capacitance between devices existing in silicon substrates when integrating many electronic devices.

The structure of the SOI substrate refers to the presence of an insulating film on a silicon wafer, and a single crystal silicon film is formed on top of the silicon wafer. In the broad definition, a silicon single crystal is formed on the top of the substrate regardless of the type of the substrate and the insulating film. Refers to the formed structure.

The manufacturing technology of the SOI substrate started with the research of Silicon On Sapphire (SOS) in the 1960s.In the early stages, recrystallization (ZMR), porous silicon oxidation, and silicon lateral epitaxial growth method were studied. As a result of continuous technological competition and market choices, the mainstream is SIMX (Separation by IMplantation of OXygen) technology, UNIBOND technology using smart cut, and Epitaxial Layer TRANsfer (ELTRAN) technology.

According to the conventional SIMOX technology, first, oxygen is injected into the silicon at about 1 to 9 × 10 ¹⁷ atoms / cm 2, and then a high temperature of about 1300 to 1500 ° C. is used to recrystallize the silicon, stabilize the buried oxide film, and remove defects. Annealing and oxidation are carried out at.

However, as described above, the conventional SIMOX technology has a problem in that it is difficult to fabricate a silicon layer having a uniform thickness and low impurity concentration, and adversely affect the device such as high defect density and poor roughness at and near the interface.

In addition, according to the conventional UNIBOND technology, first, a hydrogen ion is implanted into a silicon wafer on which an insulating film is formed, and then bonded to another silicon wafer, and then a lower portion of the ion implantation position is dropped on the hydrogen ion implanted wafer through a subsequent heat treatment process. By using the smart cut method to form a thin silicon layer by exiting, the effect of higher crystal quality, higher box quality, less surface roughness and lower price process in thick film SOI than other conventional methods can be expected. However, there is still a problem that the productivity is lowered due to the lack of thickness uniformity and various steps such as chemical mechanical polishing (CMP).

In addition, the conventional ELTRAN technology first forms a porous silicon layer on a silicon wafer, epitaxially forms a polycrystalline silicon layer thereon, and then joins the silicon wafer having an insulating film formed thereon. After removing all the silicon wafers and the porous silicon layer of the wafer on which the single crystal is formed by a polishing and etching process to obtain a flat silicon layer, the thickness of the silicon film is relatively easy to control, but is easily matched with a conventional CMOS process. However, there are problems that are limited to some applications due to film quality degradation, particle generation and surface roughness deterioration, and reliability problems.

As described above, for example, conventional technologies for manufacturing a UTB SOI substrate used in manufacturing a UTB SOI CMOS device (SIMOX, UNIBOND, and ELTRAN, etc.) include nanometers such as thickness uniformity, defect density, and several nm upper silicon thickness control characteristics. It is a situation that does not completely satisfy the ultra-thin SOI wafer specification required in the class device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing an ultra-thin SOI substrate having a uniform thickness and high quality and good interfacial properties, which are essential for manufacturing a nanoscale semiconductor device.

In order to achieve the above object, an aspect of the present invention, (a) after forming a buried oxide film layer in a predetermined depth of the first wafer to form a first oxide film on the first wafer; (b) removing the first oxide film on the first wafer so that the top surface of the first wafer is exposed, and then sequentially forming a semiconductor epitaxial layer and a semiconductor layer on the exposed top surface of the first wafer; (c) bonding a second wafer on which the second oxide film having a predetermined thickness is formed on the semiconductor layer; And (d) a first oxide film under the first wafer, a first wafer under the buried oxide layer, the buried oxide layer, a first wafer between the semiconductor epitaxial layer and the buried oxide layer to expose the semiconductor layer; It is to provide a method for producing an SOI substrate comprising the step of sequentially removing the semiconductor epitaxial layer.

Here, the step (a) may include: (a-1) implanting oxygen ions on the surface of the first wafer to form the buried oxide film layer at a predetermined depth of the first wafer; And (a-2) forming the first oxide film on the surface of the first wafer by performing a heat treatment and an oxidation process so that the interface between the buried oxide film layer is uniform and the defects of the rough surface are removed. desirable.

Preferably, the semiconductor epitaxial layer is formed of a SiGe / Si epitaxial layer, and the Ge composition in the SiGe epitaxial layer is 10 to 80%.

Preferably, the semiconductor layer is formed by performing a heat treatment with a tensile silicon layer.

Preferably, in the step (c), after the bonding of the second wafer further comprises the step of depositing a silicon nitride film on the entire surface of the resultant to protect the bonding surface.

Preferably, in step (d), the removal of the first oxide film under the first wafer is selectively performed so that the first wafer under the buried oxide layer is exposed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. It doesn't happen. Like numbers refer to like elements in the figures.

1A to 1J are cross-sectional views illustrating a method of manufacturing an SOI substrate according to an embodiment of the present invention.

Referring to FIG. 1A, a predetermined oxygen ion 105 is implanted into a surface of a first silicon wafer 100 used as a control wafer.

At this time, the oxygen ion 105 is preferably injected at about 1 to 5 × 10 ^17-18 atoms / cm 2 in the energy range of about 30 to 200 KeV.

Referring to FIG. 1B, a heat treatment and an oxidation process are performed to form a buried oxide layer 110 at a predetermined depth while recrystallizing silicon and removing defects. In this case, the buried oxide layer 110 is formed at a predetermined depth of the first silicon wafer 100 by the implanted oxygen ions 105, and the entire surface portion of the buried oxide film layer 110 is formed in a thickness range of about 50 to 200 nm by oxidation. A first oxide film 120 in the form of a box is formed.

Therefore, the interface between the buried oxide layer 110 is uniform and the rough surface defects are removed. That is, when the heat treatment is further performed in the oxidizing atmosphere, defects on the surface may be concentrated at the interface of the buried oxide layer 110, thereby greatly improving the interface state and film quality. This oxidation process may be omitted in some cases, and if necessary, it may be actively used as a method for reducing defects, improving interfacial roughness, and reducing the thickness of the first silicon wafer 100.

In addition, the thickness of the first silicon wafer 100 is primarily thinned by the formation of the first oxide film 120.

On the other hand, the heat treatment process is preferably carried out in a temperature range of about 1300 ℃ to 1500 ℃.

Referring to FIG. 1C, after removing the first oxide film 120 formed on the first silicon wafer 100 so that the upper portion of the first silicon wafer 100 is exposed, the exposed first silicon wafer 100 is removed. The semiconductor epitaxial layer 130 and the semiconductor layer 140 are sequentially formed on the top.

In this case, the semiconductor epitaxial layer 130 may be formed of, for example, a SiGe / Si epitaxial layer, and the Ge composition in the SiGe epitaxial layer may be 10 to 80%.

The semiconductor layer 140 may be formed by, for example, performing a predetermined heat treatment on a strained silicon layer.

Referring to FIG. 1D, a second silicon wafer 200 used as a handle wafer is prepared. In this case, it is preferable to form the second oxide film 210 in the form of a box in a thickness range of about 5 to 1000 nm on the entire surface of the second silicon wafer 200.

Referring to FIG. 1E, a conventional wafer bonding method (eg, hydrogen) is performed between the semiconductor layer 140 of the first silicon wafer 100 and the second oxide film 210 under the second silicon wafer 200. Bonding so as to face each other by a bonding method).

Referring to FIG. 1F, for example, chemical vapor deposition is performed on the entire surface of the resultant to protect the bonding surface of the first silicon wafer 100 and the second silicon wafer 200, that is, the sidewalls exposed after the bonding. A silicon nitride film 300 having a predetermined thickness is deposited by using a deposition method, a CVD method, or the like.

Referring to FIG. 1G, after the silicon nitride layer 300 under the first silicon wafer 100 is selectively removed to expose the first oxide layer 120 under the first silicon wafer 100, the buried oxide layer The first oxide film 120 under the first silicon wafer 100 is selectively removed to expose the first silicon wafer 100 under the 110.

Referring to FIG. 1H, after selectively removing the first silicon wafer 100 under the buried oxide layer 110 by using the buried oxide layer 110 as an etch stop layer, the semiconductor epitaxial layer 130 and The buried oxide layer 110 is removed by, for example, a wet etching method such that the first silicon wafer 100 between the buried oxide layer 110 is exposed.

Referring to FIG. 1I, after the remaining silicon nitride film 300 is completely removed, the first silicon wafer between the semiconductor epitaxial layer 130 and the buried oxide layer 110 is exposed to expose the semiconductor epitaxial layer 130. Optionally remove (100).

At this time, the first silicon wafer 100 is preferably removed by, for example, chemical mechanical polishing (CMP), wet or dry etching.

Referring to FIG. 1J, the semiconductor epitaxial layer 130 is removed to expose the semiconductor layer 140. In this case, the semiconductor epitaxial layer 130 may be removed using an etching solution (eg, SC-1 solution) having a large etching selectivity with respect to the semiconductor layer 140.

On the other hand, in order to improve the roughness and thinning of the exposed semiconductor layer 140, it is preferable to perform a chemical mechanical polishing (CMP), hydrogen heat treatment or plasma hydrogen heat treatment method.

While a preferred embodiment of the method for manufacturing the SOI substrate according to the present invention has been described above, the present invention is not limited thereto, and the present invention is not limited thereto, but is variously modified within the scope of the claims and the detailed description of the invention and the accompanying drawings. It is possible and this also belongs to the present invention.

According to the method for manufacturing the SOI substrate of the present invention as described above, there is an advantage that can provide an ultra-thin SOI substrate having a uniform thickness and high quality good interfacial properties essential for the fabrication of nanoscale semiconductor devices.

In addition, according to the present invention, the process is relatively simple and easy to implement because it utilizes existing techniques, and expensive chemical mechanical polishing (CMP) process and the like may not be used.

In addition, according to the present invention, there is an advantage that can contribute to advance the practical application of nano-scale semiconductor device, next-generation new device research, ultra-high performance circuit and system design fabrication and applied products.

Claims (14)

(a) forming a buried oxide layer at a predetermined depth of the first wafer and then forming a first oxide film on the first wafer; (b) removing the first oxide film on the first wafer so that the top surface of the first wafer is exposed, and then sequentially forming a semiconductor epitaxial layer and a semiconductor layer on the exposed top surface of the first wafer; (c) bonding a second wafer on which the second oxide film having a predetermined thickness is formed on the semiconductor layer; And (d) a first oxide layer under the first wafer, a first wafer under the buried oxide layer, a buried oxide layer, a first wafer between the semiconductor epitaxial layer and the buried oxide layer such that the semiconductor layer is exposed; And sequentially removing the semiconductor epitaxial layer. The method of claim 1, wherein step (a) (a-1) forming the buried oxide film layer at a predetermined depth in the first wafer by injecting oxygen ions into the surface of the first wafer; And (a-2) forming the first oxide film on the surface of the first wafer by performing a heat treatment and an oxidation process so that the interface between the buried oxide layer is uniform and the defects on the rough surface are removed. A method for producing an SOI substrate. The method of claim 2, wherein the oxygen ion is implanted at 1 to 5 × 10 ^{17 to 18} atoms / cm 2 in an energy range of 30 to 200 KeV. The method of claim 2, wherein the heat treatment is performed at a temperature in the range of 1300 to 1500 ° C. 4. The method of claim 1, wherein the semiconductor epitaxial layer is formed of a SiGe / Si epitaxial layer, and the Ge composition in the SiGe epitaxial layer is 10 to 80%. The method of claim 1, wherein the semiconductor layer is formed by performing heat treatment with a tensile silicon layer. 2. The SOI substrate of claim 1, further comprising depositing a silicon nitride film on the entire surface of the resultant in step (c) after bonding the second wafer to protect the junction surface. Manufacturing method. The method of claim 7, further comprising selectively removing the silicon nitride film under the first wafer after depositing the silicon nitride film. The method of claim 1, wherein in the step (d), the removal of the first oxide layer under the first wafer is selectively performed so that the first wafer under the buried oxide layer is exposed. . The method of claim 1, wherein in the step (d), the buried oxide layer is selectively removed when the first wafer under the buried oxide layer is removed as an etch stop layer. The method of claim 1, wherein in the step (d), the removal of the buried oxide layer is performed by selectively removing the first wafer between the semiconductor epitaxial layer and the buried oxide layer. . The method of claim 1, wherein in step (d), the semiconductor epitaxial layer is selectively removed to expose the semiconductor epitaxial layer when the first wafer between the semiconductor epitaxial layer and the buried oxide layer is removed. . The method of claim 1, wherein in the step (d), an SOI substrate is removed using an etching solution having a high etching selectivity with respect to the semiconductor layer so that the semiconductor layer is exposed when the semiconductor epitaxial layer is removed. Way. 2. The method of claim 1, wherein in step (d), a chemical mechanical polishing (CMP) or hydrogen heat treatment method is performed to improve roughness and thinner the exposed semiconductor layer.

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