JP4328708B2 - Manufacturing method of CMOS device and structure including CMOS device - Google Patents

Description

  The present invention relates to high performance metal oxide semiconductor field effect transistors (MOSFETs) for digital or analog use, and more particularly to MOSFETs using increased carrier mobility from surface orientation.

  In today's semiconductor technology, CMOS devices such as nFETs and pFETs are typically fabricated on a semiconductor wafer such as Si having a single crystal orientation. In particular, most of today's semiconductor devices are built on Si with a (100) crystal orientation.

  It is well known that electrons have a high mobility in the (100) Si surface orientation and holes have a high mobility in the (110) surface orientation. It is well known. That is, the value of hole mobility on (100) Si is roughly ½ to ¼ compared to the corresponding electron mobility in the case of this crystal orientation. To compensate for this discrepancy, the pFET is typically designed wider so that the pull-up currents are balanced against the pull-down currents of the nFET and uniform circuit switching is achieved. Wide pFETs are undesirable because they occupy a significant portion of the chip area.

  On the other hand, the hole mobility on (110) Si is doubled compared to that on (100) Si, so the pFET formed on the (110) plane is the same as the pFET formed on the (100) plane. Compared with a considerably higher drive current. Unfortunately, the electron mobility on the (110) Si surface is significantly lower than that on the (100) Si surface.

  As can be inferred from the above discussion, the (110) Si plane is optimal for pFET devices due to its excellent hole mobility, but such crystal orientation is not at all suitable for nFET devices. Instead, the (100) Si plane is optimal for nFET devices because its crystal orientation favors electron mobility.

  Various methods for forming planar hybrid substrates with different plane orientations by wafer bonding have been described. In such efforts, to fabricate high-performance devices, by implementing pFETs and nFETs on their own optimal crystal orientations, primarily by semiconductor-insulator or insulator-insulator wafer bonding. This planar hybrid substrate is obtained. However, at least one type of MOSFET (either pFET or nFET) is on a semiconductor-on-insulator (SOI), and the other type of MOSFET is on a bulk semiconductor or on an SOI with a thicker SOI coating.

  There are other techniques in which both nFETs and pFETs are fabricated on the same thickness of SOI and include additional processing steps. SOI devices generally have higher performance than bulk devices due to lower parasitic capacitance. However, it is known that SOI devices have a floating body (ie, well), the effect of which varies with SOI thickness. In general, each SOI device is separated from each other by a shallow trench isolation (STI) region and a buried oxide (BOX). This prior art structure is shown, for example, in FIG. In order to avoid this floating body effect, each SOI device requires an individual body contact. With such a structure, the chip area increases considerably.

On the other hand, MOSFET bodies fabricated on bulk silicon substrates are usually connected by well contacts deeper than STI. Bulk devices are separated from each other by STI, but their body contacts can be connected through a common well contact (see FIG. 2).
US patent application Ser. No. 10 / 250,241 US patent application Ser. No. 10 / 696,634 JB Lasky, “Waferbonding for silicon-on-insulator technologies”, Appl. Phys. Lett., V48, p. 78, 1986. JB Lasky, “Silicon-On-Insulator (SOI) by bonding and etch-back”, IEDM Tech. Dig, page 684, 1985 S. Bengtsson et al., “Interfacecharge control of directly bonded silicon structures”, J. Appl. Phys. V66, p. 1231, 1989. S. Farrens, “Chemical free room temperature wafer to wafer bonding”, J. Electrochem. Soc. Vol 142, p. 3949, 1995 M. Shimbo, “Silicon-to-silicon direct bonding method”, J. Appl. Phys. V60, p. 2987, 1986

  In view of the foregoing, there is a need to provide a structure comprising pFETs and nFETs on a hybrid substrate of various crystal orientations, both of which are bulk devices, and have body contacts by wells or substrates.

  One object of the present invention is to provide a method for integrating semiconductor devices such that different types of devices are formed on a special crystal orientation of a hybrid substrate that enhances the performance of each type of device.

  Another object of the present invention is to provide a method for integrating semiconductor devices such that the pFET is located on the (110) crystal plane of the hybrid substrate and the nFET is located on the (100) crystal plane of the hybrid substrate. It is.

  Another object of the present invention is to provide a method for integrating semiconductor devices on a hybrid substrate having different crystal orientations, such that each device is a bulk device and is located on a crystal orientation that enhances device performance. That is.

  Yet another object of the present invention is to provide a method for integrating semiconductor devices on hybrid substrates having different crystal orientations, such that each device has its own body contact through the well or substrate. It is.

  An additional object of the present invention is to provide a method for integrating CMOS devices on a hybrid substrate with various crystal planes, in which isolation regions are formed between different types of CMOS devices.

  These and other objects and advantages are realized in one embodiment of the present invention by using a method that uses semiconductor-semiconductor, particularly Si-Si direct wafer bonding, as one of the processing steps. This embodiment is used when a hybrid structure with a thin conductive interface (less than 10 nm) or an insulating interface is desired. In another embodiment where a thick insulating interface (10 nm or greater) is desired, the wafer including the first insulating layer may be bonded to another wafer that may or may not include the second insulating layer. it can. According to the present invention, two semiconductor wafers or substrates having different crystal orientations are directly subjected to the wafer bonding method. Following this direct wafer bonding, the hybrid substrate thus obtained is subjected to a patterning step, an etching step, a semiconductor layer regrowth step, an isolation region forming step, and a semiconductor device forming step.

One embodiment of the present invention provides:
A first semiconductor layer comprising a first crystal orientation;
With respect to a hybrid substrate comprising a second semiconductor layer having a second crystal orientation different from the first crystal orientation, the first and second semiconductor layers are separated from each other by a (conductive or insulating) interface.

More specifically, the present invention provides:
A first semiconductor layer having a first crystal orientation;
A hybrid substrate comprising a second semiconductor layer having a second crystal orientation different from the first crystal orientation is provided. The first and second semiconductor layers are separated from each other by an interface, the second semiconductor layer has a thickness of about 200 nm to 2 μm, and the interface is an oxide film having a thickness of about 10 nm or more.

Another aspect of the present invention is directed to a method for manufacturing a hybrid substrate as described above. More specifically, this hybrid substrate is
Providing a first semiconductor wafer comprising a first semiconductor material comprising a first crystal orientation and a second semiconductor wafer comprising a second semiconductor material comprising a second crystal orientation different from the first crystal orientation;
Bonding the first semiconductor wafer to the second semiconductor wafer is fabricated using a method in which an interface (conductive or insulating) is formed or exists between the two substrates.

Yet another aspect of the present invention provides:
A hybrid structure comprising a first device region having a first crystal orientation and a second device region having a second crystal orientation, wherein the first crystal orientation is different from the second crystal orientation;
An isolation region that separates the first device region from the second device region;
At least one first semiconductor device located in the first device region and at least one second semiconductor device located in the second device region, both of the first semiconductor device and the second semiconductor device being in bulk form Device relates to an integrated semiconductor structure including a well region where both devices serve as body contacts.

Yet another aspect of the present invention provides:
It includes at least a first semiconductor layer having a first crystal orientation and a second semiconductor layer having a second crystal orientation separated by an interface (conductive or insulating), and the first crystal orientation is the second crystal orientation. Differently, providing a hybrid substrate, wherein the first semiconductor layer is below the second semiconductor layer;
Selectively etching a portion of the hybrid substrate to expose a surface of the first semiconductor layer;
Re-growing a semiconductor material having the same crystal orientation as the first crystal orientation on the exposed surface of the first semiconductor layer;
Providing a well region in the second semiconductor layer and in the regrown semiconductor material;
Forming at least one first semiconductor device on the regrown semiconductor material and forming at least one second semiconductor device on the second semiconductor layer.

  The present invention, which provides a method of forming a CMOS device on a hybrid substrate having different crystal orientations using semiconductor-semiconductor direct bonding, will now be described in detail with reference to the drawings attached to this application.

  FIG. 3 shows an initial hybrid substrate 10 that can be used in the present invention and has different crystal orientations. Specifically, the hybrid substrate 10 includes a first (lower) semiconductor layer 12 and a second (upper) semiconductor layer 16 that have a bonding interface 14 between them. According to the present invention, the first semiconductor layer 12 includes a first semiconductor material having a first crystal orientation, and the second semiconductor layer 16 is a second semiconductor having a second crystal orientation different from the first crystal orientation. Contains materials.

  The first semiconductor layer 12 of the hybrid substrate 10 is made of any semiconductor material including, for example, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP, and III / V or II / VI group compound semiconductors. ing. Combinations of the above semiconductor materials are also contemplated by the present invention. The first semiconductor layer 12 may or may not be distorted, or a combination of a strained layer and an unstrained layer can be used. The first semiconductor layer 12 is also characterized by having a first crystal orientation that can be (110), (111), or (100). This first semiconductor layer 12 can optionally be formed on the top surface of a handling wafer.

  In embodiments where the first semiconductor layer 12 is a bulk handle wafer, the thickness of this layer is the thickness of the wafer.

  The second semiconductor layer 16 is made of any semiconductor material that may or may not be the same as the material of the first semiconductor layer 12. Accordingly, the second semiconductor layer 16 can include, for example, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP, and III / V or II / VI group composite semiconductors. The second semiconductor layer 16 may include a combination of the above semiconductor materials. The second semiconductor layer 16 may or may not be distorted, or a combination of strained and unstrained layers (eg, strained Si on relaxed SiGe) can be used.

  The second semiconductor layer 16 is also characterized by having a second crystal orientation different from the first crystal orientation. Therefore, the crystal orientation of the second semiconductor layer 16 is (100), (111), or (110) under the condition that the crystal orientation of the second semiconductor layer 16 is not the same as the crystal orientation of the first semiconductor layer 12. is there.

  The thickness of the second semiconductor layer 16 varies depending on the initial starting wafer used to form the hybrid substrate 10. However, the thickness of the second semiconductor layer 16 is generally about 50 nm to about 200 μm, more preferably about 150 nm to about 2 μm.

  The bonding interface 14 between the first semiconductor layer 12 and the second semiconductor layer 16 is a conductive or insulating interface. The thickness of the conductive interface 14 is generally about 10 nm or less depending on the application, and the thickness of the insulating interface 14 is about 10 nm or more. The thickness of this interface 14 depends on the bonding process used and depends on whether the surface has been treated with a hydrophilic or hydrophobic reagent prior to bonding.

  The exact crystal orientation of the first semiconductor layer 12 and the second semiconductor layer 16 may vary depending on the material of the semiconductor layer and the type of semiconductor device subsequently formed thereon. For example, when Si is used as the semiconductor material, the electron mobility is higher on the (100) plane orientation and the hole mobility is higher on the (110) plane orientation. In this case, the (100) Si surface is used as a device layer for nFET, and the (110) Si surface is used as a device layer for pFET.

  For example, in order to realize a bulk device on different plane orientations using the hybrid substrate 10 as shown in FIG. 3, the interface 14 between the first semiconductor layer 12 and the second semiconductor layer 16 has good electrical properties. It is preferable to have conductivity. In order to maintain the crystal quality of the second semiconductor layer 16 high, defects / charges are localized in the vicinity of the interface 14 during the formation of the hybrid substrate 10 and the subsequent processes, and the inside of the second semiconductor layer 16 (particularly near the surface). Should not be moved to.

  In the present invention, the hybrid substrate 10 shown in FIG. 3 is formed by semiconductor-semiconductor direct bonding. In such a method, two semiconductor substrates or wafers are directly bonded together without an insulating layer in between.

  Methods for obtaining an insulating layer between wafers using wafer bonding to realize a semiconductor-on-insulator structure are widely known, for example, JB Lasky, “Silicon on Insulator. Wafer bonding for silicon-on-insulator technologies ", Appl. Phys. Lett., V48, p. 78, 1986, and JB Lasky," Bonding and Etching. Silicon-On-Insulator (SOI) by bonding and etch-back ”, IEDM Tech. Dig, page 684, 1985.

The semiconductor-semiconductor direct bonding step used in the present invention to obtain a conductive interface 14 between two semiconductor wafers is described in detail below. The two wafers used to fabricate the hybrid substrate 10 include two bulk semiconductor wafers and a wafer (see FIG. 4) that includes the bulk semiconductor wafer and the etch stop layer 18 and the handling wafer 20, or A first bulk wafer and a second bulk wafer (see FIG. 5) that includes an ion implantation region 22 such as a hydrogen (ie, H ₂ ) implantation region that can be used to separate at least a portion of the wafer during bonding. Can be included.

In some (some) embodiments (not specifically shown) where a thick insulating interface exists in a hybrid structure, two semiconductors are bonded together and at least one wafer is an insulating layer thereon It has. In this case, bonding is performed between the insulating layer and the semiconductor or between two insulating layers of separate wafers. In this embodiment, bonding involves first bringing two wafers into intimate contact with each other, optionally applying an external force to the abutting wafers, and then bonding the two abutting wafers together. And heating under conditions that can be integrated. This heating step can be performed in the presence or absence of an external force. This heating step is typically performed in an inert atmosphere at a temperature of about 200 ° to about 1050 ° C. for a period of about 2 to about 20 hours. More preferably, bonding is performed at a temperature of about 200 ° to about 400 ° C. for about 2 to about 20 hours. The term “inert atmosphere” is used herein to refer to an atmosphere in which an inert gas such as He, Ar, N ₂ , Xe, Kr, or any mixed gas thereof is used. Preferred atmosphere used in the bonding process is N _2.

  In order to achieve a good conductive interface 14 by semiconductor-semiconductor direct wafer bonding, it is usually, but not always, to obtain either a hydrophilic or a hydrophobic surface before bonding. It is necessary to carry out a step of surface treating at least one, preferably both.

Hydrophobic surfaces are described, for example, by S. Bengtsson et al., “Interface charge control of directly bonded silicon structures”, J. Appl. Phys. V66, page 1231. This can be achieved using the HF dip method as disclosed in 1989, and hydrophilic surfaces can be produced, for example, by oxygen plasma (S. Farrens, "Chemical-free room temperature wafer-wafer bonding ( Chemical free room temperature wafer towafer bonding) ", J. Electrochem. Soc. Vol 142, page 3949, 1995), dry clean processes such as argon high energy beam surface etching, or H ₂ SO ₄ solution or HNO _It can be realized by wet chemical oxidation acid such as ₃ solutions, or both. Wet etching processes are described, for example, by M. Shimbo, “Silicon-to-silicon direct bonding method”, J. Appl. Phys. V60, 2987, 1986. Is disclosed.

  Hydrophobic surfaces can provide better electrical properties, but hydrophilic surfaces can also provide sufficient electrical conductivity. This is because the original oxide film present at the bonding interface is usually only 2-5 nm. Furthermore, a substrate formed by directly bonding two hydrophilic surfaces tends to increase the leakage current. In addition, a crystal bond can be formed after a high temperature anneal step is performed to further increase the current across the bonding interface 14.

  In the present invention, two wafers having different crystal orientations are first brought into intimate contact with each other, and optionally an external force is applied to the abutted wafers, and then the bonding energy between the two wafers is increased. By directly annealing the two wafers under conditions that can be increased, direct semiconductor-to-semiconductor wafer bonding is achieved (with or without the surface treatment described above). The annealing step can also be performed when there is no external force. Bonding is typically accomplished during an initial abutment step at nominal room temperature. Nominal room temperature means a temperature of about 15 ° C to about 40 ° C, more preferably a temperature of about 25 ° C.

After bonding, the wafer is usually annealed to increase the bonding strength and improve the interface characteristics. This anneal is typically performed at a temperature of about 900 ° to about 1300 ° C, more typically at an annealing temperature of about 1000 ° to about 1100 ° C. Annealing is performed for a variety of times that can range between about 1 hour to about 24 hours within the temperature range described above. The annealing atmosphere may be O ₂ , N ₂ , Ar, or a reduced pressure atmosphere, and may or may not use an external adhesive force. A mixed gas containing or not containing an inert gas in the annealing atmosphere described above is also contemplated by the present invention.

  High temperature anneals are often used (as described above), but low temperature anneals (below 900 ° C.) can also be used and still good mechanical and electrical properties can be achieved.

  This annealing step following the direct semiconductor-semiconductor bonding step can be performed at a single temperature with a specific ramp-up rate, or with various ramp rates and soak cycles. (Soak cycle) can be used and implemented at various temperatures.

  In order to obtain the second semiconductor layer 16 having a certain thickness, various layer transfer techniques can be used in the present invention. One direct and simple approach that can be used in the present invention is to use a wafer grinding, polishing, or etch back process. In order to better control the layer transfer process, an etch stop layer 18 located between the second semiconductor layer 16 and the handling wafer 20 can be used (see FIG. 4), and these etch stop layers and Both handling wafers are removed after wafer bonding. The etch stop layer 18 may be an oxide film, a nitride film, or an oxynitride, i.e., the starting top wafer is an SOI substrate. Alternatively, this etch stop layer 18 may be another semiconductor material, which can be selectively removed from the second semiconductor layer 16 after bonding and also serves as an etch stop for removing the handling wafer 20. .

Another layer transfer technique that can be used in embodiments where one of the wafers includes an ion implantation region is shown in FIG. In this case, the ion implantation region 22 forms a porous region to remove a portion of the wafer above the ion implantation region, thereby leaving a bonded wafer, such as the example shown in FIG. This implanted region 22 typically consists of hydrogen ions implanted into one surface of the wafer using ion implantation conditions well known to those skilled in the art. After bonding, a heating step is typically performed to increase the bonding energy at a temperature of about 100 ° to about 400 ° C. for only about 2 to about 30 hours. More preferably, this heating step is carried out at a temperature of about 200 ° to about 300 ° C. for only about 2 to about 20 hours. As used herein, the term “inert atmosphere” refers to an atmosphere in which an inert gas such as He, Ar, N ₂ , Xe, Kr, or a mixed gas thereof is used. Preferred atmosphere is used during the bonding process is N _2. During subsequent annealing at 350 ° C. to 500 ° C., layer separation occurs at the implantation region 22.

  The hybrid substrate 10 shown in FIG. 3 (which can be formed by various layer transfer techniques) is used as the starting substrate for the method of the present invention shown in FIGS. The process flow shown in these drawings will now be described in detail.

  After providing the hybrid substrate 10 shown in FIG. 3, the deposition may be performed using a deposition method such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition, or physical vapor deposition. 2 A hard mask layer or pad stack 24 is formed on the exposed upper surface of the semiconductor layer 16. Alternatively, the hard mask layer 24 can be formed using thermal oxidation, nitride film formation, or oxynitride film formation. A structure including the obtained hard mask layer 24 is shown, for example, in FIG.

  The hard mask layer 24 is made of, for example, an oxide film, a nitride film, an oxynitride film, or a stack thereof. The thickness of the hard mask layer 24 may vary depending on the composition of the mask material and the technique used to form the hard mask. Generally, the deposition thickness of this hard mask layer 24 is about 5 to about 500 nm.

  The hard mask layer 24 is then patterned by lithography and etching to obtain, for example, a patterned mask 24 'as shown in FIG. Using this patterned mask 24 ′ as an etching mask, the exposed portion of the second semiconductor layer 16 of the hybrid substrate 10 is removed, and the upper surface of the first semiconductor layer 12 or the inside of the first semiconductor layer 12 is removed. Stop with either one. The structure obtained after the pattern transfer is shown in FIG. As shown, the underlying first semiconductor layer 12 is provided in the hybrid structure to expose the opening 26.

  This etching and pattern transfer of the hard mask layer 24 can be performed using a single etching process or multiple etching steps can be used. This etch should include reactive ion etching, ion beam etching, dry etching methods such as plasma etching and laser etching, wet etching methods using chemical etchants, or any combination thereof. Can do. In one preferred embodiment of the present invention, reactive ion etching (RIE) is used to selectively remove unprotected portions of the second semiconductor layer 16.

  Subsequent openings 26 are used in defining different active device regions to form semiconductor devices. In accordance with the terminology used in the present application, a region including the second semiconductor layer 16 as an active device layer is referred to herein as a second device region 28 and is referred to as an active device layer (as an epitaxial regrowth layer described later). In the present specification, the region including the first semiconductor layer 12 is referred to as a first device region 30.

  An optional spacer 32 can then be formed on the exposed sidewall in the opening 26 provided by the above processing steps. This optional spacer 32 is formed by deposition and etching. This optional spacer 32 may comprise an insulating material such as, for example, an oxide film, a nitride film, an oxynitride film, or any combination thereof. This optional spacer 32 may be a single spacer as shown, or may comprise a plurality of spacers. FIG. 8 shows an optional spacer 32 in the structure.

  A semiconductor material 34 is then formed on the exposed surface of the first semiconductor layer 12 resulting in, for example, the structure shown in FIG. According to the present invention, the semiconductor material 34 has the same crystal orientation as that of the first semiconductor layer 12. This regrown semiconductor layer has the same plane orientation as the first semiconductor layer 12, but may be a layer made of a semiconductor material different from the first semiconductor layer 12.

  The semiconductor material 34 can include any semiconductor material, such as Si, strained Si, SiGe, SiC, SiGeC, or combinations thereof that can be formed using selective epitaxial growth methods. The semiconductor material 34 may or may not be distorted, or may comprise a strained layer and an unstrained layer (eg, strained Si on a relaxed SiGe layer).

  In some preferred embodiments, the semiconductor material 34 comprises Si. In other preferred embodiments, the semiconductor material 34 is a strained Si layer that may or may not be located above the relaxed SiGe alloy layer. In the present invention, the semiconductor material 34 is referred to as a regrowth semiconductor material.

  To achieve a high quality regrowth semiconductor layer 34, selective epitaxy is recommended in which no polysilicon or amorphous silicon is formed on the top surface of the patterned mask 24 'outside the opening 26. In order to eliminate facet formation during epitaxy, in some embodiments, this semiconductor layer 34 can be grown higher than the patterned mask 24 ′, which is then patterned mask. Polish to a height of 24 '.

  In other embodiments, the regrowth semiconductor material 34 may be recessed at this point of the present invention using a time etching process such as timed RIE (timed RIE). it can. One or more semiconductor layers can be formed directly on the top surface of the recessed surface. The formed semiconductor layers should each have the same crystal orientation as the first semiconductor layer 12.

  In order to realize a coplanar surface, it may be necessary to etch back the semiconductor layer 34 to the same height as the second semiconductor layer 16. This etching step can be performed by dry etching, wet etching or by oxidizing the silicon and then stripping the oxide film.

  Here, the mask 24 'patterned from the structure is removed using a conventional stripping method that can selectively remove the mask 24' patterned from the structure. The structure formed after removing this patterned mask 24 'is shown, for example, in FIG. In this structure, the second semiconductor device surface, ie, the second semiconductor layer 16, is substantially coplanar with the first semiconductor device surface, ie, the regrowth semiconductor material 34.

  After providing the structure shown in FIG. 9, standard CMOS processing can be performed including, for example, device isolation formation, well region formation, and gate region formation. In particular, after providing the structure shown in FIG. 9, an isolation region 36 (see FIG. 10) such as a shallow trench isolation region is typically formed, whereby the second semiconductor active device region 28 to the first semiconductor active device. The region 30 is separated.

  This isolation region 36 is formed using processing steps well known to those skilled in the art including, for example, trench definition and etching; optional trench lining with a diffusion barrier; and filling the trench with a trench dielectric such as oxide. To do. After trench filling, the structure can be planarized and an optional densification process step can be performed to densify the trench dielectric.

  The well regions are then formed within the exposed semiconductor device layer, ie, layer 16 or regrowth semiconductor material 34, both using ion implantation and annealing well known to those skilled in the art. This well region is represented by reference numeral 38 in FIG. This well region can be an n-type well region or a p-type well region, depending on the type of semiconductor device formed on the respective semiconductor layer (ie, second semiconductor layer 16 and regrown semiconductor material 34). For example, when the semiconductor device is a pFET, the well region 38 is an n-type well, and when the semiconductor device is an nFET, the well region 38 is a p-type well. The doping of each well is performed with various implantation steps, in which an implantation mask is formed over the areas not intended for implantation of a particular dopant. The well region 38 serves as a body contact in the present application. The depth of the well region 38 can vary depending on the implantation and annealing conditions and the type of dopant used.

  After the well formation, semiconductor devices, i.e., pFETs and nFETs, are formed on the exposed semiconductor layer, i.e., the second semiconductor layer 16 and on the regrown semiconductor material 34. Specifically, the second semiconductor device 50 is formed on a portion of the second semiconductor layer 16 and the first semiconductor device 52 is formed on the regrown semiconductor material 34. Although illustrated as having only a single semiconductor device within each device region, the present invention also contemplates the formation of a plurality of each type of device within a particular device region. According to the present invention, the first semiconductor device 52 may be a pFET or an nFET, the first semiconductor device being different from the second semiconductor device, and a particular device being formed on a crystal orientation that enhances device performance. Under conditions, the second semiconductor device 50 may be a pFET or an nFET.

  The pFET and nFET are formed with standard CMOS processing steps well known to those skilled in the art. Each FET comprises a gate dielectric, a gate conductor, an optional hard mask on the gate conductor, a spacer on at least the sidewall of the gate conductor, and a source / drain diffusion region. Note that the pFET is formed on a semiconductor material having a (110) or (111) orientation and the nFET is formed on a semiconductor surface having a (100) or (111) orientation. The resulting structure with a bulk FET is shown in FIG.

  In the present invention, there are several methods for designing bulk nFETs and pFETs on hybrid substrates having different crystal orientations. Here, the separation of the device and the well by the introduction of the interface 14 will be mainly discussed. In the following example, the pFET is on (110) silicon and the nFET is on (100) silicon with a conventional p-type substrate. The STI depth should be designed to have conventional isolation regions between nFET / pFET, nFET / nFET, and pFET / pFET.

  FIGS. 11 and 12 show that the conductive (ie, bonding) interface 14 can be designed to be under the isolation region 36 and well 38. If (110) Si16 is on the top surface of (100) Si12 (as shown in FIG. 11), the nFET in the p-well is on the (100) epi layer 34 and the pFET in the n-well is (110) Si16 Is on the top. In order to avoid well-well leakage, the interface 14 should be lower than the n-well. Specifically, the interface should be outside the depletion region of the well pn junction. The width of the pn junction depletion layer is inversely proportional to its doping level. A p-well-p-well connection is provided from the epi layer through the first semiconductor from the epi layer, through the bonding interface / epitaxy interface, or both. Devices in the same well can share the same well contact (to avoid floating bodies). In this particular scenario, the conductivity of the bonding interface is not critical, i.e. the bonding interface may be an insulator and the bonding may be Si-Si, Si-oxide, or oxide-oxide bonding. It's okay. However, a conductive bonding interface is preferred.

  In the embodiments shown in FIGS. 11-16, an SOI layer with a thickness of about 200 nm to about 2 μm and a thin BOX with a thickness of less than about 10 nm can be used, which can be conductive or insulating. . In yet another possible method, the SOI substrate comprises an SOI layer with a thickness of about 200 nm to about 2 μm and a thick BOX with a thickness of about 10 nm or more. In this embodiment, the BOX is insulative and the hybrid structure is formed by bonding at least one semiconductor wafer including an insulating layer to another semiconductor wafer that may or may not include an insulating layer. The In yet another embodiment, using a bonded substrate comprising a top silicon layer about 100 nm to about 200 nm thick and a conductive thin BOX less than about 10 nm thick resulting from direct Si-Si bonding. You can also.

  (As shown in FIG. 12) When (100) Si16 is on top of (110) Si12, the pFET in the n-well is on (110) epi layer 34 and the nFET in the p-well is on (100) Si16 It is in. In order to avoid well-well leakage, the bonding interface must be away from the well pn junction, so the thickness of the top Si 16 is comparable to that in FIG. In this case, the p-well-p-well connection crosses the bonding interface and / or the epitaxy interface. The conductivity of the bonding interface is not critical, that is, the bonding interface may be an insulator, but a bonding interface with good conductivity is preferred by using the Si-Si direct bonding described above.

  As shown in FIGS. 13 and 14, this bonding interface can be applied to the interior of the well, the isolation region, as long as the spacer formed before epitaxy provides a good isolation region that acts as an additional isolation region between the wells at the end of the process. 36 can be designed below. When (100) handling wafer 12 has (110) Si16 on the top surface of (100) handling wafer 12 (as shown in FIG. 13), the pFET in the n-well is on (110) Si16 and the nFET in the p-well is (100) epi. It is on Si34. The bonding interface may be above the well junction as long as it is sufficiently far from the depletion region of the well pn junction. The spacer (and stack etch) must still be below the bonding interface to pull the well pn junction away from the bonding interface. In this case, the p-well-p-well connection is made from the epi-Si through the handling wafer. However, devices in the same n-well are connected through just below the STI, with or without crossing the bonding interface. In order to ensure that all pFETs in the same n-well have good body contacts, it is preferred that the bonding interface has good conductivity. When (110) Si16 is on the top surface of (110) Si12 (as shown in FIG. 14), the bonding interface is inside the p-well. The only requirement is that the spacer (and stack etch) must be below the bonding interface in order to pull the well pn junction away from the bonding interface. In this scenario, the p-well-p-well connection must cross the bonding interface. Furthermore, good conductivity at the bonding interface is required to ensure good body contact for all nFETs in the same p-well.

  FIGS. 15 and 16 show how this bonding interface can be designed on top of the STI. When (110) Si16 is on the top surface of the (110) handling wafer 12 (as shown in FIG. 15), both the bonding interface and the well junction are below the pFET. In order to avoid S / D leakage, this bonding interface must be below the depth of the source / drain junction depletion. In order to avoid well-to-well leakage, this bonding interface must also be outside the depletion region of the well junction. Furthermore, the STI must be deep enough to pull the well junction away from the bonding interface. In order to avoid the pFET having a floating body, it is necessary that this bonding interface provide good conductivity.

  When (110) handling wafer 12 has (100) Si (as shown in FIG. 16), it is the same as in FIG. In order to avoid S / D leakage, this bonding interface must be below the depletion depth of the source / drain junction. However, since the bonding interface is in the p-well, the STI depth is the only requirement for well isolation in order to avoid well-well leakage. In order to avoid the nFET having a floating body and obtain a p-well-p-well connection, it is necessary that this bonding interface provide good conductivity.

  The bulk CMOS on the hybrid substrate described above can be combined with a strained Si process (see FIGS. 17 to 36). It is known that nFETs on (100) strained Si layers have higher performance than on unstrained (100) Si substrates. It is also known that pFETs on (110) strained Si layers have higher performance than those on unstrained (110) Si substrates. The strained Si layer can be realized by growing a relaxed SiGe buffer on the upper or lower surface of Si.

  The strained Si process contemplated by the present invention will be described with respect to the specific embodiment shown in FIGS. Unless otherwise specified, the processing steps and materials used above are also used in strained Si embodiments.

  17-20 illustrate an embodiment for providing a strained SiMOSFET device. FIG. 17 shows a hybrid structure 10 including the first semiconductor layer 12, the interface 14, and the second semiconductor layer 16 formed as described above.

  Next, as shown in FIG. 18, a relaxation buffer layer 70 such as SiGe having the same crystal orientation as that of the second semiconductor layer 16 is formed by epitaxy. After forming the relaxation buffer layer 70, a strained semiconductor layer 72 such as strained Si is deposited on the relaxation buffer layer 70. In this embodiment of the invention, the strain / relaxation layer has the same crystal orientation as the second semiconductor layer 16.

  A mask layer (hereinafter referred to as a “pad stack”) comprising pad oxide film 74 and pad nitride film 76 is then formed by deposition, and the pad stack is lithographically and exposed so that a portion of second semiconductor layer 16 is exposed. Etching. Next, the exposed portion of the second semiconductor layer 16 is etched and stopped on the first semiconductor layer 12 or inside the first semiconductor layer 12. An optional spacer 32 is then formed on each sidewall within the opening provided by the above etching step. The resulting structure is shown, for example, in FIG.

  FIG. 20 shows the structure after the semiconductor material 34 is regrown and planarized from the exposed surface of the first semiconductor layer 12. The pad oxide film 74 and the pad nitride film 76 may be removed here, and a CMOS device as described above may be formed on the strained Si layer 72 and the regrown semiconductor material 34.

  21 to 24 show another embodiment that can be used in the present invention. In this embodiment, the relaxation buffer layer 70 and the strained semiconductor layer 72 are formed on the exposed surface in the opening of the first semiconductor layer 12. In this example, the relaxation buffer layer / strained semiconductor stack has the same crystal orientation as the first semiconductor layer 12. The processing steps used in this embodiment are similar to those described above with respect to FIGS. 17-20 except for the location of the relaxation buffer layer and strained semiconductor layer.

  25 to 28 show another embodiment of the present invention. In this embodiment, a semiconductor wafer as shown in FIG. 25 is used as one of the wafers for direct bonding. Specifically, the wafer shown in FIG. 25 includes a relaxed semiconductor layer 12 ′ such as SiGe formed on the handling wafer 80. The relaxed semiconductor layer 12 ′ has the same characteristics as the first semiconductor layer 12 described above. Next, the second semiconductor layer 16 having a crystal orientation different from that of the relaxed semiconductor layer 12 'is bonded to the wafer shown in FIG. 25 by using the above-described direct bonding technique, resulting in the structure shown in FIG.

  A patterned pad stack comprising pad oxide film 74 and pad nitride film 76 is then formed as described above, an opening exposing a portion of relaxation buffer layer 12 'is provided, and optional spacer 32 is formed. The semiconductor material 34 is then grown to yield the planarized structure shown in FIG.

  The semiconductor material 34 is then recessed by using time-controlled etching. A strained semiconductor layer 72 is then formed on the recessed semiconductor material 34, after which the pad stack is removed, resulting in the structure shown in FIG. Next, a CMOS device as described above is formed on the second semiconductor layer 16 and the strained Si layer 72. It should be noted that the strained Si layer 72 has the same crystal orientation as the relaxation buffer layer 12 ′ different from the second semiconductor layer 16.

  29 to 32 show another embodiment of the present invention. In this embodiment, the first semiconductor layer 12 is directly bonded to the second semiconductor layer 16. Then (as described above), relaxed semiconductor 70 and strained semiconductor layer 72 are formed on second semiconductor layer 16 resulting in the structure shown in FIG.

  Next, a pad stack including a pad oxide film 74 and a pad nitride film 76 is formed on the strained semiconductor layer and then patterned. An opening extending down to the first semiconductor layer 12 is provided, and then an optional spacer 32 is formed in the opening. After forming the optional spacer 32, a semiconductor material 34 including a relaxed SiGe layer is formed and planarized, resulting in, for example, the structure shown in FIG. A portion of the relaxed SiGe layer 34 is recessed using a time-controlled reactive ion etching method, after which a strained semiconductor layer 72 'is provided to remove the pad stack from the structure, resulting in the structure shown in FIG. In this case, the strained semiconductor layer 72 has a crystal orientation different from that of the strained semiconductor layer 72 '. As described above, a CMOS device can be formed on each strained layer.

  33 and 34 show another embodiment of the present invention. In this embodiment, the relaxed semiconductor layer 12 ′ is formed on the handling wafer 80 (see FIG. 33), and this semiconductor layer is then bonded directly to the second semiconductor layer 16. Next, a relaxation buffer layer 70 and a strained semiconductor layer 72 having the same crystal orientation as the second semiconductor layer 16 are formed, and a pad stack including a pad oxide film 74 and a pad nitride film 76 is provided. After the lithography and etching steps that expose the surface portion of the relaxed semiconductor layer 12 ', an optional spacer 32 is formed, the relaxed semiconductor layer 34 is epitaxially grown on the relaxed semiconductor layer 12', and then the structure is planarized. . FIG. 35 shows the structure obtained.

  As described above, the regrowth semiconductor layer 34 is recessed, and a strained Si layer 72 'is formed on the recessed surface. The structure is then planarized resulting in the structure shown in FIG. Next, as described above, a CMOS device is formed on the strained semiconductor layer 72 and the strained semiconductor layer 72 '. According to the present invention, each strained semiconductor layer has a different crystal orientation.

  While the invention has been particularly shown and described with respect to preferred embodiments thereof, those skilled in the art will recognize that these and other variations can be made in form and detail without departing from the scope and spirit of the invention. .

It is a pictorial diagram (sectional view) showing the structure of the prior art in which a MOSFET is provided on an SOI substrate and a floating body exists inside. FIG. 2 is a pictorial diagram (cross-sectional view) showing a structure of a prior art including a MOSFET on a bulk substrate and having a well contact inside. It is a pictorial view (sectional drawing) which shows the hybrid board | substrate of this invention which has a different surface orientation obtained by the semiconductor-semiconductor direct bonding. FIG. 4 is a pictorial diagram (cross-sectional view) showing one method of layer transfer for realizing a thin upper surface layer of a semiconductor layer of the hybrid substrate shown in FIG. 3. FIG. 4 is a pictorial diagram (cross-sectional view) showing one method of layer transfer for realizing a thin upper surface layer of a semiconductor layer of the hybrid substrate shown in FIG. 3. FIG. 4 is a pictorial diagram (sectional view) showing one basic processing step used by the present invention using the hybrid substrate of FIG. 3 as a starting substrate. FIG. 4 is a pictorial diagram (sectional view) showing one basic processing step used by the present invention using the hybrid substrate of FIG. 3 as a starting substrate. FIG. 4 is a pictorial diagram (sectional view) showing one basic processing step used by the present invention using the hybrid substrate of FIG. 3 as a starting substrate. FIG. 4 is a pictorial diagram (sectional view) showing one basic processing step used by the present invention using the hybrid substrate of FIG. 3 as a starting substrate. FIG. 4 is a pictorial diagram (sectional view) showing one basic processing step used by the present invention using the hybrid substrate of FIG. 3 as a starting substrate. FIG. 2 is a pictorial diagram (cross-sectional view) showing one strategy for designing several bulk CMOS devices on a hybrid substrate with different plane orientations that can be used in the present invention. FIG. 2 is a pictorial diagram (cross-sectional view) showing one strategy for designing several bulk CMOS devices on a hybrid substrate with different plane orientations that can be used in the present invention. FIG. 2 is a pictorial diagram (cross-sectional view) showing one strategy for designing several bulk CMOS devices on a hybrid substrate with different plane orientations that can be used in the present invention. FIG. 2 is a pictorial diagram (cross-sectional view) showing one strategy for designing several bulk CMOS devices on a hybrid substrate with different plane orientations that can be used in the present invention. FIG. 2 is a pictorial diagram (cross-sectional view) showing one strategy for designing several bulk CMOS devices on a hybrid substrate with different plane orientations that can be used in the present invention. FIG. 2 is a pictorial diagram (cross-sectional view) showing one strategy for designing several bulk CMOS devices on a hybrid substrate with different plane orientations that can be used in the present invention. It is a pictorial diagram (sectional view) showing one technique for providing a strained SiMOSFET of the present invention. It is a pictorial diagram (sectional view) showing one technique for providing a strained SiMOSFET of the present invention. It is a pictorial diagram (sectional view) showing one technique for providing a strained SiMOSFET of the present invention. It is a pictorial diagram (sectional view) showing one technique for providing a strained SiMOSFET of the present invention. It is a pictorial figure (sectional drawing) which shows another technique which provides the distortion | strained SiMOSFET of this invention. It is a pictorial figure (sectional view) which shows the said another method which provides the distortion | strained SiMOSFET of this invention. It is a pictorial figure (sectional view) which shows the said another method which provides the distortion | strained SiMOSFET of this invention. It is a pictorial figure (sectional view) which shows the said another method which provides the distortion | strained SiMOSFET of this invention. It is a pictorial figure (sectional drawing) which shows the other method which provides the distortion | strained SiMOSFET of this invention. It is a pictorial diagram (sectional view) showing the other method for providing the strained SiMOSFET of the present invention. It is a pictorial diagram (sectional view) showing the other method for providing the strained SiMOSFET of the present invention. It is a pictorial diagram (sectional view) showing the other method for providing the strained SiMOSFET of the present invention. FIG. 10 is a pictorial diagram (cross-sectional view) showing yet another technique for providing strained Si FETs and pFETs. FIG. 6 is a pictorial diagram (cross-sectional view) showing still another method for providing strained Si FETs and pFETs. FIG. 6 is a pictorial diagram (cross-sectional view) showing still another method for providing strained Si FETs and pFETs. FIG. 6 is a pictorial diagram (cross-sectional view) showing still another method for providing strained Si FETs and pFETs. FIG. 10 is a pictorial diagram (cross-sectional view) showing yet another technique for providing strained Si FETs and pFETs. FIG. 6 is a pictorial diagram (cross-sectional view) showing still another method for providing strained Si FETs and pFETs. FIG. 6 is a pictorial diagram (cross-sectional view) showing still another method for providing strained Si FETs and pFETs. FIG. 6 is a pictorial diagram (cross-sectional view) showing still another method for providing strained Si FETs and pFETs.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Hybrid substrate 12 1st (lower side) semiconductor (Si) layer 12 'Relaxation semiconductor layer 14 Bonding interface 16 2nd (upper side) semiconductor (Si) layer 18 Etching stop layer 20 Handling wafer 22 Ion implantation layer 24 Hard mask Layer (pad stack)
24 'patterned mask 26 opening 28 second (semiconductor active) device region 30 first (semiconductor active) device region 32 optional spacer 34 semiconductor material 36 isolation region 38 well region 50 second semiconductor device 52 first semiconductor Device 70 Relaxation buffer layer 72 Strained semiconductor layer 72 'Strained semiconductor layer 74 Pad oxide film 76 Pad nitride film 80 Handling wafer

Claims (11)

A first semiconductor layer having one of the (100) plane orientation and the (110) plane orientation has the other plane orientation of the (100) plane orientation and the (110) plane orientation. Bonding the two semiconductor layers;
Forming a relaxation buffer layer having the other plane orientation on the second semiconductor layer;
Forming a strained semiconductor layer having the other plane orientation on the relaxation buffer layer;
Forming a mask layer having a mask opening on the strained semiconductor layer;
Forming an opening exposing the first semiconductor layer by etching the strained semiconductor layer, the relaxation buffer layer, and the second semiconductor layer exposed by the mask opening;
Forming a spacer on a side wall of the opening;
Growing and planarizing a relaxed semiconductor material having the one plane orientation on the first semiconductor layer so as to fill the opening;
Forming an upper portion of the relaxed semiconductor material, and forming a strained semiconductor material having the one surface orientation in the recessed portion;
Removing the mask layer to expose the strained semiconductor layer;
Forming a CMOS device on the strained semiconductor material and the strained semiconductor layer.   The manufacturing method according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are Si, and the relaxed semiconductor material is SiGe.   The manufacturing method according to claim 1, wherein the relaxation buffer layer is SiGe and the strained semiconductor layer is Si.   The manufacturing method according to claim 1, wherein the strained semiconductor material is Si.   The manufacturing method according to claim 1, wherein the mask layer includes an oxide film formed on the strained semiconductor layer and a nitride film formed on the oxide film.   The manufacturing method according to claim 1, wherein the spacer is selected from the group consisting of an oxide film, a nitride film, an oxynitride film, and a combination thereof. Provided on the first semiconductor layer having one of the (100) plane orientation and the (110) plane orientation, and the other plane orientation of the (100) plane orientation and the (110) plane orientation is A second semiconductor layer having,
A relaxation buffer layer provided on the second semiconductor layer and having the other plane orientation;
A strained semiconductor layer provided on the relaxation buffer layer and having the other plane orientation;
An opening provided in the strained semiconductor layer, the relaxation buffer layer, and the second semiconductor layer to expose the first semiconductor layer;
A spacer provided on a side wall of the opening;
A relaxed semiconductor material provided on the first semiconductor layer to fill the opening and having the one plane orientation;
A strained semiconductor material provided on the recessed portion of the upper portion of the relaxed semiconductor material and having the one surface orientation;
A structure comprising the strained semiconductor material and a CMOS device provided in the strained semiconductor layer.   8. The structure of claim 7, wherein the first semiconductor layer and the second semiconductor layer are Si, and the relaxed semiconductor material is SiGe.   The structure of claim 7, wherein the relaxation buffer layer is SiGe and the strained semiconductor layer is Si.   The structure of claim 7, wherein the strained semiconductor material is Si.   The structure of claim 7, wherein the spacer is selected from the group consisting of an oxide film, a nitride film, an oxynitride film, and combinations thereof.

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