CN102709252B - Method for improving read-out redundancy of static random access memory - Google Patents

Method for improving read-out redundancy of static random access memory Download PDF

Info

Publication number
CN102709252B
CN102709252B CN 201210158807 CN201210158807A CN102709252B CN 102709252 B CN102709252 B CN 102709252B CN 201210158807 CN201210158807 CN 201210158807 CN 201210158807 A CN201210158807 A CN 201210158807A CN 102709252 B CN102709252 B CN 102709252B
Authority
CN
Grant status
Grant
Patent type
Prior art keywords
substrate
channel
orientation
control tube
random access
Prior art date
Application number
CN 201210158807
Other languages
Chinese (zh)
Other versions
CN102709252A (en )
Inventor
俞柳江
Original Assignee
上海华力微电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Abstract

本发明公开了一种提高静态随机存储器读出冗余度的方法,其中,包括下列步骤:提供一具有混合取向的衬底,具有第一表面取向的第一衬底,具有第二表面取向的第二衬底和第三表面取向的第三衬底;在第一衬底上制作一NMOS晶体管,包括一第一沟道,第一沟道为具有第一晶向;在第二衬底上制作一PMOS晶体管,PMOS晶体管包括第二沟道,第二沟道具有第二晶向和第三衬底上制作一控制管,第三控制管包括一具有第三晶向的第三沟道;在PMOS晶体管与NMOS晶体管之间形成第一浅沟槽隔离结构,在所述PMOS晶体管和控制管之间制作第二浅沟槽隔离结构。 The present invention discloses a method for improving a static random memory reading redundancy, comprising the steps of: providing a substrate having a hybrid alignment, a first substrate having a first surface orientation, having a second surface orientation the third substrate and the second substrate of the third surface orientation; formed on a substrate, a first NMOS transistor comprising a first channel, the first channel having a first crystal orientation; on the second substrate making a PMOS transistor, a PMOS transistor including a second channel, the second channel having a second control tube produced a crystal orientation and the third substrate, comprising a third control tube having a third crystal orientation of the third channel; forming a first shallow trench isolation structure between the PMOS transistor and NMOS transistor, forming a second shallow trench isolation structure between the PMOS transistor and the control tube. 本发明降低了控制管器件的载流子迁移率,增大了控制管的等效电阻,提高了随机存储器读出冗余度。 The present invention reduces the control tube device carrier mobility increases the equivalent resistance of the control tube, to improve the read-out random access memory redundancy.

Description

一种提高静态随机存储器读出冗余度的方法 A method of reading out a static random access memory redundancy to improve

技术领域 FIELD

[0001] 本发明涉及微电子领域,尤其涉及一种提高静态随机存储器读出冗余度的方法。 [0001] The present invention relates to the field of microelectronics, in particular, it relates to a method of reading out a static random access memory redundancy increase.

背景技术 Background technique

[0002] 静态随机存储器(SRAM)作为半导体存储器中的一类重要产品,在计算机、通信、多媒体等高速数据交换系统中得到了广泛的应用。 [0002] The static random access memory (SRAM) as semiconductor memories important class of products, has been widely used in computer, communications, multimedia and other high speed data exchange system.

[0003] 如图1中所示,图1是一个90纳米以下的通常的SRAM单元的版图结构,包括有源区、多晶硅栅、和接触孔这三个层次。 [0003] As shown in FIG. 1, FIG. 1 is a 90 nm layout structure of a conventional SRAM cell comprising an active region, the polysilicon gate, and a contact hole three levels. 图中区域I所标示出来的为控制管(Pass Gate),该器件为一NMOS器件,区域21所标示出来的为下拉管(Pull Down M0S),该器件同样为一NMOS器件,区域22所标示出来的为上拉管(Pull Up M0S),该器件为一PMOS器件。 FIG region I is marked as control tube (Pass Gate), the device is an NMOS device, the marked region 21 of the pulldown transistor (Pull Down M0S), the device likewise an NMOS device, as indicated by region 22 out of the pullup transistor (Pull Up M0S), the device is a PMOS device.

[0004] 读出冗余度是衡量SRAM单元读出性能的一个重要参数,图2是一个SRAM器件在读取时的工作示意图,如图2所示,包括控制管1,下拉管21,上拉管22,假设第一节点31存储数据为高电位(即存储数据为“ I ”),而相应地,第二节点32存储数据为低电位(即存储数据为“0”),在读取动作前,位线41和位线42会被预充电到高电位,读取动作开始时,字线43打开,由于第一节点31存储的数据为高电位,所以位线41上的电压保持不变,而由于第二节点32存储的数据为低电位,位线42上的电压会被向下拉,通过感知位线41和位线42上的电压差来完成SRAM单元的读动作。 [0004] The read redundancy is an important parameter to measure the performance of the SRAM cell is read out, FIG 2 is a schematic view of a working device when reading the SRAM shown in Figure 2, includes a control tube 1, the pulldown transistor 21, the trombone 22, the stored data is assumed that the first node 31 to a high level (i.e., the stored data is "the I"), and accordingly, the data storage node 32 is low (i.e., the stored data is "0"), read before the operation, the bit line 41 and bit line 42 is precharged to a high potential, the read operation is started, the word line 43 is opened, since the data stored in the first node 31 is high, the voltage on the bit line 41 remains change, but since the data stored in the second node 32 is low, the voltage on the bit line 42 is pulled down by sensing the bit line 41 and bit line 42 the voltage difference between the read operation to complete the SRAM cell. 在读出过程中有一个必须保证的条件,就是不能改变SRAM单元中原先存储的数据。 A condition must be guaranteed in the read process, that they can not change the data previously stored in the SRAM cell. 当字线43打开后,位线42上的电压被下拉的同时,第二节点32的电位也会同时被拉升到一个中间电位,即不再保持“0”,中间电位的大小是由下拉管和控制管的比例所决定的,即可理解为下拉管和控制管的等效电阻的比例所决定的。 When the word line 43 is opened, while the voltage on bit line 42 is pulled down, the potential of the second node 32 will be pulled simultaneously raised to an intermediate potential, i.e., does not remain "0", the size of the intermediate potential by the pull-down proportional control tube and the tube of the decision can be understood as the ratio of the pull-down pipe and the equivalent resistance of the control tube of the decision. 为了不改变SRAM单元中原先存储的数据,第二节点32的中间电位被要求必须小于一定数值,即下拉管和控制管的等效电阻的比例必须小于一定值。 In order not to change the data previously stored in the SRAM cell, the potential of the intermediate node 32 is required to be less than a certain value, i.e. the ratio of the pull-down pipe and the equivalent resistance of control tubes must be less than a certain value. 这就是SRAM读出动作时读出冗余度的要求。 This is read out when required redundancy SRAM read operation. 增大控制管的等效电阻,可以降低第二节点32的中间电位,从而增加SRAM单元的读出冗余度。 Increasing the equivalent resistance of the control tube, can reduce the potential of the second intermediate point 32, thereby increasing the redundancy SRAM cell read.

[0005] 随着工艺代的进步,特别是在65纳米以下工艺代中,会采用混合取向技术(Hybrid Orientat1n Technology)制备CMOS器件。 [0005] As the process generation advances, particularly in the 65 nm generation process, we will use hybrid orientation technology (Hybrid Orientat1n Technology) to prepare a CMOS device. 这是由于娃能带的各向异性,当采用不同衬底晶向和沟道取向时,可以得到不同载流子迁移率的原因。 This is the reason because the anisotropy energy with the baby, when different wafers in alignment and the channel, can be a different carrier mobility. 对于NMOS器件,采用 For NMOS devices, the use of

(100)衬底〈110〉沟道取向,可以获得最大的电子迁移率,而对于PMOS器件,采用(110)衬底〈110>沟道取向,则可以获得最大的空穴迁移率。 (100) substrate <110> orientation channel, obtain the maximum electron mobility, while for a PMOS device, using the (110) substrate <110> orientation of the channel, can be obtained the maximum hole mobility. 在采用混合取向技术制备CMOS器件时,通过外延技术,可以将两种衬底集成在一起。 When using techniques for preparing hybrid orientation CMOS devices by epitaxial technique, two kinds of the substrate may be integrated together. 使得在同一硅片上,对NMOS器件采用(100)衬底〈110〉沟道取向,而对PMOS器件采用(110)衬底〈110〉沟道取向,以同时获得最大的电子和空穴迁移率。 So that on the same wafer, use of NMOS devices (100) substrate <110> orientation of the channel, while the PMOS device using (110) substrate <110> orientation of the channel, in order to obtain the maximum simultaneous electron and hole mobilities rate. 在通常的工艺中NMOS器件、PMOS器件以及控制管在采用混合取向技术制备后,NMOS器件控制管(因为其同样是NMOS器件)均采用(100)衬底〈110〉沟道取向,而PMOS器件采用(110)衬底〈110〉沟道取向,电子和空穴的迁移率同时达到最大。 In a typical process of the NMOS device, a PMOS device and a control tube was prepared in the hybrid orientation technology employed, the control tube NMOS device (because it is also an NMOS device) are used (100) substrate <110> orientation of the channel, while the PMOS device using (110) substrate <110> orientation of the channel, the mobility of electrons and holes simultaneously maximized. 特别地,控制管的电子迁移率也达到最大,因此等效电阻较小。 In particular, the electron mobility control tube has reached the maximum, so the equivalent resistance is small.

发明内容 SUMMARY

[0006] 针对上述存在的问题,本发明的目的是提供提高静态随机存储器读出冗余度的方法。 [0006] For the above-described problems, an object of the present invention to provide a method of reading out a static random access memory redundancy increase. 本发明在静态随机存储器制备工艺过程中,降低了控制管器件的载流子迁移率,增大了控制管的等效电阻,提高了随机存储器读出冗余度。 In the preparation process of the present invention is a static random access memory, reducing the carrier mobility of the device control tube, increases the equivalent resistance of the control tube, to improve the read-out random access memory redundancy.

[0007] 本发明的目的是通过下述技术方案实现的: [0007] The object of the present invention is achieved by the following technical scheme:

[0008] 一种提高静态随机存储器读出冗余度的方法,其中,包括下列步骤: [0008] A method of reading out a static random access memory redundancy to improve, comprising the steps of:

[0009] 提供一具有混合取向的衬底,衬底包括具有第一表面取向的第一衬底,具有第二表面取向的第二衬底和第三表面取向的第三衬底; The third substrate and the second substrate of the third surface alignment [0009] providing a substrate having a hybrid alignment, comprising a substrate having a first surface orientation of the first substrate, having a second surface orientation;

[0010] 在所述第一衬底上制作一NMOS晶体管,所述NMOS晶体管中包括一第一沟道,所述第一沟道为具有第一晶向;在所述第二衬底上制作一PMOS晶体管,所述PMOS晶体管包括第二沟道,所述第二沟道具有第二晶向和第三衬底上制作一控制管,所述第三控制管包括一具有第三晶向的第三沟道; [0010] formed on a substrate of said first NMOS transistor, the NMOS transistor comprising a first channel, the first channel having a first crystal orientation; formed on said second substrate a PMOS transistor, said PMOS transistor comprises a second channel, the second channel having a second crystal orientation and a production on a third substrate control tube, comprising the third control tube having a third crystal orientation The third channel;

[0011] 在所述PMOS晶体管与所述NMOS晶体管之间形成第一浅沟槽隔离结构,在所述PMOS晶体管和所述控制管之间制作第二浅沟槽隔离结构。 [0011] forming a first shallow trench isolation structure between the PMOS transistor and the NMOS transistor, forming a second shallow trench isolation structure between said PMOS transistor and said control tube.

[0012] 上述的提高静态随机存储器读出冗余度的方法,其中,所述控制管为一PMOS器件。 [0012] The improved static random access memory redundancy readout method, wherein the control tube is a PMOS device.

[0013] 上述的提高静态随机存储器读出冗余度的方法,其中,所述第一衬底的第一表面取向是(100)平面,所述第一晶向是〈110〉晶向。 [0013] The improved static random access memory redundancy readout method, wherein the first orientation of the first surface of the substrate is (100) plane, the first crystal orientation is the <110> crystal orientation.

[0014] 上述的提高静态随机存储器读出冗余度的方法,其中,所述第二衬底的第二表面取向是(110)平面,所述第二晶向是〈110〉晶向。 [0014] The improved static random access memory redundancy readout method, wherein said second substrate second surface orientation is (110) plane, the second crystal orientation is the <110> crystal orientation.

[0015] 上述的提高静态随机存储器读出冗余度的方法,其中,所述第三衬底的第三表面取向是(110)平面,所述第二晶向是〈110〉晶向。 [0015] The improved static random access memory redundancy readout method, wherein the third surface of the third substrate orientation is (110) plane, the second crystal orientation is the <110> crystal orientation.

[0016] 与已有技术相比,本发明的有益效果在于: [0016] Compared with the prior art, the beneficial effects of the present invention:

[0017] 本发明通过逻辑运算,当采取混合取向技术制备CMOS器件时,使得控制管与PMOS器件同样使用(110)衬底〈110〉沟道取向,从而降低了控制管器件的载流子迁移率,增大了控制管的等效电阻,在读取过程中,降低了节点的电位,从而提高了随机存储器的读出冗余度。 [0017] The present invention is by logical operation, when taking techniques for preparing hybrid orientation CMOS devices, so that the control tube and PMOS devices use the same (110) substrate <110> orientation of the channel, thereby reducing the carrier mobility of the device control tube ratio, increases the equivalent resistance of the control tube, during reading, reducing the potential of the node, thereby increasing the readout random access memory redundancy.

附图说明 BRIEF DESCRIPTION

[0018] 图1是一种静态随机存储器单元的版图结构示意图; [0018] FIG. 1 is a schematic layout structure of a static random access memory cells;

[0019] 图2是一种静态随机存储器的读取工作示意图; [0019] FIG. 2 is a schematic diagram of a read operation of a static random access memory;

[0020] 图3是本发明的一种提高静态随机存储器读出冗余度的方法流程图。 [0020] FIG. 3 is a readout method of the present invention is a static random access memory redundancy flowchart improved.

具体实施方式 Detailed ways

[0021] 下面结合原理图和具体操作实施例对本发明作进一步说明。 [0021] The following embodiments of the present invention will be further described in conjunction with the schematic and specific operation.

[0022] 本发明的提高静态随机存储器读出冗余度的方法,具体包括以下步骤: [0022] Static random access memory according to the present invention is to improve the redundancy of readout method, includes the following steps:

[0023] S1:提供一具有混合取向的衬底,衬底包括具有第一表面取向的第一衬底,具有第二表面取向的第二衬底和第三表面取向的第三衬底; [0023] S1: providing a substrate having a hybrid alignment, the substrate comprising a first substrate having a first surface orientation, a second orientation surface of the third substrate and the third substrate second surface orientation;

[0024] 实施中,该第一衬底为(100)平面,第二衬底为(110)平面,第三衬底为(110)平面。 [0024] In embodiments, the first substrate is a (100) plane, the second substrate is a (110) plane, a third substrate is a (110) plane.

[0025] S2:在第一衬底上制作一NMOS晶体管,NMOS晶体管中包括一第一沟道,第一沟道为具有第一晶向〈110〉;在第二衬底上制作一PMOS晶体管,PMOS晶体管包括第二沟道,第二沟道具有第二晶向〈110〉和在第三衬底上制作一控制管,第三控制管包括一具有第三晶向〈110〉的第三沟道; [0025] S2: making an NMOS transistor on a first substrate, a first NMOS transistor comprising a channel, the first channel having a first crystal orientation <110>; making a PMOS transistor on a second substrate the <110> and control a production tube in the third substrate includes a third control tube having a third crystal orientation <110> third, the PMOS transistor comprises a second channel, the second channel having a second crystal channel;

[0026] S3:进行浅槽隔离工艺,在PMOS晶体管与NMOS晶体管之间形成第一浅沟槽隔离结构,在PMOS晶体管和控制管之间制作第二浅沟槽隔离结构。 [0026] S3: shallow trench isolation process, a first shallow trench isolation structure is formed between the PMOS transistor and NMOS transistor, forming a second shallow trench isolation structure between the PMOS transistor and the control tube.

[0027] 以上对本发明的具体实施例进行了详细描述,但本发明并不限制于以上描述的具体实施例,其只是作为范例。 [0027] The foregoing specific embodiments of the present invention has been described in detail, but the present invention is not limited to the specific embodiments described above, only as examples thereof. 对于本领域技术人员而言,任何等同修改和替代也都在本发明的范畴之中。 To those skilled in the art, any equivalent modifications and alternatives are also within the scope of the invention. 因此,在不脱离本发明的精神和范围下所作出的均等变换和修改,都应涵盖在本发明的范围内。 Accordingly, equalization changes and modifications without departing from the spirit and scope of the present invention made, shall fall within the scope of the present invention.

Claims (3)

  1. 1.一种提高静态随机存储器读出冗余度的方法,其特征在于,包括下列步骤: 提供一具有混合取向的衬底,所述衬底包括具有第一表面取向的第一衬底,具有第二表面取向的第二衬底和第三表面取向的第三衬底; 在所述第一衬底上制作一NMOS晶体管,所述NMOS晶体管中包括一第一沟道,所述第一沟道为具有第一晶向;在所述第二衬底上制作一PMOS晶体管,所述PMOS晶体管包括第二沟道,所述第二沟道具有第二晶向和第三衬底上制作一控制管,所述控制管包括一具有第三晶向的第三沟道; 在所述PMOS晶体管与所述NMOS晶体管之间形成第一浅沟槽隔离结构,在所述PMOS晶体管和所述控制管之间制作第二浅沟槽隔离结构; 所述控制管与所述PMOS器件使用同样(I 10)衬底〈110〉沟道取向。 1. A method of reading out a static random access memory redundancy increase, characterized by comprising the steps of: providing a substrate having a hybrid alignment, the substrate comprising a first substrate having a first surface orientation, having the third substrate and the second substrate of the third surface orientation of the second surface orientation; making an NMOS transistor on the first substrate, the NMOS transistor comprising a first channel, said first trench channel having a first crystal orientation; making a PMOS transistor on the second substrate, the PMOS transistor comprises a second channel, the second channel having a second crystal orientation produced on the substrate and a third control tube, the control tube comprises a third channel having a third crystal orientation; forming a first shallow trench isolation structure between the PMOS transistor and the NMOS transistor, the PMOS transistor and the control forming a second shallow trench isolation structure between the tubes; the control tube and the PMOS device using the same (I 10) of the substrate <110> orientation channel.
  2. 2.如权利要求1所述的提高静态随机存储器读出冗余度的方法,其特征在于,所述控制管为一PMOS器件。 2. The improved static random access memory according to claim 1 redundancy readout method, characterized in that the control tube is a PMOS device.
  3. 3.如权利要求1所述的提高静态随机存储器读出冗余度的方法,其特征在于,所述第一衬底的第一表面取向是(100)平面,所述第一晶向是〈110〉晶向。 3. The improved static random access memory according to claim 1 redundancy readout method, wherein said first substrate first surface orientation is (100) plane, the first crystal orientation is < 110> crystal orientation.
CN 201210158807 2012-05-22 2012-05-22 Method for improving read-out redundancy of static random access memory CN102709252B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201210158807 CN102709252B (en) 2012-05-22 2012-05-22 Method for improving read-out redundancy of static random access memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201210158807 CN102709252B (en) 2012-05-22 2012-05-22 Method for improving read-out redundancy of static random access memory

Publications (2)

Publication Number Publication Date
CN102709252A true CN102709252A (en) 2012-10-03
CN102709252B true CN102709252B (en) 2014-11-05

Family

ID=46901911

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201210158807 CN102709252B (en) 2012-05-22 2012-05-22 Method for improving read-out redundancy of static random access memory

Country Status (1)

Country Link
CN (1) CN102709252B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579245A (en) * 2013-10-18 2014-02-12 上海华力微电子有限公司 Static random access memory in hybrid orientation technology and method for improving write margin
CN106158865A (en) * 2015-04-03 2016-11-23 中芯国际集成电路制造(上海)有限公司 SRAM device and electronic device thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958328A (en) * 2009-07-16 2011-01-26 中芯国际集成电路制造(上海)有限公司 CMOS (Complementary Metal Oxide Semiconductor) device and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100361302C (en) * 2003-10-29 2008-01-09 国际商业机器公司 CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
US7405436B2 (en) * 2005-01-05 2008-07-29 International Business Machines Corporation Stressed field effect transistors on hybrid orientation substrate
US7605447B2 (en) * 2005-09-22 2009-10-20 International Business Machines Corporation Highly manufacturable SRAM cells in substrates with hybrid crystal orientation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958328A (en) * 2009-07-16 2011-01-26 中芯国际集成电路制造(上海)有限公司 CMOS (Complementary Metal Oxide Semiconductor) device and manufacturing method thereof

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Akinobu Teramoto,et al.Very High Carrier Mobility for High-Performance CMOS on a Si(110) Surface.《IEEE TRANSACTIONS ON ELECTRON DEVICES》.2007,第54卷(第6期), *
Rihito Kuroda, et al.Impact of Channel Direction Dependent Low Field Hole Mobility on (100) Orientation Silicon Surface.《Janpaese Journal of Applied Physics》.2011,第50卷 *

Also Published As

Publication number Publication date Type
CN102709252A (en) 2012-10-03 application

Similar Documents

Publication Publication Date Title
Chang et al. An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches
US6424016B1 (en) SOI DRAM having P-doped polysilicon gate for a memory pass transistor
US20130258759A1 (en) Methods and Apparatus for SRAM Cell Structure
US20130181297A1 (en) SRAM Cells and Arrays
US20090224321A1 (en) Semiconductor device and method of manufacturing semiconductor device
US20130292777A1 (en) Structure for FinFETs
US20130154027A1 (en) Memory Cell
US20110299327A1 (en) Four-transistor and five-transistor bjt-cmos asymmetric sram cells
US8294212B2 (en) Methods and apparatus for SRAM bit cell with low standby current, low supply voltage and high speed
US20140001562A1 (en) Integrated Circuit Having FinFETS with Different Fin Profiles
US20130270652A1 (en) Apparatus for FinFETs
US7365432B2 (en) Memory cell structure
US20120299106A1 (en) Semiconductor device and method of fabrication
US20130272056A1 (en) Apparatus for SRAM Cells
US20080273382A1 (en) Pseudo 6T SRAM Cell
US6133608A (en) SOI-body selective link method and apparatus
US20070253239A1 (en) Read-preferred SRAM cell design
Chang et al. A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-V MIN applications
Chuang et al. High-performance SRAM in nanoscale CMOS: Design challenges and techniques
CN101494222A (en) Semiconductor memory device, semiconductor memory array and read-in method
US20120106236A1 (en) Tfet based 6t sram cell
Hu Device challenges and opportunities
CN1725373A (en) SRAM stable against various process-voltage-temperature variations
US20140306296A1 (en) Semiconductor device and method for fabricating the same
CN101221953A (en) Multiport and multi-channel embedded dynamic ram and operating method thereof

Legal Events

Date Code Title Description
C06 Publication
C10 Request of examination as to substance
C14 Granted