JPH0546100B2 - - Google Patents

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Publication number
JPH0546100B2
JPH0546100B2 JP59163410A JP16341084A JPH0546100B2 JP H0546100 B2 JPH0546100 B2 JP H0546100B2 JP 59163410 A JP59163410 A JP 59163410A JP 16341084 A JP16341084 A JP 16341084A JP H0546100 B2 JPH0546100 B2 JP H0546100B2
Authority
JP
Japan
Prior art keywords
mirror
semiconductor substrate
bonded
substrate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59163410A
Other languages
Japanese (ja)
Other versions
JPS6142154A (en
Inventor
Masaru Shinho
Kyoshi Fukuda
Kazuyoshi Furukawa
Tamotsu Oohata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP16341084A priority Critical patent/JPS6142154A/en
Publication of JPS6142154A publication Critical patent/JPS6142154A/en
Publication of JPH0546100B2 publication Critical patent/JPH0546100B2/ja
Granted legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、内部に誘電体埋込み層が形成された
半導体基板を製造する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor substrate having a dielectric buried layer formed therein.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体集積回路では、一般にpn接合により素
子分離が行われている。しかしこの素子分離法は
高耐圧素子を含む場合には問題である。電力用半
導体集積回路では、高圧大電流を扱う部分と小信
号を扱う信号処理回路や駆動回路部分を電気的に
確実に分離することが必要になるが、pn接合分
離では不十分であることが多い。このような場合
の素子分離法としては誘電体分離法が好ましい。
In semiconductor integrated circuits, elements are generally separated by pn junctions. However, this element isolation method poses a problem when high voltage elements are included. In power semiconductor integrated circuits, it is necessary to reliably electrically separate the parts that handle high voltages and large currents from the signal processing circuits and drive circuit parts that handle small signals, but pn junction isolation is insufficient. many. A dielectric isolation method is preferable as an element isolation method in such a case.

しかしながら誘電体分離法では、素子の一部を
誘電体で包み込むことが容易ではない。特に素子
領域を基板領域と分離するためには誘電体の埋込
み層が必要となるが、従来の誘電体埋込みの方法
には種々の難点があつた。
However, in the dielectric isolation method, it is not easy to wrap a part of the element with a dielectric. In particular, a dielectric embedding layer is required to separate the element region from the substrate region, but conventional dielectric embedding methods have various drawbacks.

その一つの方法は、半導体基板表面に素子を形
成し、横方向の素子分離を行つた後、半導体基板
を裏面からラツピングし素子領域の下部を露出さ
せ、ここに酸化膜等の誘電体膜を形成し、再び支
持体となるべき多結晶シリコン層等を形成するも
のである。この方法はプロセス上の制約が多い上
に、素子領域下の基板領域を電流経路や他の能動
素子として使用することを困難にする。
One method is to form elements on the surface of a semiconductor substrate, perform lateral element isolation, wrap the semiconductor substrate from the back side to expose the lower part of the element area, and then apply a dielectric film such as an oxide film to this area. Then, a polycrystalline silicon layer, etc., which is to serve as a support again is formed. This method has many process constraints and also makes it difficult to use the substrate area under the device area as a current path or other active device.

誘電体埋込み層形成の他の方法として、単結晶
基板の上に誘電体層を形成し、その上に多結晶シ
リコン層を堆積してこれを熱処理やレーザ光照射
により単結晶化する方法がある。しかしこの方法
も、形成される単結晶の大きさや質、形状等に制
約がある、といつた問題がある。
Another method for forming a buried dielectric layer is to form a dielectric layer on a single crystal substrate, deposit a polycrystalline silicon layer on top of it, and turn it into a single crystal by heat treatment or laser light irradiation. . However, this method also has problems such as limitations on the size, quality, shape, etc. of the single crystal that is formed.

以上のような理由で、特に電力用集積回路にお
いて素子特性上の要請を素子の設計に反映させる
ために多くの工夫が必要であつた。このため半導
体基板内部に簡単な工程で、制御性良く誘電体埋
込み層を形成する技術が望まれていた。
For the above-mentioned reasons, many efforts have been necessary to reflect requirements regarding device characteristics in device design, especially in power integrated circuits. For this reason, there has been a desire for a technique for forming a dielectric buried layer inside a semiconductor substrate through a simple process and with good controllability.

〔発明の目的〕[Purpose of the invention]

本発明は上記した点に鑑みてなされたもので、
内部に酸化膜を簡単且つ制御性良く埋込み形成す
ることを可能とした半導体基板の製造方法を提供
することを目的とする。
The present invention has been made in view of the above points, and
It is an object of the present invention to provide a method for manufacturing a semiconductor substrate that allows an oxide film to be embedded therein easily and with good controllability.

〔発明の概要〕[Summary of the invention]

本発明者らは、鏡面研磨された2枚の半導体基
板を、充分清浄な雰囲気下でゴミなどの異物を介
在させることなく研磨面どうしを密着させること
により、強固な接合体基板が得られ、更にこれを
200℃以上の温度で熱処理すれば接合強度がより
大になることを見出した。すなわち表面粗さが
500Å以下に鏡面研磨された半導体基板同士を清
浄な状態で接触させると、何等の接着剤を用いる
ことなく、また機械的な押圧力を要せず、強固な
接合体基板を得ることができるのである。この接
合のメカニズムの詳細は未だ不明であるが、鏡面
研磨面に形成される自然酸化膜が重要な役割を果
たしているらしいことが推測されるに至つてい
る。本発明はこの技術を用いるものであり、例え
ば、特開昭56−13733号公報に記載されているよ
うな高温加圧条件下で塑性変形を伴う技術とは異
なる技術によるものである。
The present inventors have discovered that a strong bonded substrate can be obtained by bringing the polished surfaces of two mirror-polished semiconductor substrates into close contact with each other in a sufficiently clean atmosphere without intervening foreign substances such as dust. Furthermore this
It has been found that heat treatment at a temperature of 200°C or higher increases the bonding strength. In other words, the surface roughness
If semiconductor substrates that have been mirror-polished to a thickness of 500 Å or less are brought into contact with each other in a clean state, a strong bonded substrate can be obtained without using any adhesive or requiring mechanical pressing force. be. Although the details of this bonding mechanism are still unclear, it has been speculated that the natural oxide film formed on the mirror-polished surface seems to play an important role. The present invention uses this technique, which is different from the technique that involves plastic deformation under high temperature and pressurized conditions, as described in, for example, Japanese Patent Application Laid-open No. 13733/1983.

すなわち本発明は、第1の半導体基板の表面粗
さ500A以下に鏡面研磨された表面に、第1の半
導体基板端面に開口する溝を形成する工程と、表
面粗さ500A以下に鏡面研磨された面を有する第
2の半導体基板及び第1の半導体基板の少なくと
も一方の鏡面研磨された表面に、第1及び第2の
半導体基板の鏡面研磨面どうしを接合したときに
前記溝と連通する前記溝より浅い凹部を形成する
工程と、第1及び第2の半導体基板の鏡面研磨面
どうしを清浄な雰囲気下で対向させて密着させ、
塑性変形させることなく直接接合した接合体基板
を形成する工程と、前記接合体基板を酸化性ガス
雰囲気に晒して前記溝に沿つて酸化性ガスを供給
することにより前記凹部に酸化膜を充填する工程
とを備え、直接接合された接合体基板内部に誘電
体埋込み層を形成することを特徴とする半導体基
板の製造方法である。
That is, the present invention includes a step of forming a groove opening to an end surface of the first semiconductor substrate on the surface of the first semiconductor substrate that has been mirror-polished to a surface roughness of 500A or less, and a step of forming a groove that opens to the end surface of the first semiconductor substrate; the groove that communicates with the groove when the mirror-polished surfaces of the first and second semiconductor substrates are bonded to the mirror-polished surface of at least one of the second semiconductor substrate and the first semiconductor substrate having a surface; a step of forming a shallower recess, and bringing the mirror-polished surfaces of the first and second semiconductor substrates into close contact with each other in a clean atmosphere,
forming a bonded substrate directly bonded without plastic deformation; and filling the recess with an oxide film by exposing the bonded substrate to an oxidizing gas atmosphere and supplying the oxidizing gas along the groove. A method of manufacturing a semiconductor substrate is characterized in that a dielectric buried layer is formed inside a directly bonded bonded substrate.

この場合、凹部を溝より浅く形成しておくこと
により、凹部が完全に酸化膜で充填されるまで酸
化性ガスを供給する溝が閉じられることがない。
In this case, by forming the recess to be shallower than the groove, the groove for supplying the oxidizing gas will not be closed until the recess is completely filled with the oxide film.

また凹部に、予め不純物を導入するかまたはダ
メージを与えてこの部分の酸化速度を速くする処
理を施すことにより、凹部を溝より浅くしなくて
も凹部を酸化膜で充填するまで酸化性ガスを供給
することができる。
In addition, by introducing impurities or damaging the recesses in advance to speed up the oxidation rate in these areas, oxidizing gas can be applied until the recesses are filled with an oxide film without having to make the recesses shallower than the grooves. can be supplied.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、非常に簡単に埋込み酸化膜を
形成した半導体基板を得ることができる。この埋
込み酸化膜は、半導体基板の厚みや凹部の深さ、
形状により埋込み位置や形状を任意に設定するこ
とができ、電力用集積回路や多層構造集積回路に
適用して有用である。
According to the present invention, a semiconductor substrate on which a buried oxide film is formed can be obtained very easily. This buried oxide film depends on the thickness of the semiconductor substrate and the depth of the recess.
The embedding position and shape can be set arbitrarily depending on the shape, and it is useful when applied to power integrated circuits and multilayer structure integrated circuits.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して本発明の実施例を説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

第1図a〜dは一実施例による製造工程を示
す。第1のシリコン基板11、第2のシリコン半
導体基板12はその接合すべき対向面が表面粗さ
500Å以下に鏡面研磨されている。これより凹凸
が大きいと良好な接着が実現しにくくなる。第1
のシリコン半導体基板11の研磨面には第1図a
に示すように、基板端部に開口する溝2が形成さ
れ、またこの溝2と一部重なるように所定のパタ
ーンで凹部3が形成されている。第2図はこの第
1のシリコン基板の溝2および凹部3が形成され
た様子を示す斜視図である。凹部3は酸化膜を埋
込む位置であつて、その深さは溝2より浅く、必
要とする酸化膜厚の0.7倍程度の深さとする。溝
2のピツチには特に制限はないが、素子のシービ
ングラインに合せれば便利である。これらの基板
1,12を充分洗浄し乾燥させた後、浮遊塵20
個/m3以下の清浄な雰囲気下で第1図bに示すよ
うに研磨面どうしを密着させ、接合する。この接
合体基板1は接合強度を高めるため200℃以上、
好ましくは1000℃程度で熱処理するのがよい。た
だしこの熱処理は次の熱工程で兼用することがで
きる。このように形成した接合体基板1を、酸素
性ガス雰囲気中で1200℃程度で加熱して、溝2に
沿つてガスを凹部3まで供給することにより、第
1図cに示すように凹部3を酸化膜4で埋込む。
この後接合体基板1を第1図cに一点鎖線で示す
位置まで研磨等により削り、第1図dに示す基板
を得る。
Figures 1a-d illustrate the manufacturing process according to one embodiment. The first silicon substrate 1 1 and the second silicon semiconductor substrate 1 2 have opposing surfaces to be bonded that have surface roughness.
Mirror polished to 500Å or less. If the unevenness is larger than this, it becomes difficult to achieve good adhesion. 1st
The polished surface of the silicon semiconductor substrate 11 is shown in Figure 1a.
As shown in FIG. 2, a groove 2 opening at the end of the substrate is formed, and a recess 3 is formed in a predetermined pattern so as to partially overlap the groove 2. As shown in FIG. FIG. 2 is a perspective view showing how grooves 2 and recesses 3 are formed in this first silicon substrate. The recess 3 is a position where an oxide film is buried, and its depth is shallower than the trench 2, and is approximately 0.7 times as deep as the required oxide film thickness. There is no particular limit to the pitch of the grooves 2, but it is convenient if it matches the sheaving line of the element. After thoroughly cleaning and drying these substrates 1 1 and 1 2 , floating dust 20
The polished surfaces are brought into close contact with each other and bonded as shown in FIG . This bonded substrate 1 is heated at temperatures above 200°C to increase bonding strength.
Preferably, the heat treatment is performed at about 1000°C. However, this heat treatment can also be used in the next heat step. The thus formed bonded substrate 1 is heated at about 1200° C. in an oxygen gas atmosphere and gas is supplied along the grooves 2 to the recesses 3, thereby forming the recesses 3 as shown in FIG. 1c. is filled with an oxide film 4.
Thereafter, the bonded substrate 1 is ground by polishing or the like to the position shown by the dashed line in FIG. 1c to obtain the substrate shown in FIG. 1d.

このようにして酸化膜4が埋め込まれた基板に
所望の素子を形成し、常法に従つて横方向の素子
分離を行えば、集積回路が得られる。
Desired elements are formed on the substrate in which the oxide film 4 is embedded in this manner, and the elements are separated in the lateral direction according to a conventional method to obtain an integrated circuit.

こうして本実施例によれば、酸化膜4を内部に
埋込み形成したシリコン基板を簡単に形成するこ
とができる。この基板は酸化膜4を素子分離層と
して通常のIC基板として用いることができるだ
けでなく、酸化膜4が基板を上下に完全に電気的
に分離する状態とすれば、多層構造IC基板とし
ても用いられる。
Thus, according to this embodiment, it is possible to easily form a silicon substrate in which the oxide film 4 is embedded. This substrate can not only be used as a normal IC substrate with the oxide film 4 as an element isolation layer, but also as a multilayer IC substrate if the oxide film 4 completely electrically isolates the upper and lower parts of the substrate. It will be done.

第3図a〜dは本発明の別の実施例の製造工程
を示す。第3図aに示すように、第1のシリコン
基板11には先の実施例と同様に溝2を形成し、
第2のシリコン基板12には凹部3を形成する。
凹部3にはイオン注入により高不純物濃度層5を
形成しておく。この後先の実施例と同様にして第
3図bに示すように接合体基板を形成し、酸化性
ガス雰囲気中で熱処理する。凹部3は他の部分よ
り酸化速度が2倍程度速いため、第3図cに示す
ようにこの部分が先に酸化膜4で埋め込まれ、こ
うしてち密な酸化膜埋込み層を形成した半導体基
板が得られる。第3図dは更に酸化処理を継続し
て、溝2の殆ど全てが酸化膜で埋め込まれるよう
にした場合である。
Figures 3a-d illustrate the manufacturing process of another embodiment of the invention. As shown in FIG. 3a, grooves 2 are formed in the first silicon substrate 11 in the same manner as in the previous embodiment,
A recess 3 is formed in the second silicon substrate 12 .
A high impurity concentration layer 5 is formed in the recess 3 by ion implantation. Thereafter, a bonded substrate is formed as shown in FIG. 3b in the same manner as in the previous embodiment, and heat treated in an oxidizing gas atmosphere. Since the oxidation rate of the recess 3 is about twice as fast as that of other parts, this part is first filled with the oxide film 4 as shown in FIG. It will be done. FIG. 3d shows the case where the oxidation treatment is further continued so that almost all of the grooves 2 are filled with an oxide film.

この実施例によつても先の実施例と同様の効果
が得られる。
This embodiment also provides the same effects as the previous embodiment.

なお溝と凹部は、二枚の半導体基板を接合した
時に互いに連通すればよいのであつてこれらはい
ずれの半導体基板に形成しても差支えない。
Note that the groove and the recess may be formed in either semiconductor substrate as long as they communicate with each other when the two semiconductor substrates are bonded.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a〜dは本発明の一実施例を説明するた
めの工程断面図、第2図はその第1の基板の斜視
図、第3図a〜dは他の実施例を説明するための
工程断面図である。 11……第1のシリコン基板、12……第2のシ
リコン基板、2……溝、3……凹部、4……埋込
み酸化膜、5……高不純物濃度層。
Figures 1 a to d are process sectional views for explaining one embodiment of the present invention, Figure 2 is a perspective view of the first substrate, and Figures 3 a to d are for explaining other embodiments. FIG. 1 1 ... first silicon substrate, 1 2 ... second silicon substrate, 2 ... groove, 3 ... recess, 4 ... buried oxide film, 5 ... high impurity concentration layer.

Claims (1)

【特許請求の範囲】 1 第1の半導体基板の表面粗さ500A以下に鏡
面研磨された表面に、第1の半導体基板端面に開
口する溝を形成する工程と、表面粗さ500A以下
に鏡面研磨された面を有する第2の半導体基板及
び第1の半導体基板の少なくとも一方の鏡面研磨
された表面に、第1及び第2の半導体基板の鏡面
研磨面どうしを接合したときに前記溝と連通する
前記溝より浅い凹部を形成する工程と、第1及び
第2の半導体基板の鏡面研磨面どうしを清浄な雰
囲気下で対向させて密着させ、塑性変形させるこ
となく直接接合した接合体基板を形成する工程
と、前記接合体基板を酸化性ガス雰囲気に晒して
前記溝に沿つて酸化性ガスを供給することにより
前記凹部に酸化膜を充填する工程とを備え、直接
接合された接合体基板内部に誘電体埋込み層を形
成することを特徴とする半導体基板の製造方法。 2 第1の半導体基板の表面粗さ500A以下に鏡
面研磨された表面に、第1の半導体基板端面に開
口する溝を形成する工程と、表面粗さ500A以下
に鏡面研磨された面を有する第2の半導体基板及
び第1の半導体基板の少なくとも一方の鏡面研磨
された表面に、第1及び第2の半導体基板の鏡面
研磨面どうしを接合したときに前記溝と連通する
前記溝より浅い凹部を形成する工程と、前記凹部
に不純物導入またはダメージを与えることでその
部分の酸化速度を他の部分より早くする処理を行
う工程と、第1及び第2の半導体基板の鏡面研磨
面どうしを清浄な雰囲気下で対向させて密着さ
せ、塑性変形させることなく直接接合した接合体
基板を形成する工程と、前記接合体基板を酸化性
ガス雰囲気に晒して前記溝に沿つて酸化性ガスを
供給することにより前記凹部に酸化膜を充填する
工程とを備え、直接接合された接合体基板内部に
誘電体埋込み層を形成することを特徴とする半導
体基板の製造方法。
[Claims] 1. A step of forming a groove opening to the end face of the first semiconductor substrate on the mirror-polished surface of the first semiconductor substrate to a surface roughness of 500A or less, and mirror polishing to a surface roughness of 500A or less. When the mirror-polished surfaces of the first and second semiconductor substrates are bonded to the mirror-polished surfaces of at least one of the second semiconductor substrate and the first semiconductor substrate, which have a polished surface, the mirror-polished surfaces of the first and second semiconductor substrates communicate with the groove. forming a recess shallower than the groove; and forming a bonded substrate in which the mirror-polished surfaces of the first and second semiconductor substrates are brought into close contact with each other facing each other in a clean atmosphere, and are directly bonded without plastic deformation. and a step of filling the concave portion with an oxide film by exposing the bonded substrate to an oxidizing gas atmosphere and supplying the oxidizing gas along the groove, and filling the inside of the bonded substrate directly. A method of manufacturing a semiconductor substrate, comprising forming a dielectric buried layer. 2. Forming a groove opening to the end face of the first semiconductor substrate on the mirror-polished surface of the first semiconductor substrate to a surface roughness of 500A or less; A recess shallower than the groove that communicates with the groove when the mirror-polished surfaces of the first and second semiconductor substrates are bonded to each other is formed in the mirror-polished surface of at least one of the second semiconductor substrate and the first semiconductor substrate. a process of introducing impurities into the recess or damaging the recess to make the oxidation rate of that part faster than other parts; and a process of cleaning the mirror-polished surfaces of the first and second semiconductor substrates. A step of forming bonded substrates that are directly bonded to each other by facing each other in close contact with each other without plastic deformation in an atmosphere, and exposing the bonded substrates to an oxidizing gas atmosphere and supplying an oxidizing gas along the grooves. A method of manufacturing a semiconductor substrate, comprising: filling the recess with an oxide film, and forming a dielectric buried layer inside the directly bonded assembly substrate.
JP16341084A 1984-08-02 1984-08-02 Manufacture of semiconductor substrate Granted JPS6142154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16341084A JPS6142154A (en) 1984-08-02 1984-08-02 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16341084A JPS6142154A (en) 1984-08-02 1984-08-02 Manufacture of semiconductor substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP1293487A Division JPH0669063B2 (en) 1989-11-10 1989-11-10 Semiconductor wafer manufacturing method

Publications (2)

Publication Number Publication Date
JPS6142154A JPS6142154A (en) 1986-02-28
JPH0546100B2 true JPH0546100B2 (en) 1993-07-13

Family

ID=15773360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16341084A Granted JPS6142154A (en) 1984-08-02 1984-08-02 Manufacture of semiconductor substrate

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JP (1) JPS6142154A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63126245A (en) * 1986-11-15 1988-05-30 Mitsubishi Electric Corp Semiconductor device
JPH01111888U (en) * 1988-01-25 1989-07-27
JP2685244B2 (en) * 1988-09-30 1997-12-03 株式会社日本自動車部品総合研究所 Method for manufacturing semiconductor device
US5164218A (en) * 1989-05-12 1992-11-17 Nippon Soken, Inc. Semiconductor device and a method for producing the same
JPH03283636A (en) * 1990-03-30 1991-12-13 Nippon Soken Inc Manufacture of semiconductor substrate
JPH04258595A (en) * 1991-02-12 1992-09-14 Ishikawajima Harima Heavy Ind Co Ltd Globe valve

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613773A (en) * 1979-07-03 1981-02-10 Licentia Gmbh Fet and method of manufacturing same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613773A (en) * 1979-07-03 1981-02-10 Licentia Gmbh Fet and method of manufacturing same

Also Published As

Publication number Publication date
JPS6142154A (en) 1986-02-28

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