JPH04307735A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH04307735A
JPH04307735A JP7158291A JP7158291A JPH04307735A JP H04307735 A JPH04307735 A JP H04307735A JP 7158291 A JP7158291 A JP 7158291A JP 7158291 A JP7158291 A JP 7158291A JP H04307735 A JPH04307735 A JP H04307735A
Authority
JP
Japan
Prior art keywords
film
soi
polishing
sio2
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7158291A
Other languages
Japanese (ja)
Inventor
Yutaka Ito
豊 伊藤
Tadashi Morimoto
廉 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7158291A priority Critical patent/JPH04307735A/en
Publication of JPH04307735A publication Critical patent/JPH04307735A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To polish a thick-film SOI film and to make it into a thin film having the good uniformity in its film thickness. CONSTITUTION:A second SiO2 film 5 is deposited on an opening part 4 formed in a semiconductor film 3 on a first insulator 2. The film thickness of the second SiO2 film 5 is set to a target film thickness for an SOI. After that, resist is left only in the opening part by a resist coating operation and by an etching- back method, and the second SiO2 film 5 other than the bottom part of the opening part 4 is removed by a wet etching operation or a dry etching operation. After that, the SOI film is polished and made into a thin film by using an abrasive material until the second SiO2 film 5 on the bottom part of the opening part 4 comes into contact with an abrasive plate. When a material whose polishing rate is large with reference to Si and very small with reference to SiO2 is selected as the abrasive material, the second SiO2 film 5 at the bottom part of the opening part 4 acts as a polishing stopper, and the SOI film can be polished over the whole surface of a wafer and can be made a thin film so as to make the uniformity of its film thickness good.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はSOI(Silicon
 On Insulator)形の高性能の半導体装置
の製造方法に関する。
[Industrial Application Field] The present invention relates to SOI (Silicon
The present invention relates to a method of manufacturing a high-performance semiconductor device of the on-insulator type.

【0002】0002

【従来の技術】近年、SOI形半導体装置は、耐放射線
性、高速性においてSi基板に形成した半導体装置に比
べ優位性を持つため、実用化に向け研究が行われている
。SOI形半導体装置は一般にSi膜の膜厚が0.2μ
m前後より薄くないとSi基板に形成した半導体装置に
対して優位性が小さかった。ところが、ZMR(Zon
e Melting Recrystallizati
on)法、貼合わせ法で、形成したSOI基板は一般に
膜厚が0.5μm以上あり、しかも膜厚の均一性も悪く
、これを研磨により薄膜化することは膜厚制御の面で非
常に困難であった。そこで、予め、研磨ストッパーパタ
ーンを形成しておき、その後ZMR法、貼合わせ法でS
OI膜を形成し研磨により薄膜化する方法があった。
2. Description of the Related Art In recent years, SOI type semiconductor devices have been studied for practical use because they have advantages over semiconductor devices formed on Si substrates in terms of radiation resistance and high speed. Generally, the thickness of the Si film in SOI type semiconductor devices is 0.2μ.
Unless it is thinner than about m, it has little advantage over a semiconductor device formed on a Si substrate. However, ZMR (Zon
e Melting Recrystallizati
SOI substrates formed using the on) method and the bonding method generally have a film thickness of 0.5 μm or more, and the film thickness is not uniform, so reducing the film thickness by polishing is extremely difficult in terms of film thickness control. It was difficult. Therefore, a polishing stopper pattern is formed in advance, and then S
There is a method in which an OI film is formed and the film is made thinner by polishing.

【0003】以下図面を参照しながら、上記した従来の
薄膜SOIを形成するための半導体装置の製造方法の一
例について説明する。図2は研磨ストッパーパターンと
ZMR法を用いた薄膜SOIの形成方法を示すものであ
る。
An example of a method for manufacturing a semiconductor device for forming the above-mentioned conventional thin film SOI will be described below with reference to the drawings. FIG. 2 shows a method of forming a thin film SOI using a polishing stopper pattern and the ZMR method.

【0004】まず同図(a)では、Si基板101上に
研磨ストッパーパターン103を有するSiO2膜10
2を形成し、さらにその上に非単結晶Si膜104を形
成する。次に同図(b)では、非単結晶Si膜104を
線状ヒータ106により溶融再結晶化し、単結晶Si膜
105を形成する。
First, in FIG. 1A, a SiO2 film 10 having a polishing stopper pattern 103 on a Si substrate 101 is shown.
2 is formed, and a non-single crystal Si film 104 is further formed thereon. Next, in FIG. 3B, the non-single crystal Si film 104 is melted and recrystallized by the linear heater 106 to form a single crystal Si film 105.

【0005】次に同図(c)では、非研磨材と研磨板を
用いて単結晶Si膜105を研磨ストッパーパターン1
03表面が研磨板に接するまで研磨し薄膜化する。研磨
レートがSiに対してはやくSiO2に対して非常に遅
い研磨材を選ぶことにより、研磨ストッパーパターン1
03表面が研磨板に接すると研磨速度が極端に低下し、
ウェハー全面で同図(c)に示すように膜厚の均一性の
よい単結晶Si膜が形成できるのである。
Next, in FIG. 1C, the single crystal Si film 105 is polished using a non-abrasive material and a polishing plate.
03 Polish the surface until it touches the polishing plate to form a thin film. By selecting an abrasive whose polishing rate is fast for Si and very slow for SiO2, polishing stopper pattern 1
03 When the surface comes into contact with the polishing plate, the polishing speed decreases extremely,
A single-crystal Si film with good thickness uniformity can be formed over the entire surface of the wafer, as shown in FIG. 3(c).

【0006】図3は研磨ストッパーパターンと貼合わせ
法を用いた薄膜SOIの形成方法を示すものである。
FIG. 3 shows a method for forming a thin film SOI using a polishing stopper pattern and a bonding method.

【0007】まず同図(a)では、第1のSi基板20
1にフォトマスク法とドライエッチ法により凹部204
を形成し、その後SiO2膜202、および多結晶Si
膜203を堆積する。凹部204の深さは目標とするS
OI膜厚と同じに設定する。
First, in FIG. 2(a), a first Si substrate 20
1, a recess 204 is formed using a photomask method and a dry etching method.
is formed, and then a SiO2 film 202 and a polycrystalline Si film 202 are formed.
Deposit film 203. The depth of the recess 204 is the target S
Set it to be the same as the OI film thickness.

【0008】次に同図(b)では、研磨板と研磨材を用
いて多結晶Si膜203を研磨し凹部204の部分以外
の多結晶Si膜203を除去する。
Next, in FIG. 2B, the polycrystalline Si film 203 is polished using a polishing plate and an abrasive to remove the polycrystalline Si film 203 other than the recessed portion 204.

【0009】次に同図(c)では、第1のSi基板20
1と第2のSi基板205を貼合わせ接着する。
Next, in FIG. 2(c), the first Si substrate 20
The first and second Si substrates 205 are bonded and bonded together.

【0010】次に同図(d)に示すように研磨板と研磨
材を用いて第1のSi基板201を裏面側から研磨して
いき、凹部204におけるSiO2膜202が露出する
まで研磨する。最終的にSOI薄膜206が膜厚の均一
性よく形成される。
Next, as shown in FIG. 2D, the first Si substrate 201 is polished from the back side using a polishing plate and a polishing material until the SiO2 film 202 in the recess 204 is exposed. Finally, the SOI thin film 206 is formed with good film thickness uniformity.

【0011】[0011]

【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、例えばZMR法の場合は、再結晶化時に
研磨ストッパーパターンが下地段差として存在するため
、再結晶化SOI層において研磨ストッパーパターン周
辺で結晶欠陥が発生したり、研磨ストッパーパターンを
再結晶化前に形成するため、再結晶化したあとは研磨ス
トッパーパターンにより素子レイアウトが制約されるの
で、素子レイアウト設計をしてからでないと再結晶化で
きないとうという問題点を有していた。
[Problems to be Solved by the Invention] However, in the above structure, for example, in the case of the ZMR method, the polishing stopper pattern exists as a step on the base during recrystallization, so that the polishing stopper pattern around the polishing stopper pattern in the recrystallized SOI layer is Crystal defects may occur, and since the polishing stopper pattern is formed before recrystallization, the device layout will be restricted by the polishing stopper pattern after recrystallization, so recrystallization must be done after designing the device layout. The problem was that it could not be done.

【0012】また、研磨ストッパーパターンを形成後、
貼合わせおよび研磨により薄膜化する場合は、研磨工程
を2回通らねばならず、また貼合わせる前に素子レイア
ウト設計を終えて研磨ストッパーパターンを形成しなけ
らばならないという問題点を有していた。また研磨スト
ッパーパターンがない場合には研磨によりSi膜厚が大
きくバラつくという問題点を有していた。
[0012] Also, after forming the polishing stopper pattern,
When thinning the film by bonding and polishing, there were problems in that the polishing process had to be performed twice, and the device layout design had to be completed and a polishing stopper pattern had to be formed before bonding. . Furthermore, when there is no polishing stopper pattern, there is a problem in that the Si film thickness varies greatly due to polishing.

【0013】本発明は上記問題点に鑑み、研磨ストッパ
ーパターンを後から形成するのでZMR法で再結晶化す
る場合にSOI層の結晶性に影響を与えず、素子レイア
ウト設計がまだでも再結晶化や貼合わせにより厚膜のS
OI形成までは行うことができ、また研磨ストッパーパ
ターンの無いSOI基板でも膜厚の制御性よく薄膜化が
可能な半導体装置の製造方法を提供することを目的とす
る。
In view of the above-mentioned problems, the present invention forms a polishing stopper pattern afterwards, so it does not affect the crystallinity of the SOI layer when recrystallizing by the ZMR method, and recrystallization can be performed even when the element layout is not yet designed. Thick film S
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can perform up to OI formation, and which can thin the film with good controllability even on an SOI substrate without a polishing stopper pattern.

【0014】[0014]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、第1の絶縁膜上に形成された半導体膜に開口
部を設ける工程と、この開口部に第2の絶縁膜を堆積す
る工程と、前記開口部の底面を除く部分の前記第2の絶
縁膜を除去する工程と、前記開口部の底面に残った前記
第2の絶縁膜を研磨ストッパーとして研磨板と研磨材を
用いて前記半導体膜を薄膜化する工程とを備えたもので
ある。
[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes the steps of providing an opening in a semiconductor film formed on a first insulating film, and depositing a second insulating film in the opening. a step of removing the second insulating film in a portion other than the bottom surface of the opening, and using a polishing plate and an abrasive material with the second insulating film remaining on the bottom surface of the opening as a polishing stopper. and a step of thinning the semiconductor film.

【0015】[0015]

【作用】本発明は上記した構成によって、SOI層の形
成後に研磨ストッパーパターンを形成するため、素子レ
イアウト設計ができていなくても厚膜SOIの形成まで
は進めることができ、また研磨ストッパーパターンの無
いSOI基板にも後から研磨ストッパーパターンを形成
して薄膜化することが可能となる。
[Operation] With the above-described structure, the present invention forms a polishing stopper pattern after forming the SOI layer, so even if the element layout design has not been completed, it is possible to proceed with the formation of a thick film SOI. It becomes possible to form a polishing stopper pattern later on an SOI substrate that does not have one, thereby making it a thin film.

【0016】[0016]

【実施例】以下本発明の一実施例の半導体装置の製造方
法についてについて、図面を参照しながら説明する。図
1は本発明の実施例における半導体装置の製造方法を示
す部分工程断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a partial process cross-sectional view showing a method for manufacturing a semiconductor device in an embodiment of the present invention.

【0017】図1(a)は、第1の絶縁膜2上に半導体
膜3が形成された基板1、すなわちSOI基板の断面図
である。基板1としては例えばSi基板、第1の絶縁膜
2としては例えばSiO2膜、半導体膜3としては例え
ばSi単結晶膜とする。このSOI基板はZMR法、貼
合わせ法、SIMOX法、エピタキシャル成長法、陽極
酸化法、レーザ・電子ビーム再結晶化法などを用いて形
成したものであり、半導体膜3の膜厚は0.1μmから
3μm程度、第1の絶縁膜2の膜厚は0.01μmから
5μm程度が適当である。
FIG. 1A is a cross-sectional view of a substrate 1 in which a semiconductor film 3 is formed on a first insulating film 2, that is, an SOI substrate. The substrate 1 is, for example, a Si substrate, the first insulating film 2 is, for example, a SiO2 film, and the semiconductor film 3 is, for example, a Si single crystal film. This SOI substrate is formed using a ZMR method, a bonding method, a SIMOX method, an epitaxial growth method, an anodizing method, a laser/electron beam recrystallization method, etc., and the thickness of the semiconductor film 3 is from 0.1 μm to 0.1 μm. Appropriately, the thickness of the first insulating film 2 is approximately 3 μm, and the thickness of the first insulating film 2 is approximately 0.01 μm to 5 μm.

【0018】このような構造のSOI基板に図1(b)
に示すように半導体膜3にフォトマスク法とドライエッ
チ法により開口部4を設ける。開口部4の形状、大きさ
は限定されるものではないが、格子状に形成すると後の
研磨工程において膜厚の均一性を得やすい。格子の1辺
は数μmから数100μmが適当である。また幅は1μ
m程度から数10μm程度とする。
FIG. 1(b) shows an SOI substrate having such a structure.
As shown in FIG. 3, an opening 4 is formed in the semiconductor film 3 by a photomask method and a dry etching method. Although the shape and size of the openings 4 are not limited, if they are formed in a lattice shape, it is easier to obtain uniformity in film thickness in the subsequent polishing process. Appropriately, one side of the grating is several μm to several 100 μm. Also, the width is 1μ
It is set to be about m to several tens of μm.

【0019】次に図1(c)では、開口部4を含む全面
に第2の絶縁膜5を堆積する。第2の絶縁膜5は例えば
CVD法によるSiO2膜とする。ここで重要なことは
第2の絶縁膜5の膜厚が開口部4底部と半導体膜3上で
等しくなるように堆積条件や堆積装置を選ぶことである
。第2の絶縁膜5の膜厚は半導体膜3の研磨目標膜厚で
もあり、よって0.3μm以下,0.01μm以上が適
当である。
Next, in FIG. 1(c), a second insulating film 5 is deposited over the entire surface including the opening 4. Then, as shown in FIG. The second insulating film 5 is, for example, a SiO2 film formed by CVD. What is important here is to select the deposition conditions and deposition apparatus so that the thickness of the second insulating film 5 is equal on the bottom of the opening 4 and on the semiconductor film 3. The thickness of the second insulating film 5 is also the polishing target thickness of the semiconductor film 3, and is therefore suitably 0.3 μm or less and 0.01 μm or more.

【0020】次に図1(d)では、開口部4を含む全面
にレジスト塗布を行う。そして図1(e)に示すように
レジスト全面エッチバックにより開口部4にのみレジス
トを残す。なお、ここでは開口部4にレジストを残す方
法としてエッチバック法を用いたがフォトマスク露光工
程を用いてもよい。
Next, in FIG. 1(d), a resist is applied to the entire surface including the opening 4. Then, as shown in FIG. 1(e), the entire resist is etched back, leaving the resist only in the opening 4. Note that although an etch-back method is used here as a method for leaving the resist in the opening 4, a photomask exposure process may also be used.

【0021】次に図1(f)では、ドライエッチもしく
はウェットエッチ法により開口部4底部以外の第2の絶
縁膜5を除去する。
Next, in FIG. 1(f), the second insulating film 5 other than the bottom of the opening 4 is removed by dry etching or wet etching.

【0022】次に図1(g)では研磨板6と研磨材を用
いて、半導体膜3を開口部4底部の第2の絶縁膜5が露
出するまで研磨、薄膜化する。研磨レートが半導体膜3
に対して大きく第2の絶縁膜5に対して非常に小さい研
磨材を選ぶことにより、図1(h)のように半導体膜3
の膜厚が開口部4底部の第2の絶縁膜5の膜厚に等しく
なり、開口部4底部の第2の絶縁膜5の表面が研磨板6
に接すると研磨速度が著しく低下し、半導体膜3の研磨
は進まなくなり、図1(i)に示すように基板1全面に
わたって第2の絶縁膜5に等しい膜厚の半導体膜3が得
られる。研磨材としては例えばアミン系水溶液を用いる
Next, in FIG. 1G, the semiconductor film 3 is polished and thinned using a polishing plate 6 and an abrasive material until the second insulating film 5 at the bottom of the opening 4 is exposed. Polishing rate is semiconductor film 3
By selecting an abrasive that is large for the second insulating film 5 and very small for the second insulating film 5, the semiconductor film 3 is polished as shown in FIG. 1(h).
The film thickness of the second insulating film 5 at the bottom of the opening 4 is equal to that of the second insulating film 5 at the bottom of the opening 4, and the surface of the second insulating film 5 at the bottom of the opening 4 is
When the polishing rate comes into contact with the semiconductor film 3, the polishing rate decreases significantly and the polishing of the semiconductor film 3 stops progressing, and the semiconductor film 3 having the same thickness as the second insulating film 5 is obtained over the entire surface of the substrate 1 as shown in FIG. 1(i). For example, an amine aqueous solution is used as the polishing material.

【0023】なお本実施例において、半導体膜3はSi
単結晶膜としたが、Si多結晶膜やGe膜、GaAs膜
でもよい。
In this embodiment, the semiconductor film 3 is made of Si.
Although a single crystal film is used, a Si polycrystal film, a Ge film, or a GaAs film may be used.

【0024】[0024]

【発明の効果】以上のように本発明は、SOI層形成後
に研磨ストッパーパターンを設けることにより、SOI
層の結晶性に悪影響を与えず、また研磨ストッパーパタ
ーンの無いSOI基板も研磨薄膜化することができる。
Effects of the Invention As described above, the present invention provides a polishing stopper pattern after forming an SOI layer.
It does not adversely affect the crystallinity of the layer, and even an SOI substrate without a polishing stopper pattern can be polished into a thin film.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例における半導体装置の製造方
法の工程断面図である。
FIG. 1 is a process cross-sectional view of a method for manufacturing a semiconductor device in an embodiment of the present invention.

【図2】従来例を説明する工程断面図である。FIG. 2 is a process sectional view illustrating a conventional example.

【図3】従来例を説明する工程断面図である。FIG. 3 is a process cross-sectional view illustrating a conventional example.

【符号の説明】[Explanation of symbols]

1  基板 2  第1の絶縁膜 3  半導体膜 4  開口部 5  第2の絶縁膜 7  研磨板 1 Board 2 First insulating film 3 Semiconductor film 4 Opening 5 Second insulating film 7. Polishing plate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】第1の絶縁膜上に形成された半導体膜に開
口部を設ける工程と、この開口部に第2の絶縁膜を堆積
する工程と、前記開口部の底面を除く部分の前記第2の
絶縁膜を除去する工程と、前記開口部の底面に残った前
記第2の絶縁膜を研磨ストッパーとして研磨板と研磨材
を用いて前記半導体膜を薄膜化する工程とを備えた半導
体装置の製造方法。
1. A step of forming an opening in a semiconductor film formed on a first insulating film, a step of depositing a second insulating film in the opening, and a step of depositing a second insulating film in the opening. A semiconductor device comprising: removing a second insulating film; and using a polishing plate and an abrasive material to thin the semiconductor film using the second insulating film remaining on the bottom surface of the opening as a polishing stopper. Method of manufacturing the device.
JP7158291A 1991-04-04 1991-04-04 Manufacture of semiconductor device Pending JPH04307735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7158291A JPH04307735A (en) 1991-04-04 1991-04-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7158291A JPH04307735A (en) 1991-04-04 1991-04-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04307735A true JPH04307735A (en) 1992-10-29

Family

ID=13464832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7158291A Pending JPH04307735A (en) 1991-04-04 1991-04-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04307735A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0599761A1 (en) * 1992-10-27 1994-06-01 International Business Machines Corporation A method of forming uniformly thin, isolated silicon mesas on an insulating substrate
US5795828A (en) * 1994-07-14 1998-08-18 Matsushita Electric Industrial Co., Ltd. Electroless plating bath used for forming a wiring of a semiconductor device, and method of forming a wiring of a semiconductor device
US6025270A (en) * 1997-02-03 2000-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Planarization process using tailored etchback and CMP

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0599761A1 (en) * 1992-10-27 1994-06-01 International Business Machines Corporation A method of forming uniformly thin, isolated silicon mesas on an insulating substrate
US5795828A (en) * 1994-07-14 1998-08-18 Matsushita Electric Industrial Co., Ltd. Electroless plating bath used for forming a wiring of a semiconductor device, and method of forming a wiring of a semiconductor device
US6025270A (en) * 1997-02-03 2000-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Planarization process using tailored etchback and CMP

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