JPH04258152A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH04258152A
JPH04258152A JP1982091A JP1982091A JPH04258152A JP H04258152 A JPH04258152 A JP H04258152A JP 1982091 A JP1982091 A JP 1982091A JP 1982091 A JP1982091 A JP 1982091A JP H04258152 A JPH04258152 A JP H04258152A
Authority
JP
Japan
Prior art keywords
film
sio2
polishing
opening
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982091A
Other languages
Japanese (ja)
Inventor
Yutaka Ito
豊 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1982091A priority Critical patent/JPH04258152A/en
Publication of JPH04258152A publication Critical patent/JPH04258152A/en
Pending legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To make a polishing stopper pattern later at an SOI substrate, which has a rather thick Si layer, and make a film SOI by the filming by polishing. CONSTITUTION:In an Si substrate (SOI substrate), equipped with a first Si film 3 through the first SiO2 film made by ZMR method, a first aperture 4 and a second aperture 7 are made partially, and a second Si film 8 is grown selectively by CVD method. Then, by thermal oxidation, a third SiO2 film 9 is made on the second Si film 8, and using a polishing plate and an abrasive, the first Si film 3 is filmed by polishing with the third SiO2 film 9 as a stopper.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はSOI(Silicon
 On Insulator)型半導体装置の製造方法
に関するものである。
[Industrial Application Field] The present invention relates to SOI (Silicon
The present invention relates to a method for manufacturing an on-insulator type semiconductor device.

【0002】0002

【従来の技術】近年、SOI型半導体装置は、耐放射線
性、高速性においてSi基板につくられた半導体装置に
比べ優位性を持つものとして実用化されつつある。SO
I型半導体装置は一般にSi膜の膜厚が0.2μm前後
より薄くないとSi基板に形成した半導体装置に対して
優位性が小さかった。ところが、ZMR(Zone M
elting Recrystallization)
法、貼合わせ法で形成したSOI基板は一般に膜厚が0
.5μm以上あり、しかも膜厚の均一性も悪い。これを
研磨により薄膜化することは膜厚制御の面で非常に困難
であった。そこで、予め研磨ストッパーパターンを形成
しておき、その後ZMR法、貼合わせ法でSOI膜を形
成し研磨により薄膜化する方法があった。
2. Description of the Related Art In recent years, SOI type semiconductor devices have been put into practical use as they have advantages over semiconductor devices fabricated on Si substrates in terms of radiation resistance and high speed. S.O.
In general, type I semiconductor devices have little superiority over semiconductor devices formed on Si substrates unless the thickness of the Si film is less than about 0.2 μm. However, ZMR (Zone M
elting Recrystallization)
SOI substrates formed by the bonding method and bonding method generally have a film thickness of 0.
.. The thickness is 5 μm or more, and the uniformity of the film thickness is also poor. It was extremely difficult to reduce the thickness of this film by polishing in terms of film thickness control. Therefore, there has been a method in which a polishing stopper pattern is formed in advance, and then an SOI film is formed using a ZMR method or a bonding method, and the film is made thinner by polishing.

【0003】図4は従来の研磨ストッパーパターンとZ
MR法を用いた薄膜SOIの形成方法を示すものである
。図4において、101はSi基板、102はSiO2
膜、103は研磨ストッパーパターン、104は非単結
晶Si膜、105は単結晶Si膜である。
FIG. 4 shows a conventional polishing stopper pattern and Z
This shows a method for forming a thin film SOI using the MR method. In FIG. 4, 101 is a Si substrate, 102 is a SiO2
103 is a polishing stopper pattern, 104 is a non-single crystal Si film, and 105 is a single crystal Si film.

【0004】以上のように構成された研磨ストッパーパ
ターンとZMR法を用いた薄膜SOIの形成方法につい
て、以下その動作について説明する。
The operation of the method for forming a thin film SOI using the polishing stopper pattern constructed as described above and the ZMR method will be described below.

【0005】まず図4(a)に示すようにSi基板10
1上に研磨ストッパーパターン103を有するSiO2
膜102を形成し、さらにその上に非単結晶Si膜10
4を形成する。次に図4(b)に示すように非単結晶S
i膜104を線状ヒータ106により溶融再結晶化し、
単結晶Si膜105を形成する。
First, as shown in FIG. 4(a), a Si substrate 10 is
SiO2 with polishing stopper pattern 103 on 1
A film 102 is formed, and a non-single crystal Si film 10 is further formed thereon.
form 4. Next, as shown in Fig. 4(b), the non-single crystal S
The i-film 104 is melted and recrystallized by a linear heater 106,
A single crystal Si film 105 is formed.

【0006】次に図4(c)に示すように研磨材と研磨
板を用いて単結晶Si膜105を研磨ストッパーパター
ン103が露出するまで研磨し薄膜化する。研磨レート
がSiがはやくSiO2がほとんど削れない研磨材を選
ぶことにより、研磨ストッパーパターン103が露出す
ると研磨速度が非常に遅くなりウェハー全面での膜厚の
均一性のよい単結晶Si膜が形成できるのである。
Next, as shown in FIG. 4C, the monocrystalline Si film 105 is polished using an abrasive and a polishing plate until the polishing stopper pattern 103 is exposed, thereby reducing its thickness. By selecting an abrasive that has a fast polishing rate for Si and hardly removes SiO2, the polishing rate becomes extremely slow when the polishing stopper pattern 103 is exposed, and a single crystal Si film with a uniform thickness over the entire wafer surface can be formed. It is.

【0007】[0007]

【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、例えばZMR法で再結晶化する時に研磨
ストッパーパターンが下地段差として存在するために、
再結晶化SOI層において研磨ストッパーパターン周辺
で結晶欠陥が発生したり、研磨ストッパーパターンは再
結晶化前に形成するため、再結晶化したあとは研磨スト
ッパーパターンにより素子レイアウトが制約されてしま
うという問題点を有していた。また研磨ストッパーパタ
ーンの無いSOI板を研磨により薄膜化する場合、SO
I層の膜厚を正確に制御できないという課題があった。
[Problems to be Solved by the Invention] However, in the above-mentioned configuration, since the polishing stopper pattern exists as a step on the base layer during recrystallization using the ZMR method, for example,
Problems include crystal defects occurring around the polishing stopper pattern in the recrystallized SOI layer, and because the polishing stopper pattern is formed before recrystallization, the device layout is restricted by the polishing stopper pattern after recrystallization. It had a point. In addition, when polishing an SOI plate without a polishing stopper pattern to make it thin, the SOI
There was a problem in that the thickness of the I layer could not be accurately controlled.

【0008】本発明は上記問題点に鑑み、研磨ストッパ
ーパターンを後から形成することでSOI層の結晶性に
悪影響を与えず、また研磨ストッパーパターンの無いS
OI基板をも膜厚の制御性よく薄膜化する半導体装置の
製造方法を提供することを目的とする。
In view of the above-mentioned problems, the present invention has been developed to form a polishing stopper pattern afterwards so as not to adversely affect the crystallinity of the SOI layer.
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which an OI substrate can also be thinned with good controllability of film thickness.

【0009】[0009]

【課題を解決するための手段】上記問題点を解決するた
めに本発明の半導体装置の製造方法は、第1のSiO2
膜を介して第1のSi膜を備えたSi基板において、フ
ォトマスク法とドライエッチにより前記第1のSi膜に
前記第1のSiO2膜表面が露出するように第1の開口
部を設ける工程と、熱酸化により前記第1のSi膜に第
2のSiO2膜を形成する工程と、前記第1の開口部に
おいて前記耐酸化マスク膜と前記第1のSiO2膜に前
記Si基板が露出しかつ前記第1の開口部より小さい第
2の開口部を設ける工程と、CVD法により前記第2の
開口部に選択的に第2のSi膜を成長させる工程と、熱
酸化により前記第2のSi膜に表面が少なくとも前記第
1のSiO2膜表面より高くなるように第3のSiO2
膜を形成する工程と、前記第1のSi膜表面の前記第2
のSiO2膜を除去する工程と、研磨板と研磨材を用い
て前記第1のSi膜の表面が前記第3のSiO2膜表面
とほぼ同じ高さになるまで前記第1のSi膜を研磨する
工程とを備えたものである。
[Means for Solving the Problems] In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a first SiO2
A step of providing a first opening in the first Si film so that the surface of the first SiO2 film is exposed by photomask method and dry etching in a Si substrate provided with a first Si film via the film. forming a second SiO2 film on the first Si film by thermal oxidation, and exposing the Si substrate to the oxidation-resistant mask film and the first SiO2 film in the first opening; a step of providing a second opening smaller than the first opening; a step of selectively growing a second Si film in the second opening by CVD; and a step of growing the second Si film by thermal oxidation. A third SiO2 layer is applied to the film so that the surface thereof is at least higher than the surface of the first SiO2 film.
a step of forming a film; and a step of forming a film on the surface of the first Si film.
and polishing the first Si film using a polishing plate and an abrasive material until the surface of the first Si film is approximately at the same height as the surface of the third SiO film. It is equipped with a process.

【0010】0010

【作用】本発明は上記した構成によって、SOI層の形
成後に研磨ストッパーパターンを形成するためにSOI
層の結晶性に影響を与えず、また研磨ストッパーパター
ンの無い厚膜SOIに後から研磨ストッパーパターンを
形成して薄膜化することが可能となる。
[Operation] According to the above-described structure, the present invention uses an SOI layer to form a polishing stopper pattern after forming an SOI layer.
This does not affect the crystallinity of the layer, and it is possible to form a polishing stopper pattern later on a thick film SOI without a polishing stopper pattern to make the film thinner.

【0011】[0011]

【実施例】以下本発明の一実施例の半導体装置の製造方
法について、図面を参照しながら説明する。図1,図2
は本発明の請求項1記載の半導体装置の製造方法を示す
工程断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. Figure 1, Figure 2
1A and 1B are process cross-sectional views showing a method for manufacturing a semiconductor device according to claim 1 of the present invention.

【0012】図1において、1はSi基板、2は第1の
SiO2膜、3は第1のSi膜、4は第1の開口部、5
は第2のSiO2膜、6は耐酸化マスク膜である。
In FIG. 1, 1 is a Si substrate, 2 is a first SiO2 film, 3 is a first Si film, 4 is a first opening, and 5 is a first SiO2 film.
6 is a second SiO2 film, and 6 is an oxidation-resistant mask film.

【0013】図1(a)では、第1のSiO2膜2を介
して第1のSi膜3を備えたSi基板、すなわちSOI
基板の断面図である。このSOI基板はZMR法や貼合
わせ法やSIMOX法などを用いて形成したものであり
、第1のSiO2膜2の膜厚は0.2μmから2μm程
度、第1のSi膜3の膜厚は0.1μmから4μm程度
とする。
In FIG. 1(a), a Si substrate, ie, an SOI substrate, is provided with a first Si film 3 via a first SiO2 film 2.
FIG. 3 is a cross-sectional view of the substrate. This SOI substrate is formed using a ZMR method, a bonding method, a SIMOX method, etc., and the film thickness of the first SiO2 film 2 is about 0.2 μm to 2 μm, and the film thickness of the first Si film 3 is The thickness is approximately 0.1 μm to 4 μm.

【0014】このような構造のSOI基板に図1(b)
に示すように第1のSiO2膜2表面が露出するように
第1の開口部4をフォトマスクとドライエッチ法により
形成する。第1の開口部4の形状は限定されるものでは
ないが、例えば格子状に形成すると後の研磨に都合が良
い。格子の1辺は数10μmから数100μmが適当で
ある。また幅は数μmから数10μm程度とする。
FIG. 1(b) shows an SOI substrate having such a structure.
As shown in FIG. 2, a first opening 4 is formed using a photomask and dry etching method so that the surface of the first SiO2 film 2 is exposed. Although the shape of the first opening 4 is not limited, for example, forming it in a lattice shape is convenient for later polishing. Appropriately, one side of the grating is several tens of micrometers to several hundred micrometers. Further, the width is approximately several μm to several tens of μm.

【0015】次に図1(c)に示すように熱酸化により
第1のSi膜3に第2のSiO2膜5を形成し、その後
耐酸化マスク膜6として例えばCVD−SiN膜を堆積
する。第2のSiO2膜5の膜厚は2nmから100n
m程度、SiN膜の膜厚は10nmから200nm程度
とする。
Next, as shown in FIG. 1C, a second SiO2 film 5 is formed on the first Si film 3 by thermal oxidation, and then a CVD-SiN film, for example, is deposited as an oxidation-resistant mask film 6. The thickness of the second SiO2 film 5 is from 2 nm to 100 nm.
The thickness of the SiN film is approximately 10 nm to 200 nm.

【0016】次に図1(d)に示すようにフォトマスク
とドライエッチ法により、第1の開口部4の中にSi基
板1が露出するように第2の開口部7を形成する。第2
の開口部7の形状は第1の開口部4の形状に準じるが、
その幅は第1の開口部4より数μm程度狭くする。
Next, as shown in FIG. 1D, a second opening 7 is formed using a photomask and dry etching so that the Si substrate 1 is exposed in the first opening 4. As shown in FIG. Second
The shape of the opening 7 is similar to the shape of the first opening 4, but
The width thereof is made narrower than the first opening 4 by several μm.

【0017】次に図1(e)に示すように第2の開口部
7にCVD法により選択的に第2のSi膜8を形成する
。この第2のSi膜8の膜厚は最終的に第1のSi膜3
の膜厚をいくらに設定するかで変わってくるが、ここで
は第1のSiO2膜2と同じ膜厚とする。すなわち第1
のSiO2膜2と第2のSi膜8の表面が同じ高さにな
るようにする。
Next, as shown in FIG. 1(e), a second Si film 8 is selectively formed in the second opening 7 by CVD. The film thickness of this second Si film 8 is finally the same as that of the first Si film 3.
The thickness of the first SiO2 film 2 is set to be the same as that of the first SiO2 film 2, although the thickness of the first SiO2 film 2 is determined here. That is, the first
The surfaces of the SiO2 film 2 and the second Si film 8 are made to be at the same height.

【0018】次に図2(a)に示すように第2のSi膜
8に熱酸化により第3のSiO2膜9を形成する。第3
のSiO2膜9の膜厚は、第1のSi膜3の目標膜厚や
第1のSiO2膜2や第2のSi膜8の膜厚によって変
わるが、本実施例のように第1のSiO2膜2と第2の
Si膜8の膜厚が等しい場合には(数1)で表わされる
Next, as shown in FIG. 2(a), a third SiO2 film 9 is formed on the second Si film 8 by thermal oxidation. Third
The film thickness of the SiO2 film 9 varies depending on the target film thickness of the first Si film 3 and the film thicknesses of the first SiO2 film 2 and the second Si film 8. When the film thicknesses of the film 2 and the second Si film 8 are equal, it is expressed by (Equation 1).

【0019】[0019]

【数1】 (数1)は、熱酸化SiO2膜界面が初期Si膜表面に
対して下方向にSiO2膜膜厚の45%もぐり、上方向
に55%上がることより導かれる。例えば第1のSi膜
3の目標膜厚が50nmとすると、第2のSi膜8に9
0.9nmの熱酸化膜すなわち第3のSiO2膜9を形
成することになる。
Equation (1) is derived from the fact that the thermally oxidized SiO2 film interface subsides by 45% of the SiO2 film thickness downward and rises by 55% upward relative to the initial Si film surface. For example, if the target thickness of the first Si film 3 is 50 nm, the second Si film 8 has a thickness of 9 nm.
A thermal oxide film, that is, a third SiO2 film 9 of 0.9 nm is formed.

【0020】次に図2(b)に示すようにフォトマスク
工程により第3のSiO2膜9が隠れるようにレジスト
10を残す。
Next, as shown in FIG. 2(b), a resist 10 is left so as to hide the third SiO2 film 9 by a photomask process.

【0021】次に図2(c)に示すようにウェットエッ
チあるいはドライエッチのより耐酸化マスク膜6及び第
2のSiO2膜5を除去する。
Next, as shown in FIG. 2C, the oxidation-resistant mask film 6 and the second SiO2 film 5 are removed by wet etching or dry etching.

【0022】次に図2(d)に示すように研磨板11と
研磨材を用いて第1のSi膜3を研磨し薄膜化する。研
磨材としてはSiの研磨速度が非常に早くSiO2に対
して非常に遅いもの、たとえばアミン系水溶液を用いる
。このように第1のSi膜をどんどん薄くしていくと第
3のSiO2膜9の表面が研磨板11に接するようにな
る(図2e参照)。するとSiO2膜の研磨速度が非常
に遅いためこれ以上研磨が進まなくなり、第1のSi膜
の研磨も自動的に停止する。最終的に第1のSi膜3の
膜厚は第3のSiO2膜9の表面の高さと第1のSiO
2膜2の表面の高さの差に等しくなるわけである。
Next, as shown in FIG. 2(d), the first Si film 3 is polished using a polishing plate 11 and an abrasive to make it thin. As the abrasive material, a material whose polishing speed is very fast for Si and very slow for SiO2 is used, such as an amine aqueous solution. As the first Si film is made thinner and thinner in this way, the surface of the third SiO2 film 9 comes into contact with the polishing plate 11 (see FIG. 2e). Then, since the polishing speed of the SiO2 film is very slow, the polishing cannot proceed any further, and the polishing of the first Si film also stops automatically. Finally, the thickness of the first Si film 3 is determined by the height of the surface of the third SiO2 film 9 and the thickness of the first SiO2 film 3.
This is equal to the difference in height between the surfaces of the two films 2.

【0023】研磨終了後は図3のようになり、薄膜化さ
れた第1のSi膜3にMOSトランジスタ等の半導体素
子を形成するわけである。
After polishing is completed, the result is as shown in FIG. 3, and semiconductor elements such as MOS transistors are formed on the thinned first Si film 3.

【0024】なお、SiO2膜以外の耐酸化マスク膜6
の形成は必ずしも必要ではなく、第3のSiO2膜9の
形成の時に第2のSiO2膜5が厚くなり第1のSi膜
が薄くなることを除けばその後は全く同じ工程である。
Note that the oxidation-resistant mask film 6 other than the SiO2 film
The formation of is not necessarily necessary, and the subsequent steps are exactly the same except that when forming the third SiO2 film 9, the second SiO2 film 5 becomes thicker and the first Si film becomes thinner.

【0025】[0025]

【発明の効果】以上のように本発明は、SOI層形成後
に研磨ストッパーパターンを設けることにより、SOI
層の結晶性に悪影響を与えず、また研磨ストッパーパタ
ーンを有していないSOI基板も研磨薄膜化することが
できる。
Effects of the Invention As described above, the present invention provides a polishing stopper pattern after forming an SOI layer.
It does not adversely affect the crystallinity of the layer, and even an SOI substrate that does not have a polishing stopper pattern can be polished into a thin film.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例における半導体装置の製造方
法の部分工程断面図である。
FIG. 1 is a partial process cross-sectional view of a method for manufacturing a semiconductor device in an embodiment of the present invention.

【図2】本発明の一実施例における半導体装置の製造方
法の部分工程断面図である。
FIG. 2 is a partial process cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図3】同実施例によって形成された半導体装置の断面
図である。
FIG. 3 is a cross-sectional view of a semiconductor device formed according to the same example.

【図4】従来例を説明する工程断面図である。FIG. 4 is a process sectional view illustrating a conventional example.

【符号の説明】[Explanation of symbols]

1  Si基板 2  第1のSiO2膜 3  第1のSi膜 4  第1の開口部 5  第2のSiO2膜 6  耐酸化マスク膜 7  第2の開口部 8  第2のSi膜 9  第3のSiO2膜 10  レシ゛スト 11  研磨板 1 Si substrate 2 First SiO2 film 3 First Si film 4 First opening 5 Second SiO2 film 6 Oxidation-resistant mask film 7 Second opening 8 Second Si film 9 Third SiO2 film 10 Recipe 11 Polishing plate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】第1のSiO2膜を介して第1のSi膜を
備えたSi基板において、フォトマスク法とドライエッ
チにより前記第1のSi膜に前記第1のSiO2膜表面
が露出するように第1の開口部を設ける工程と、熱酸化
により前記第1のSi膜に第2のSiO2膜を形成する
工程と、前記第1の開口部において前記耐酸化マスク膜
と前記第1のSiO2膜に前記Si基板が露出しかつ前
記第1の開口部より小さい第2の開口部を設ける工程と
、CVD法により前記第2の開口部に選択的に第2のS
i膜を成長させる工程と、熱酸化により前記第2のSi
膜に表面が少なくとも前記第1のSiO2膜表面より高
くなるように第3のSiO2膜を形成する工程と、前記
第1のSi膜表面の前記第2のSiO2膜を除去する工
程と、研磨板と研磨材を用いて前記第1のSi膜の表面
が前記第3のSiO2膜表面とほぼ同じ高さになるまで
前記第1のSi膜を研磨する工程とを備えた半導体装置
の製造方法。
1. In a Si substrate provided with a first Si film via a first SiO2 film, a surface of the first SiO2 film is exposed to the first Si film by a photomask method and dry etching. a step of forming a second SiO2 film on the first Si film by thermal oxidation; and a step of forming a second SiO2 film on the first Si film in the first opening; a step of providing a second opening in the film through which the Si substrate is exposed and which is smaller than the first opening; and selectively forming a second S into the second opening by a CVD method.
The step of growing an i film and thermal oxidation
forming a third SiO2 film on the film so that its surface is at least higher than the first SiO2 film surface; removing the second SiO2 film on the first Si film surface; and a polishing plate. and polishing the first Si film using an abrasive until the surface of the first Si film is approximately at the same height as the surface of the third SiO2 film.
JP1982091A 1991-02-13 1991-02-13 Manufacture of semiconductor device Pending JPH04258152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982091A JPH04258152A (en) 1991-02-13 1991-02-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982091A JPH04258152A (en) 1991-02-13 1991-02-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04258152A true JPH04258152A (en) 1992-09-14

Family

ID=12009956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982091A Pending JPH04258152A (en) 1991-02-13 1991-02-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04258152A (en)

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