JPH02237066A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make a Si layer of an element forming layer uniform in thickness by a method wherein grooves are provided to optional parts of the surface of a laminated wafer, the bases of the grooves are covered with an SiO2 film of a specified thickness, and the Si layer is polished. CONSTITUTION:One side of a laminated wafer 1 is etched, and the thickness of a remaining Si layer 3 is larger than that of an Si layer which is to be left as an element forming layer. An SiO2 film 2 is thoroughly removed, and grooves 4 are provided so deep as to make the Si face of the wafer 1 exposed, an oxidation resistant mask as a nitride film is provided to the surface of the film 3, Si of the groove base is thermally oxidized to form a SiO2 layer 5, and the thickness of the layer 5 is so set as to make its upside level with that of an Si element forming layer. When the wafer 1 provided with grooves on whose bases the SiO2 layer 5 has been formed is ethced using an amine etching solution, the SiO2 layer 5 serves as stopper for a ethced process to prevent the Si layer from being etched further and the Si layer becomes flat. By this setup, even if an Si layer is not uniform in thickness at the start of etching, it becomes uniform in thickness through its whole face at the end of etching.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to the formation of a so-called SOT substrate in which a semiconductor layer, which is an element formation layer, is deposited on an insulating substrate. The purpose of this method is to provide a method for manufacturing a type SOI substrate, in which a Si single crystal layer is polished to a thickness close to a predetermined thickness of an element formation layer according to a normal process for forming a bonded type SOI substrate.
Dig a groove in the polished Si layer, ? The structure includes a step of forming a SiO2 layer at the bottom of the groove and polishing it to reduce the thickness of the SiH layer to the same height as the surface of the SiO2 layer.

When the polishing of SiJl progresses to the same height as the SiO layer at the bottom of the groove, SiOt acts as a stopper, so the thickness of Si hardly decreases in this area, and the remaining thicker Si layer is polished. only will proceed. As a result, even if the thickness of the Si layer left after the initial polishing is non-uniform, the thickness of the Si layer, which is the element forming layer, will eventually become uniform over the entire wafer.

[Industrial application field]

The present invention relates to a substrate for forming an integrated circuit commonly referred to as SOI, and relates to a method for manufacturing an SOI substrate that allows a semiconductor layer of uniform thickness to be obtained.

Compared to fabricating an integrated circuit on a bulk semiconductor substrate, forming various elements on a thin semiconductor layer provided on an insulating material is more advantageous in terms of element characteristics and isolation between elements. From this point of view, an integrated circuit board as shown in FIG. 3 is desired. This is the Sol substrate.

In the drawing, 1 is a Si single crystal wafer, 2 is a Sing film, and 3 is a Si single crystal layer for forming elements. 1 is S
The support base that holds the iOz film 2 and the Si single crystal layer 3 is usually made of the same material as the element forming layer in order to avoid deformation and stress generation during heat treatment. is used.

? Prior Art] The usual manufacturing method of the above structure is shown in Figs. 4(a) to (C).
As shown in The manufacturing process will be described below with reference to the drawings.

(a) As shown in the figure, the surfaces of two single-crystal Si wafers are thermally oxidized to form an SiO2 film 2. When the SiOz films are held abutted against each other and heated, the two wafers are firmly bonded as shown in the figure. Subsequently, one of the bonded Si wafers is subjected to chemical/mechanical polishing to leave a thickness suitable for forming elements, resulting in an SOI substrate as shown in Figure (C).

The SOI substrate formed in this way has high performance L because the Si layer of the element formation layer has good quality comparable to that of bulk crystal.
It is attracting attention as a substrate for SI. In addition, the above chemistry
Mechanical polishing is a process of reducing friction by, for example, rubbing the Si surface with a polishing cloth while pouring an alkaline Si etching solution.

[Problem to be solved by the invention]

As described above, in the method of polishing one side of the bonded wafer, it is difficult to make the thickness of the portion to be left as the element forming layer uniform. Since most of the wafer, which is usually several hundred micrometers thick, is removed by polishing and a layer of 1 micrometer or less is left behind, the progress of polishing varies within the wafer surface, and the thickness of the Si layer left behind becomes unstable. This tends to result in uniformity, which lowers the manufacturing yield of SO2 substrates.

An object of the present invention is to provide an element formation layer in the formation of an SOI type substrate. The object of the present invention is to provide a processing method for making the thickness of SiQ uniform, thereby improving the manufacturing yield of SOI type IC substrates.

? Means for Solving the Problems] In order to achieve the above object, the present invention first includes a step of bonding two single crystal Si wafers with an oxide film interposed therebetween, and determining the thickness of one of the bonded Si wafers. a step of reducing the thickness and leaving a Si single crystal layer with a thickness not less than the thickness required for the element forming layer, a part of the Si layer whose thickness has been reduced and a part adjacent to the bottom surface of the Si layer; A step of selectively removing the oxide film and forming a trench whose width is larger than its depth; thermally oxidizing the Si exposed at the bottom of the trench to form silicon dioxide (S);
iOz)N and making the thickness of the SiO2 layer larger than the thickness of the insulating material layer;
polishing the single crystal layer to reduce its thickness and aligning its surface with the top surface of the S i O z layer deposited on the groove bottom surface.

? In the second aspect of the present invention, in the process of the first aspect, the depth of the groove formed in the Si layer with the reduced thickness is equal to the depth of the groove forming part of the Si layer with the reduced thickness. The SiO2 layer formed on the bottom surface of the groove is characterized by being formed by a deposition method.

? Effect] According to the present invention, grooves are provided at various places on the surface of the bonded wafer, and when the Si layer is polished with the bottom of the groove covered with a SiOz film having a predetermined thickness, the Si When the thickness of the layer decreases to the same height as the SiO2 film, polishing of the Si layer stops. This is because in treatments such as chemical and mechanical polishing, when Si etching solution is used, SiO
This is because ■ is hardly polished. That is, the thickness of sto. The JW will function as a polishing stopper.

On the other hand, in areas where the Si layer is thicker and the Siow film remains submerged in the Si layer, polishing of the Si progresses and the thickness of the Si layer continues to decrease further until the stopper is activated. Therefore, even if the thickness of the Si layer to be left as an element forming layer is non-uniform at the start of polishing Ig, it becomes uniform over the entire wafer surface at the end.

〔Example〕

FIGS. 1(a) to 1(e) are schematic cross-sectional views showing the steps of the first embodiment of the present invention, and the steps of the first embodiment will be explained below with reference to the drawings. The embodiment is claimed in claim (1).
This corresponds to the invention of

The figure (a) shows a state in which one side of the Si wafers bonded together is polished to reduce its thickness by a known process. At this point, the thickness of the remaining SiN3 is greater than the thickness of the Si layer to be left as an element forming layer. In particular, when there is non-uniformity in thickness due to the inclination of the polishing surface, even the thinnest part is required to be no less than the thickness of the element forming layer. In the figure, 1 is a Si wafer on the supporting side, and 2 is a SiO2 film, which is usually a thermally oxidized film.

? In this, grooves 4 are formed as shown in (b). Processing method is RIE
A commonly used method such as
is completely removed to the extent that the Si surface of the wafer 1 is exposed. Furthermore, in this example, the width of the groove is set to several tens of μm, while the depth of the groove is set to 10 μm even when the element forming layer is thick.
It cannot be larger than μm. As will become clear from the following description, in order to achieve the desired effect in the present invention, the width W of the groove needs to be sufficiently larger than the depth D, several times or more. Should be set to . This also applies to the second embodiment described later.

Next, as shown in (C), the Si at the groove bottom is thermally oxidized to form SiOz.
Form layer 5. The thickness of the layer is set to such a value that its upper surface coincides with the upper surface of the Si element forming layer. The thickness of S i O z formed by this thermal oxidation is uniform over the entire surface of the wafer and is not affected by the thickness of the Si layer 3 . Also,
Although not shown, an oxidation-resistant mask such as a nitride film is provided on the surface of the Si layer 3, so that the surface of the Si layer 3 is not oxidized, but the Si surface exposed on the sidewall of the trench is covered with SiO.
Will the Z layer grow? .

If the width of the groove is too narrow, this process will cause distortions and defects in the Si layer 3, and the thickness of the SiOf layer at the bottom of the groove may become non-uniform. Therefore, as mentioned above, it is necessary to make the width of the groove sufficiently large.

The wafer with the S i O z layer formed on the groove bottom is polished using an amine-based etching solution. In this process, Si
Since the polishing rates of Si and S i O z are significantly different,
As the polishing progresses, the S
The iO2 layer 5 acts as a stopper for the polishing process, and the Si layer is no longer polished. On the other hand, polishing continues in a portion where the Si layer remains thicker, as shown in the right half of the figure.

(e) As shown in the figure, Si
When the surfaces of the two N and S i 0 layers are aligned at the same height, polishing will no longer proceed and the polishing is terminated. Through the above processing, an SO₂ substrate is obtained.

The processing conditions for the above polishing may be the same as those for forming a normal Sol substrate, and the Sin layer formed on the side surface of the groove is
Although this is not preferable for the polishing process, since the area exposed to the polishing surface is small, it does not significantly impede the polishing of the Si surface.

The grooves forming the polishing stopper should be evenly distributed over the wafer surface, but if they are provided in the separation area for cutting the formed integrated circuit into chips, they can be distributed over the entire wafer surface without reducing the area of the element forming area. This can be said to be convenient as it will be evenly distributed.

Next, a second embodiment corresponding to claim (2) will be described. The steps of this embodiment are shown in FIGS. 2(a) to 2(C), and it is FIG. 2 that will be referred to in the following description.

In this embodiment as well, one side of the bonded Si wafers is polished in the same manner as in the formation of a normal Sol substrate, and grooves are formed in the same manner as in the first embodiment. This state is schematically shown in figure (a). The difference from the first embodiment is that in this embodiment, S
Although it is required that the i-layer not be left on the groove bottom, is it possible to expose the Si surface of wafer 1 on the groove bottom? There is no need to do so. In the etching process for digging trenches, the etching speed for Si and Sing is usually significantly different, so if the etching process is stopped when the Si layer is completely removed, (
a) The state shown in the figure will occur.

Next, by low pressure CVD method, S is deposited on the groove bottom as shown in (b).
Deposit iO■N6. Processing conditions are substrate temperature 500°C.
, the raw material is SiH. +O■, and the thickness of the deposited layer is the same as that of the Si element forming layer. This essentially makes the surface of the Sing layer and the surface of the Si element forming layer the same, but
The thickness of the deposited layer is set in this way because the S i O 2 layer 2 is hardly etched in the previous step.

The low pressure CVD method has good coating properties, so even with this process, the sides of the grooves can be coated with porridge. ``A SiOt layer of the same thickness is deposited.

As mentioned above, this is not preferable, but it does not interfere with subsequent processing, and the good thickness control accuracy is appreciated.

If it is desired to eliminate Sing from adhering to the side surfaces, a deposition method with poor coverage such as sputtering may be used.

Hereinafter, as in the first embodiment, by polishing, the SOI in figure (C) is
Get the board. In this polishing, the SiOzJm at the bottom of the groove acts as a stopper, as in the first embodiment, so that the thickness of the element forming layer becomes uniform over the entire wafer.

In the second embodiment, the width of the groove may be slightly smaller than that in the first embodiment, but in order for the S i O z layer formed at the bottom of the groove to function effectively as a stopper, the thickness must be increased. It is necessary to make the groove uniform over the entire surface of the wafer, and for this purpose, the width of the groove should not be too narrow, and as in the first embodiment, the width should be several times the depth. desirable.

If the polishing stopper is formed by deposition, the risk of distortion or defects occurring in the element forming layer, as would be the case when thermal oxidation is used, is eliminated, and an element forming layer with good crystallinity can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, the thickness of the element formation layer is uniform over the entire wafer, and the SO layer has good crystallinity.
An I-substrate can be reliably formed.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional diagram showing the steps of the first embodiment, FIG. 2 is a schematic cross-sectional diagram showing the steps of the second embodiment, and FIG. 3 is a schematic cross-sectional diagram showing the structure of a known SOI substrate. FIG. 4 is a schematic diagram showing the process of forming a conventional SOI substrate, in which 1 is a Si wafer, 2 is an SiO film, 3 is a single crystal Si layer, 4 is a groove, and 5 is a thermally oxidized SiOzN layer. , 6 C V D S i O t layer, schematic cross-sectional diagram showing the process of the first embodiment Figure 1 Schematic cross-sectional diagram showing the process of the second embodiment Figure 2 Schematic cross-sectional diagram showing the process of the second embodiment Figure 3

Claims (2)

[Claims] (1) A step of bonding two single-crystal Si wafers via an insulating material film, reducing the thickness of one of the bonded Si wafers so that the thickness does not fall below the thickness required for the element formation layer. selectively removing a portion of the Si layer whose thickness has been reduced and the insulating material film adjacent to the bottom surface of the portion of the Si layer, leaving a Si single crystal layer with a thickness smaller than that of the Si single crystal layer; The step of forming a groove with a large width is to thermally oxidize the Si exposed at the bottom of the groove to form silicon dioxide (S).
iO_2) layer and making the thickness of the SiO_2 layer larger than the thickness of the insulating material layer, reducing the thickness of the Si single crystal layer in which the groove is formed, and changing the position of its surface to the bottom surface of the groove. A method for manufacturing a semiconductor device, comprising the step of aligning the top surface of a SiO_2 layer deposited on the top surface of the SiO_2 layer. (2) In the method for manufacturing a semiconductor device according to claim (1),
The depth of the groove formed in the Si layer with the reduced thickness is a value that is not less than the thickness of the groove forming part of the Si layer with the reduced thickness, and the groove is formed on the bottom surface of the groove. A method for manufacturing a semiconductor device, characterized in that the SiO_2 layer is formed by a deposition method.