JPH03136346A - Manufacture of soi substrate - Google Patents

Manufacture of soi substrate

Info

Publication number
JPH03136346A
JPH03136346A JP27519389A JP27519389A JPH03136346A JP H03136346 A JPH03136346 A JP H03136346A JP 27519389 A JP27519389 A JP 27519389A JP 27519389 A JP27519389 A JP 27519389A JP H03136346 A JPH03136346 A JP H03136346A
Authority
JP
Japan
Prior art keywords
substrate
oxide film
film
element formation
element isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27519389A
Other languages
Japanese (ja)
Inventor
Toru Miyayasu
宮保 徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP27519389A priority Critical patent/JPH03136346A/en
Publication of JPH03136346A publication Critical patent/JPH03136346A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable an SOI substrate in even thickness of an Si layer not exceeding 1mum to be formed by a method wherein an element formation substrate and an oxide film are etched away from openings of a mask formed on the element formation substrate junctioned with a holding substrate through the oxide film while exposed parts are thermal-oxidized to form insulating films for element isolation to leave element isolation regions by grinding process. CONSTITUTION:A holding substrate (Si) 1 and an element formation substrate (Si) 3 are junctioned with each other through an oxide film (SiO2) 2. The substrate 3 is thinned by grinding process to form an element formation Si layer 8. When a mask 4 having openings 5 in the substrate 3 is formed while the substrate 3 and an oxide film 2 are etched away from the openings 5 to expose the holding substrate 1 for thermal-oxodizing the exposed parts, insulating films 6 for element isolation are formed and the surfaces of the films 6 jut out of the surface of the oxide film 2 but the level differences in respective openings 5 between the surfaces of the insulating film 6 and the surface of the oxide film 2 are equal to each other. When the substrate 3 is ground at much higher grinding rate than that of the insulating film 6, the grinding process can be almost stopped as soon as the insulating films 6 appear so that element formation regions 7 in even thickness isolated from the insulating films 6 may be formed.

Description

【発明の詳細な説明】 〔概要〕   。[Detailed description of the invention] 〔overview〕 .

SOI基板の製造方法に係り、特に張り合わせSOI基
板の製造方法に関し。
The present invention relates to a method of manufacturing an SOI substrate, particularly a method of manufacturing a bonded SOI substrate.

非常に薄くてしかも厚さの均一な素子形成領域を持つS
OI基板の提供を目的とし。
S with an extremely thin and uniform device formation area
The purpose is to provide OI substrates.

酸化膜を介して支持基板と素子形成基板を接合する工程
と、該素子形成基板上に開孔を有するマスクを形成し、
該開孔から該素子形成基板と該酸化膜をエツチングして
除去し該支持基板を露出する工程と、該露出部を熱酸化
して上面が該酸化膜の上面よりも上部に突き出る素子分
離絶縁膜を形成する工程と、該素子形成基板を研磨して
該素子分離絶縁膜と同一の高さとし、該素子分離絶縁膜
に隔てられた素子形成領域を残す工程とを含むSol基
板の製造方法により構成する。
a step of bonding a support substrate and an element formation substrate via an oxide film, and forming a mask having an opening on the element formation substrate,
A step of etching and removing the element formation substrate and the oxide film through the opening to expose the supporting substrate; and a step of thermally oxidizing the exposed portion so that the upper surface thereof protrudes above the upper surface of the oxide film. A method for manufacturing a Sol substrate, including a step of forming a film, and a step of polishing the element formation substrate to the same height as the element isolation insulating film, leaving an element formation region separated by the element isolation insulating film. Configure.

〔産業上の利用分野〕[Industrial application field]

本発明はS OI (Silicon on 1nsu
lator)基板の製造方法に係り、特に、張り合わせ
SOI基板の製造方法に関する。
The present invention is based on SOI (Silicon on Insu)
The present invention relates to a method of manufacturing a bonded SOI substrate, and particularly to a method of manufacturing a bonded SOI substrate.

Sol基板は、素子特性や素子間分離の点でバルク基板
よりすぐれており、その中でもバルクの結晶性が生かせ
る張り合わせ技術によるSO■基板が注目されている。
Sol substrates are superior to bulk substrates in terms of element characteristics and isolation between elements, and among them, SO2 substrates made of bonding technology that take advantage of bulk crystallinity are attracting attention.

張り合わせSO■基板は、素子形成領域となるSi層の
厚さをlam以下とする超薄膜SOI基板の得られる可
能性を持つものであるが、薄りてしかも均一な厚さの素
子形成領域を形成する信転性のある技術がまだ確立され
ていない。
The bonded SOI substrate has the possibility of obtaining an ultra-thin film SOI substrate in which the thickness of the Si layer that forms the element formation area is less than lam, but it is difficult to obtain an element formation area that is thin and has a uniform thickness. Reliable technology for formation has not yet been established.

〔従来の技術〕[Conventional technology]

第2図(a)乃至(c)は張り合わせSOI基板を作る
工程の例を従来例Iとして断面図で示すものである。
FIGS. 2(a) to 2(c) are cross-sectional views showing an example of the process of manufacturing a bonded SOI substrate as Conventional Example I.

表面に酸化膜11の形成されたSiウェハ1と表面に酸
化膜31の形成されたSiウェハ3の酸化膜同志を突き
合わせて重ねる(第2図(a))。
The oxide films of a Si wafer 1 having an oxide film 11 formed on its surface and a Si wafer 3 having an oxide film 31 formed on its surface are butted against each other and overlapped (FIG. 2(a)).

加熱して酸化膜同志を接合し酸化膜2を形成する(第2
図(b))。
The oxide films are bonded together by heating to form oxide film 2 (second
Figure (b)).

Siウェハ1を支持基板、 Siウェハ3を素子形成基
板とし、 Siウェハ3を研磨して薄膜化し、素子形成
Si層8を形成する(第2図(C))。
Using the Si wafer 1 as a supporting substrate and the Si wafer 3 as an element forming substrate, the Si wafer 3 is polished to become a thin film and an element forming Si layer 8 is formed (FIG. 2(C)).

ところで、支持基板や素子形成基板となるSiウェハの
厚さの場所によるばらつきを、1μm以下にすることは
通常極めて困難で、そのため2通常の研削技術、研磨技
術を用いて支持基板や素子形成基板を加工し、素子形成
Si層の厚さを1μm以下の厚さでしかも均一に形成す
ることは事実上不可能である。
By the way, it is usually extremely difficult to reduce the variation in the thickness of Si wafers, which are used as supporting substrates and element forming substrates, to 1 μm or less depending on the location. It is virtually impossible to form an element-forming Si layer with a thickness of 1 μm or less and with a uniform thickness.

第3図(a)乃至(d)は張り合わせSol基板を作る
工程の他の例を従来例■として断面図で示すものである
FIGS. 3(a) to 3(d) are cross-sectional views showing another example of the process of making a bonded Sol substrate as conventional example (2).

まず、素子形成基板となるSiウェハ3に、酸化膜31
とL OCOS (Local oxidation 
of 5ilicon)32とを形成する(第3図(a
))。
First, an oxide film 31 is placed on a Si wafer 3 that will become an element formation substrate.
and LOCOS (Local oxidation
of 5ilicon) 32 (Fig. 3(a)
)).

次に、LOGO3の突き出た部分を研磨することにより
、平坦化する(第3図(b))。
Next, the protruding portion of LOGO3 is polished to make it flat (FIG. 3(b)).

次に、支持基板となるSiウェハlの酸化膜11の形成
された面と平坦化されたLOGO3の面を突き合わせて
重ね、加熱接合する(第2図(C))。
Next, the surface of the Si wafer I serving as a support substrate on which the oxide film 11 is formed and the surface of the planarized LOGO 3 are butted against each other, overlapped, and bonded by heating (FIG. 2(C)).

Siウェハ3のLOGO3と反対側の面から研削を進め
てSiウェハ3を薄膜化し、さらにStは研磨されるが
SiO2は研磨されない研磨方法を用いて研磨し、LO
GO332で分離された素子形成領域7を形成する(第
3図(d))。
Grinding is performed from the side opposite to LOGO 3 of the Si wafer 3 to thin the Si wafer 3, and further polishing is performed using a polishing method in which St is polished but SiO2 is not polished, and LO
Element formation regions 7 separated by GO 332 are formed (FIG. 3(d)).

ところで、この場合も前述の従来例■と同様の理由によ
り、LOGO3を平坦化する時Siを露出させることな
く平坦化することが極めて難しい。
By the way, in this case as well, for the same reason as the above-mentioned conventional example (2), it is extremely difficult to flatten LOGO3 without exposing Si.

というのは9通常の研磨方法でLOGO332を研磨し
ようとすると酸化膜31も少しず研磨されてしまい、酸
化膜31は1μm以下の厚さであるので。
This is because if the LOGO 332 is polished using a normal polishing method, the oxide film 31 will also be polished away, and the thickness of the oxide film 31 is less than 1 μm.

酸化膜31を均一に残してLOGO332を完全に平坦
化することは9通常極めて困難であるからである(第3
図(b)参照)。
This is because it is usually extremely difficult to completely flatten the LOGO 332 while leaving the oxide film 31 uniformly (see the third example).
(See figure (b)).

さらに、研磨されたSiO□膜の表面は9面粗さが大き
いので張り合わせの接合強度が小さくなる。
Furthermore, since the surface of the polished SiO□ film has large surface roughness, the bonding strength of the bonding is reduced.

結局、 SiO□膜の表面を研磨することは、張り合わ
せSOI基板を作製する上で、望ましくない。
After all, polishing the surface of the SiO□ film is not desirable when producing a bonded SOI substrate.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

“従って、素子形成領域のSi層の厚さが1μm以下の
超薄膜SO■基板を従来の方法で作ることは。
“Therefore, it is impossible to make an ultra-thin SO2 substrate with a Si layer thickness of 1 μm or less in the element formation region using the conventional method.

極めて困難である。It is extremely difficult.

本発明は、素子形成領域のSi層の厚さが1μm以下で
しかも均一な超薄膜Sol基板を実現する新しい方法を
提供することを目的とする。
An object of the present invention is to provide a new method for realizing an ultra-thin Sol substrate in which the thickness of the Si layer in the element formation region is 1 μm or less and is uniform.

〔課題を解決するための手段〕[Means to solve the problem]

第1図(a)乃至(d)は本発明の詳細な説明するため
の断面図である。
FIGS. 1(a) to 1(d) are sectional views for explaining the present invention in detail.

上記課題は、酸化膜2を介して支持基板1と素子形成基
板3を接合する工程と、該素子形成基板3上に開孔5を
有するマスク4を形成し、該開孔5から、該素子形成基
板3と該酸化膜2をエツチングして除去し該支持基板1
を露出する工程と、該露出部を熱酸化して上面が該酸化
膜2の上面よりも上部に突き出る素子分離絶縁膜6を形
成する工程と、該素子形成基板3を研磨して該素子分離
絶縁膜6と同一の高さとし、該素子分離絶縁膜で隔てら
れた素子形成領域7を残す工程とを含むSol基板の製
造方法によって解決される。
The above-mentioned problems include the step of bonding the support substrate 1 and the element formation substrate 3 via the oxide film 2, the formation of a mask 4 having an opening 5 on the element formation substrate 3, and the formation of a mask 4 having an opening 5 through the opening 5. The forming substrate 3 and the oxide film 2 are etched and removed, and the supporting substrate 1 is removed.
a step of thermally oxidizing the exposed portion to form an element isolation insulating film 6 whose upper surface protrudes above the upper surface of the oxide film 2; and a step of polishing the element forming substrate 3 to isolate the element. This problem is solved by a method for manufacturing a Sol substrate, which includes a step of leaving an element formation region 7 that is at the same height as the insulating film 6 and separated by the element isolation insulating film.

〔作用〕[Effect]

本発明では、まず、支持基板1と素子形成基板3を酸化
膜2を介して接合する。支持基板1と素子形成基板3を
平坦に形成し、その表面に酸化膜を形成しておけば、接
合強度を大きくすることができ、しかも接合された酸化
膜2は平坦で均一な厚さに形成される。
In the present invention, first, the supporting substrate 1 and the element forming substrate 3 are bonded with the oxide film 2 interposed therebetween. By forming the supporting substrate 1 and the element forming substrate 3 flat and forming an oxide film on their surfaces, the bonding strength can be increased, and the bonded oxide film 2 is flat and has a uniform thickness. It is formed.

開孔下の支持基板lの露出部に形成される素子分離絶縁
膜6は、その上面が酸化膜2の上面よりも上部に突き出
るが、素子分離絶縁膜6の上面と酸化膜2の上面の高さ
の差は各開孔とも等しい。
The upper surface of the element isolation insulating film 6 formed on the exposed part of the support substrate l under the opening protrudes above the upper surface of the oxide film 2, but the upper surface of the element isolation insulating film 6 and the upper surface of the oxide film 2 are The difference in height is the same for each aperture.

次いで、素子形成基板3を研磨して、素子分離絶縁膜6
と同一の高さとするのであるが、その際。
Next, the element formation substrate 3 is polished to form an element isolation insulating film 6.
In this case, the height is the same as that of .

素子形成基板2に対する研磨速度が素子分離絶縁膜6に
対する研磨速度よりも迩かに大きい研磨方法を用いれば
、素子分離絶縁膜6が現出した時点で研磨がほぼストッ
プし、素子分離絶縁膜6に隔てられた均一な厚さの素子
形成領域7が形成される。
If a polishing method is used in which the polishing rate for the element formation substrate 2 is much higher than the polishing rate for the element isolation insulating film 6, the polishing will almost stop when the element isolation insulating film 6 appears, and the element isolation insulating film 6 will be removed. Element forming regions 7 of uniform thickness are formed.

〔実施例〕〔Example〕

第1図(a)乃至(d)は本発明の詳細な説明するため
の断面図であり、lは支持基板であってSiウェハ、2
は酸化膜であってSin、膜、3は素子形成基板であっ
てSiウェハ、4はマスク、5は開孔。
FIGS. 1(a) to 1(d) are cross-sectional views for explaining the present invention in detail, and 1 is a support substrate, and 2 is a Si wafer.
3 is an oxide film, which is a Si film; 3 is an element forming substrate, which is a Si wafer; 4 is a mask; and 5 is an opening.

6は素子分離絶縁膜あってSiO□膜、7は素子形成領
域、8は素子形成Si層を表す。
Reference numeral 6 represents an element isolation insulating film, which is a SiO□ film, 7 represents an element forming region, and 8 represents an element forming Si layer.

以下、これらの図を参照しながら説明する。The following description will be made with reference to these figures.

第1図(a)参照 支持基板1として表面に厚さ0.25μmのSiO□膜
の形成された厚さ0.6 m++wのSiウェハ、素子
形成基板3として表面に厚さ0.25μmの5iO1膜
の形成された厚さ0.6 +amのSiウェハを使用し
て1両者を重ねて加熱接合する。これにより、支持基板
lと素子形成基板3の間には厚さ0.5μmのSing
膜2が介在するようになる。
FIG. 1(a) Reference support substrate 1 is a 0.6 m++w Si wafer with a 0.25 μm thick SiO□ film formed on the surface, element forming substrate 3 is a 0.25 μm thick 5iO1 surface. Using Si wafers having a thickness of 0.6 +am on which a film has been formed, they are stacked one on top of the other and bonded together by heating. As a result, there is a Sing with a thickness of 0.5 μm between the support substrate l and the element formation substrate 3.
Membrane 2 becomes interposed.

第1図(b)参照 素子形成基板3を研削することにより、2μmまで薄(
して素子形成Si層8を形成する。
By grinding the reference element forming substrate 3 shown in FIG. 1(b), the thickness is reduced to 2 μm (
Then, an element-forming Si layer 8 is formed.

素子形成Si層8の上に1.2μm幅の開孔5を有する
厚さ0.1zmのSiNのマスク4を形成する。
A SiN mask 4 having a thickness of 0.1 zm and having an opening 5 having a width of 1.2 μm is formed on the element-forming Si layer 8 .

開孔5から素子形成Si層8及びSiO□膜2をエツチ
ングして除去し、支持基板lを露出させる。
The element forming Si layer 8 and the SiO□ film 2 are etched and removed through the opening 5 to expose the support substrate l.

第1図(c)参照 支持基板lを熱酸化して、開孔部に5i(h膜の素子分
離絶縁膜6を形成する。熱酸化により2体積が増加して
素子分離絶縁膜6は上方に盛り上がるが、その上面は元
の支持基板1面より約1μm上に来るような条件で熱酸
化する。これにより、素子分離絶縁膜6の上面はSiO
□膜2の上面より0.5μm高(なる。
Referring to FIG. 1(c), the supporting substrate l is thermally oxidized to form an element isolation insulating film 6 of 5i (h film) in the opening.Thermal oxidation increases the volume by 2, and the element isolation insulating film 6 is directed upward. However, it is thermally oxidized under conditions such that its upper surface is approximately 1 μm above the original surface of the supporting substrate 1. As a result, the upper surface of the element isolation insulating film 6 becomes SiO
□0.5 μm higher than the top surface of the membrane 2.

第1図(d)参照 研磨剤としてアミン系水溶液を用い、研磨布として発泡
ポリウレタンパッドを用いて素子形成Si層8を研磨す
る。アミン系水溶液はSiに対する研磨速度がSing
に対する研磨速度に比べて10’倍以上大きい。
Referring to FIG. 1(d), the element-forming Si layer 8 is polished using an amine aqueous solution as the polishing agent and a foamed polyurethane pad as the polishing cloth. Amine-based aqueous solution has a polishing rate of Sing for Si.
The polishing rate is more than 10' times higher than that of the standard.

素子形成Si層8は表面から均一に除去されて行って、
素子分離絶縁膜6が現れた瞬点からはほとん2除去され
なくなる。これにより、 Si層の厚さが0.5amで
、厚さの均一な素子形成領域7が形成される。
The element forming Si layer 8 is uniformly removed from the surface.
From the moment when the element isolation insulating film 6 appears, it is almost no longer removed. As a result, an element formation region 7 is formed in which the Si layer has a thickness of 0.5 am and has a uniform thickness.

かくして、lam以下の均一な厚さの素子形成領域7.
を持つ超薄膜Sol基板が作製できる。
Thus, the device formation region 7. has a uniform thickness of less than lam.
It is possible to fabricate an ultra-thin film Sol substrate with

なお、素子分離絶縁膜6が現れた時点でStの研磨を停
止させるためには、開孔5の幅は0.5μm以上あるこ
とが必要である。本実施例では開孔5の幅は1.2μm
で、素子形成領域7の厚さを0.5μmプラスマイナス
0.02μmに抑えることができた。
Note that in order to stop the polishing of St when the element isolation insulating film 6 appears, the width of the opening 5 needs to be 0.5 μm or more. In this example, the width of the opening 5 is 1.2 μm.
Thus, the thickness of the element forming region 7 could be suppressed to 0.5 μm plus or minus 0.02 μm.

〔発明の効果〕〔Effect of the invention〕

以上説明したように:本発明によれば、厚さが1μm以
下で均一な厚さの素子形成領域を持ち。
As described above, according to the present invention, the device has an element formation region with a uniform thickness of 1 μm or less.

しかも、張り合わせの接合強度が大きいSO1基板を提
供することができる。
Furthermore, it is possible to provide an SO1 substrate with high bonding strength.

本発明は張り合わせSOI基板の製造の歩留りの向上と
、それを用いるデバイスの性能向上に寄与するところが
大きい。
The present invention greatly contributes to improving the manufacturing yield of bonded SOI substrates and improving the performance of devices using the same.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)乃至(d)は実施例を説明するための断面
図。 第2図(a)乃至(c)は従来例Iを説明するための断
面図。 第3図(a)乃至(d)は従来例■を説明するための断
面図 である。 図において。 1は支持基板であってSiウェハ。 2は酸化膜であってSiO□膜。 3は素子形成基板であってSiウェハ。 4はマスク。 5は開孔。 6は素子分離絶縁膜であってSiO□膜。 7は素子形成領域。 8は素子形成St層。 11は酸化膜であってSiO□膜。 31は酸化膜であってSiO□膜。 32はLOCO3 尖 s!、  例 系 1 図 檄 来  枦j 第 2 図
FIGS. 1(a) to 1(d) are sectional views for explaining an embodiment. FIGS. 2(a) to 2(c) are sectional views for explaining conventional example I. FIGS. 3(a) to 3(d) are sectional views for explaining conventional example (2). In fig. 1 is a supporting substrate, which is a Si wafer. 2 is an oxide film, which is a SiO□ film. 3 is an element forming substrate, which is a Si wafer. 4 is a mask. 5 is an open hole. 6 is an element isolation insulating film, which is a SiO□ film. 7 is an element forming area. 8 is an element forming St layer. 11 is an oxide film, which is a SiO□ film. 31 is an oxide film, which is a SiO□ film. 32 is LOCO3 cusp s! , Example series 1 Figure 2

Claims (1)

【特許請求の範囲】  酸化膜(2)を介して支持基板(1)と素子形成基板
(3)を接合する工程と、 該素子形成基板(2)上に開孔(5)を有するマスク(
4)を形成し、該開孔(5)から該素子形成基板(3)
と該酸化膜(2)をエッチングして除去し該支持基板(
1)を露出する工程と、 該露出部を熱酸化して上面が該酸化膜(2)の上面より
も上部に突き出る素子分離絶縁膜(6)を形成する工程
と。 該素子形成基板(2)を研磨して該素子分離絶縁膜(6
)と同一の高さにし、該素子分離絶縁膜(6)で隔てら
れた素子形成領域(7)を残す工程とを含むことを特徴
とするSOI基板の製造方法。
[Claims] A step of bonding a support substrate (1) and an element formation substrate (3) via an oxide film (2), and a mask (5) having an opening (5) on the element formation substrate (2).
4), and the element forming substrate (3) is formed through the opening (5).
The oxide film (2) is etched and removed, and the supporting substrate (2) is removed.
1); and a step of thermally oxidizing the exposed portion to form an element isolation insulating film (6) whose upper surface protrudes above the upper surface of the oxide film (2). The element forming substrate (2) is polished to form the element isolation insulating film (6).
) and leaving an element formation region (7) separated by the element isolation insulating film (6).
JP27519389A 1989-10-23 1989-10-23 Manufacture of soi substrate Pending JPH03136346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27519389A JPH03136346A (en) 1989-10-23 1989-10-23 Manufacture of soi substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27519389A JPH03136346A (en) 1989-10-23 1989-10-23 Manufacture of soi substrate

Publications (1)

Publication Number Publication Date
JPH03136346A true JPH03136346A (en) 1991-06-11

Family

ID=17551979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27519389A Pending JPH03136346A (en) 1989-10-23 1989-10-23 Manufacture of soi substrate

Country Status (1)

Country Link
JP (1) JPH03136346A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5449638A (en) * 1994-06-06 1995-09-12 United Microelectronics Corporation Process on thickness control for silicon-on-insulator technology
WO1997043676A1 (en) * 1996-05-16 1997-11-20 Bookham Technology Limited Assembly of an optical component and an optical waveguide
EP1120672A1 (en) * 2000-01-25 2001-08-01 Corning Incorporated Self-alignment hybridization process and component
JP2004040093A (en) * 2002-07-05 2004-02-05 Samsung Electronics Co Ltd Soi wafer and method of manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5449638A (en) * 1994-06-06 1995-09-12 United Microelectronics Corporation Process on thickness control for silicon-on-insulator technology
WO1997043676A1 (en) * 1996-05-16 1997-11-20 Bookham Technology Limited Assembly of an optical component and an optical waveguide
US5991484A (en) * 1996-05-16 1999-11-23 Harpin; Arnold Peter Roscoe Assembly of an optical component and an optical waveguide
EP1120672A1 (en) * 2000-01-25 2001-08-01 Corning Incorporated Self-alignment hybridization process and component
US6621961B2 (en) 2000-01-25 2003-09-16 Corning Incorporated Self-alignment hybridization process and component
JP2004040093A (en) * 2002-07-05 2004-02-05 Samsung Electronics Co Ltd Soi wafer and method of manufacturing the same

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