JPH03284871A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a highly intelligent and integrated semiconductor device by arranging piezo-resistance layers on a high-device-characteristic single-crystal silicon substrate and arranging bipolar transistors on a high-device-characteristic epitaxial layer. CONSTITUTION:A single-crystal silicon substrate 3 having a face 110 is joined to the smooth face of the single-crystal silicon substrate 2, which has a face 111, of a semiconductor pressure sensor with a part of the smooth face exposed, an epitaxial layer 8 is formed on the smooth face of the substrate 2, and the predetermined quantity of the layer 8 is removed to expose the layer 8 acting as bipolar transistor formation regions and the substrate 3 acting as piezo- resistance layer formation regions, with the surface smooth. As a result, a semiconductor pressure sensor which has the layer 8 exposed on the surface of the substrate, having the face 111, and acting as bipolar transistor formation regions and has the substrate 3 exposed on the surface of the substrate, having the face 110 with different face azimuth from the layer 8, and acting as piezo- resistance layer formation regions can be manufactured.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Prior Art and Problems] In recent years, integrated circuit devices have been required to be highly integrated and intelligent, but no device has appeared that satisfies these demands.

An object of the present invention is to provide a semiconductor device that is highly intelligent and highly integrated.

[Means for Solving the Problems] A first invention includes a first single crystal silicon portion exposed on the substrate surface and serving as a first element formation region, and a first single crystal silicon portion exposed on the substrate surface,
The gist of the semiconductor device is a semiconductor device including a second single-crystal silicon portion having a plane orientation different from that of the first single-crystal silicon portion and serving as a second element formation region.

A second aspect of the invention is to apply a second surface orientation to a smooth surface of a first single crystal silicon substrate having a first surface orientation, with a part of the smooth surface of the first single crystal silicon substrate being exposed. a second step of forming an epitaxial layer on the smooth surface of the first single crystal silicon substrate; and a second step of forming an epitaxial layer on the smooth surface of the first single crystal silicon substrate. a third step of exposing the epitaxial layer, which will become a first element formation region, and the second single crystal silicon substrate, which will become a second element formation region, in a smooth state. The gist is the method.

A third invention is a semiconductor in which a silicon oxide film is formed on the exposed portion of the second single crystal silicon substrate in the first step of the second invention, and an epitaxial layer is formed in the second step in this state. The gist is the manufacturing method of the device.

[Operation] The first invention provides a semiconductor device with excellent device characteristics by selecting the orientation planes of the first and second single crystal silicon portions according to the first and second devices.

That is, for example, when the first element is a bipolar transistor and the second element is a MOS transistor, the first
An integrated circuit device having excellent transistor characteristics can be obtained by forming the first single-crystal silicon portion with a <111> plane and by forming the first single-crystal silicon portion with a <100> plane.

The second invention provides a second invention in which a part of the smooth surface of the first single crystal silicon substrate is exposed to the smooth surface of the first single crystal silicon substrate having the first surface orientation in the first step. A second single crystal silicon substrate having a surface orientation of is bonded, an epitaxial layer is formed on the smooth surface of the first single crystal silicon substrate in a second step, and a predetermined amount of the epitaxial layer is removed in a third step. the epitaxial layer which becomes a first element formation region with a smooth surface;
The second single-crystal silicon substrate, which will become the second element formation region, is exposed. As a result, the semiconductor device of the first invention is manufactured.

In the third invention, in the first step of the second invention, a silicon oxide film is formed on the exposed portion of the second single crystal silicon substrate, and in this state, the epitaxial layer is formed in the second step. An epitaxial layer is formed only on the first single-crystal silicon substrate, and there is no disturbance in crystal orientation.

[First Embodiment] A first embodiment in which the present invention is embodied in a semiconductor pressure sensor will be described with reference to the drawings.

FIG. 1 shows a semiconductor pressure sensor, and FIGS. 2 to 7 show its manufacturing method.

As shown in FIG. 2, a single crystal silicon substrate 1 having a <100> plane orientation and a P-type single crystal silicon substrate 2 (first single crystal silicon substrate) having a <111> plane orientation are prepared. , a single crystal silicon substrate 2 is directly bonded to the surface of a single crystal silicon substrate 1. Then, the surface of the single crystal silicon substrate 2 is mirror polished to a predetermined thickness.

Next, as shown in FIG. 3, a single crystal silicon substrate 3 (second single crystal silicon substrate) having an N-type <110> plane orientation is directly bonded to the surface of the single crystal silicon substrate 2. Then, the surface of the single crystal silicon substrate 3 is mirror-polished to a predetermined thickness. Subsequently, the element formation region (diaphragm formation region) of the single crystal silicon substrate 3 is formed using trench technology.
A groove 4 having a width of 1.5 μm is formed around A. That is, a silicon oxide film 5 is formed on the surface of a single crystal silicon substrate 3,
A mask pattern is formed using an ordinary photolithography technique, and a groove 4 is formed as a trench to reach the bonding surface with the single crystal silicon substrate 2.

Thereafter, using this silicon oxide film 5 as a mask, P type impurities are diffused to form a P+ diffusion layer 6 in the groove 4. This P+
The diffusion layer 6 electrically isolates a piezoresistive layer and peripheral elements, which will be described later.

Next, as shown in FIG. 4, a silicon oxide film 7 with a thickness of 1 μm is formed on the surface of the single crystal silicon substrate 3 including the inside of the groove 4 by thermal oxidation. At this time, since the inner wall of the trench 4 is oxidized from both sides, the inside of the trench 4 is covered with silicon oxide film 7 due to thermal oxidation.
filled with. Also, the thickness of the single crystal silicon substrate 3 is 5μ.
It becomes m.

Then, as shown in FIG. 5, the silicon oxide film 7 on the single crystal silicon substrate 3 other than the element formation region A is removed by photolithography. Furthermore, using the remaining silicon oxide film 7 in the element forming area A as an etching mask, the single crystal silicon substrate 3 other than the element forming area A is etched with an alkaline solution such as KOH or EPW. At this time, the etching rate of the alkali etching differs depending on the plane orientation of the silicon; for example, the etching rate for the <111> plane is several hundredths of that for the <100> plane. As a result, etching stops when the single crystal silicon substrate 2 is exposed.

Note that when bonding the single-crystal silicon substrate 2 and the single-crystal silicon substrate 3, a silicon oxide film may be formed at the bonding interface, and the bonding may be performed via this silicon oxide film. In this case, the etching of the single crystal silicon substrate 3 is also stopped due to the exposure of the silicon oxide film.

Next, as shown in FIG. 6, an N-type epitaxial layer 8 is formed on the single crystal silicon substrate 2 to a thickness of 10 μm or more. Thereafter, as shown in FIG. 7, a predetermined amount of the surface of the epitaxial layer 8 is removed by mirror polishing to expose the silicon oxide film 7 with a smooth surface.

After that, as shown in FIG.
The silicon oxide film 7 on the upper surface is removed with hydrofluoric acid, and the upper surface of the epitaxial layer 8 is polished to make the upper surface of the single crystal silicon substrate 3 and the upper surface of the epitaxial layer 8 flush with each other. After that, K is applied from the back side of the single crystal silicon substrate l.
Anisotropic etching is performed using an etching solution such as OH to form a diaphragm of single crystal silicon substrates 2 and 3. Then, four piezoresistive layers 9 are formed on the single crystal silicon substrate 3 (diaphragm) to form a bridge circuit. Furthermore, peripheral circuits such as a temperature compensation circuit made of bipolar transistors 10 and 11 are formed in the epitaxial layer 8. Furthermore, the wiring layer 12 and the like are formed to complete the semiconductor pressure sensor.

When measuring pressure, the pressure applied to the diaphragm is electrically converted by the piezoresistive layer 9, temperature-compensated and amplified by a peripheral circuit including bipolar transistors to, 11, and taken out.

In this way, in the semiconductor pressure sensor of this example, <
111> plane (first plane orientation) with a part of the smooth surface of the single crystal silicon substrate 2 exposed to the smooth surface of the single crystal silicon substrate 2 (first single crystal silicon substrate).
A single crystal silicon substrate 3 (second single crystal silicon substrate) having a 110> plane (second plane orientation) is bonded (first step), and an epitaxial layer 8 is formed on the smooth surface of the single crystal silicon substrate 2. 2nd step), further, a predetermined amount of the epitaxial layer 8 is removed to expose the epitaxial layer 8, which will become the bipolar transistor formation region, and the single crystal silicon substrate 3, which will become the piezoresistive layer formation region, with a smooth surface. (3rd step).

As a result, the <111> plane epitaxial layer 8 (first single crystal silicon portion) exposed on the substrate surface and serving as a bipolar transistor formation region is different from the <111> plane orientation of the epitaxial layer 8 exposed on the substrate surface. has a 110> face,
In addition, a semiconductor pressure sensor is manufactured, which includes a single crystal silicon substrate 3 (second single crystal silicon portion) serving as a piezoresistive layer formation region.

In this device, a piezoresistive layer 9 is formed on a <110> plane single crystal silicon substrate 3, and a <110>
Bipolar transistors 10 and 11 can be formed in the epitaxial layer 8 on the 1> plane.

That is, the piezoresistive layer 9 has excellent device characteristics and is 11O
> bipolar transistor 10
．． 11 can be arranged on the <111> plane, which has excellent device characteristics.

In this way, the best performance of each element of the piezoresistive layer and the peripheral circuit (bipolar transistor) can be brought out, and a semiconductor device with excellent intelligence and high integration can be obtained.

Further, a silicon oxide film 7 is formed on the exposed portion of the single crystal silicon substrate 3.
Since the epitaxial layer 8 was formed in this state, the epitaxial layer 8 of only the single-crystal silicon substrate 2 was formed, and the crystal orientation was not disturbed. In other words, if there is no silicon oxide film 7, during the epitaxial growth from the <111> single crystal silicon substrate 2, <110>
Although the epitaxial layer grown from the single crystal silicon substrate 3 of > is mixed together and the quality of the crystal deteriorates, this example avoids such a problem.

Furthermore, as shown in FIG. 8, conventionally, when forming a diaphragm using anisotropic etching, it was not possible to form a square diaphragm with good controllability by etching the <110> plane. Since it is single crystal silicon with a <100> plane orientation, it is possible to form a square diaphragm portion by etching with good controllability.

[Second Embodiment] Next, a second embodiment will be described with reference to FIGS. 9 to 16. The semiconductor pressure sensor of this embodiment does not require very high integration, and the process is simplified by not using the silicon oxide film 7 that covers the exposed portion of the single crystal silicon substrate 3 in the first embodiment. We are trying to

As shown in FIG. 9, a P-type single crystal silicon substrate 13 (first single crystal silicon substrate) having a <111> plane orientation
In addition, as shown in Figure 10, <100
> A single crystal silicon substrate 14 having a plane orientation is prepared.

Then, as shown in FIG. 11, a single crystal silicon substrate 1
A single crystal silicon substrate 13 is directly bonded to the surface of 4.

Then, the surface of the single crystal silicon substrate 13 is mirror polished to a predetermined thickness.

Next, as shown in FIG.
An N-type single crystal silicon substrate 15 (second single crystal silicon substrate) having <110> plane orientation is directly bonded to the surface of the substrate. Then, the surface of the single crystal silicon substrate 15 is mirror polished to a predetermined thickness.

Subsequently, as shown in FIG. 13, the single crystal silicon substrate 15 is etched except for the element formation region (diaphragm formation region) of the single crystal silicon substrate 15. Next, the 14th
As shown in the figure, an N-type epitaxial layer 16 is formed on a single crystal silicon substrate 13. Thereafter, as shown in FIG. 15, a predetermined amount of the surface of the epitaxial layer 16 is removed by mirror polishing to expose the single crystal silicon substrate 15 with a smooth surface.

Thereafter, as shown in FIG. 16, anisotropic etching is performed from the back side of the single crystal silicon substrate 14 using an etching solution such as KOH to form a diaphragm of the single crystal silicon substrates 13 and 15. Then, four piezoresistive layers 17 are formed on the single crystal silicon substrate 15 (diaphragm) to form a bridge circuit. Further, peripheral circuits such as a temperature compensation circuit including bipolar transistors 18 and 19 are formed in the epitaxial layer 16. Furthermore, the wiring layer 20 and the like are formed to complete the semiconductor pressure sensor.

[Third Example] Next, a third example will be described with reference to FIGS. 17 to 25.

First, as shown in FIG. 17, an N-type single-crystal silicon substrate 21 having a <110> plane orientation is prepared, and an uneven portion of a predetermined depth is formed on its surface. The depth of the uneven portion determines the thickness of the diaphragm of the semiconductor pressure sensor. On the other hand, a single crystal silicon substrate 22 having a <100> plane orientation shown in FIG. 18 is prepared. Then, as shown in FIG. 19, the uneven surface of the single crystal silicon substrate 21 is directly bonded to the surface of the single crystal silicon substrate 22. Then, as shown in FIG.

Next, as shown in FIG. 20, a silicon oxide film 23 is formed on the opposing surfaces of the single crystal silicon substrate 22 and the single crystal silicon substrate 21 by thermal oxidation. Then, as shown in FIG. 21, the upper surface side of the single crystal silicon substrate 21 is polished until the silicon oxide film 23 is exposed. Next, as shown in FIG. 22, after removing the silicon oxide film 23, a silicon oxide film 24 is formed on the upper surface of the single crystal silicon substrate 21.

Subsequently, as shown in FIG. 23, an N-type epitaxial layer 25 is formed on the upper surface of the single crystal silicon substrate 22.

Thereafter, as shown in FIG.
A predetermined amount of the surface is removed to expose the silicon oxide film 24 with a smooth surface. Thereafter, as shown in FIG. 25, a peripheral circuit including a diaphragm 26, a piezoresistive layer 27, MOS transistors 28, 29, etc. is formed.

In this way, in this embodiment, in a semiconductor pressure sensor including MOS transistors 28 and 29 in the peripheral circuit, the MOS transistors 28 and 29 are used.
An epitaxial layer 25 having a <100> plane orientation, which is advantageous in terms of S transistor characteristics, can be used.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and for example, although the embodiments are embodied in semiconductor pressure sensors, they may be embodied in other semiconductor devices.

[Effects of the Invention] As described in detail above, the present invention exhibits excellent effects that can provide a semiconductor device that is highly intelligent and highly integrated.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the semiconductor pressure sensor of the first embodiment, and
7 to 7 are diagrams showing the manufacturing process thereof, FIG. 8 is a sectional view of a semiconductor pressure sensor for comparison, and FIGS. 9 to 16 are diagrams showing the manufacturing process of the semiconductor pressure sensor of the second embodiment. , 1st
7 to 25 are diagrams showing the manufacturing process of the semiconductor pressure sensor of the third embodiment. 2 is a single crystal silicon substrate as a first single crystal silicon substrate, 3 is a single crystal silicon substrate as a second single crystal silicon substrate, 7 is a silicon oxide film, and 8 is an epitaxial layer.

Claims (1)

[Claims] 1. A first region exposed on the substrate surface and serving as a first element formation region.
a second single-crystal silicon portion that is exposed on the substrate surface, has a plane orientation different from that of the first single-crystal silicon portion, and serves as a second element formation region. A semiconductor device comprising: 2. A second silicon substrate having a second surface orientation is placed on the smooth surface of the first single crystal silicon substrate having the first surface orientation, with a part of the smooth surface of the first single crystal silicon substrate being exposed. a first step of bonding single crystal silicon substrates; a second step of forming an epitaxial layer on the smooth surface of the first single crystal silicon substrate; and removing a predetermined amount of the epitaxial layer so that the surface is smooth. A method of manufacturing a semiconductor device, comprising: a third step of exposing the epitaxial layer which becomes a first element formation region and the second single crystal silicon substrate which becomes a second element formation region. 3. The method for manufacturing a semiconductor device according to claim 2, wherein a silicon oxide film is formed on the exposed portion of the second single crystal silicon substrate in the first step, and an epitaxial layer is formed in the second step in this state. .