JPS63202034A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63202034A
JPS63202034A JP3486087A JP3486087A JPS63202034A JP S63202034 A JPS63202034 A JP S63202034A JP 3486087 A JP3486087 A JP 3486087A JP 3486087 A JP3486087 A JP 3486087A JP S63202034 A JPS63202034 A JP S63202034A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
manufacturing
semiconductor device
uneven portion
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3486087A
Other languages
Japanese (ja)
Inventor
Masaaki Ikegami
雅明 池上
Masao Yoshizawa
吉澤 正夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3486087A priority Critical patent/JPS63202034A/en
Publication of JPS63202034A publication Critical patent/JPS63202034A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To prevent warping in a semiconductor substrate without a time for forming, by additionally manufacturing a semiconductor substrate having protruding and recess parts, which are complementary to recess and protruding parts of another semiconductor substrate, bonding both substrates through an insulating film and thereafter polishing the substrates. CONSTITUTION:An oxide film 2a is formed on a silicon substrate 1a. A patterned oxide film 2b is similarly formed on a silicon substrate 1b, which is separately prepared. The patterns of the oxide films 2a and 2b are complementary to each other. Oxide films 4a and 4b are formed on a high concentration impurity diffused layer 3 of the silicon substrate 1a and on the silicon substrate 1b, respectively. SOG 5 is further applied on the oxide film 4a on the silicon substrate 1a. The silicon substrates 1a and 1b are tightly contacted, and heat treatment is performed. Then the SOG 5 is chemically bonded to the oxide films 4a and 4b, and both films are bonded as a unitary body. After the separately manufactured two semiconductor substrates are bonded, polishing is performed. Thus the forming time of a conventional polysilicon layer is not required, and the warping problem of the semiconductor substrates is eliminated.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は半導体装置の製造方法に関し、特に絶縁層に
よって分離される半導体装置の製造方法に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device separated by an insulating layer.

[従来の技術] 第2図は従来の絶縁層で分離される半導体装置の製造工
程を示す断面図である。
[Prior Art] FIG. 2 is a cross-sectional view showing the manufacturing process of a conventional semiconductor device separated by an insulating layer.

以下、図を参照して従来の製造方法を説明する。Hereinafter, a conventional manufacturing method will be explained with reference to the drawings.

まず、シリコン基板1の上に熱酸化法またはCVD法等
によって酸化膜2を形成し、これを写真製版等でバター
ニングする(第2図(a)参照)。
First, an oxide film 2 is formed on a silicon substrate 1 by a thermal oxidation method or a CVD method, and then patterned by photolithography or the like (see FIG. 2(a)).

バターニングされた酸化膜2をマスクとして湿式または
乾式のエツチングで半導体基板1をエツチングする(第
2図(b)参照)。
The semiconductor substrate 1 is etched by wet or dry etching using the patterned oxide film 2 as a mask (see FIG. 2(b)).

酸化膜2を除去した後、凹凸となったシリコン基板1の
表面全体に高濃度不純物を注入し、拡散法等を用いて高
濃度不純物拡散層3を形成する(第2図(c)参照)。
After removing the oxide film 2, a high concentration impurity is injected into the entire surface of the silicon substrate 1 which has become uneven, and a high concentration impurity diffusion layer 3 is formed using a diffusion method or the like (see FIG. 2(c)). .

次に連続して凹凸部に形成された高濃度不純物拡散層3
の上にCVD法で絶縁層となる酸化膜4を形成し、さら
にその上に同じ<CVD法で数1100t1程度のポリ
シリコン層7を形成する(第2図(d)参照)。
Next, a high concentration impurity diffusion layer 3 is continuously formed on the uneven portion.
An oxide film 4 serving as an insulating layer is formed thereon by the CVD method, and a polysilicon layer 7 having a thickness of about 1100 t1 is further formed thereon by the same CVD method (see FIG. 2(d)).

最後に基板を反転した後、シリコン基板1の凹凸部の裏
面からポリシリコン層7の凸部まで研磨してシリコン基
板1の一群が相互に独立するような絶縁層分離の半導体
装置が製造される(第2図(e)参照)。
Finally, after inverting the substrate, polishing is performed from the back surface of the uneven portion of the silicon substrate 1 to the convex portion of the polysilicon layer 7, thereby manufacturing a semiconductor device with insulating layer separation in which a group of silicon substrates 1 are mutually independent. (See Figure 2(e)).

[発明が解決しようとする問題点] 上記のような従来の製造方法では、ポリシリコン層を数
100μm程度の厚さまでCVD法で形成するのに膨大
な時間を要し、さらにポリシリコン層の形成時の熱影響
によって生じた残留応力で半導体基板に反りが生じるの
で、後の研磨工程において研磨量が一定でなくなり精度
の良い絶縁層分離とならないという問題点があった。
[Problems to be Solved by the Invention] In the conventional manufacturing method as described above, it takes an enormous amount of time to form a polysilicon layer to a thickness of several 100 μm using the CVD method, and it takes a long time to form the polysilicon layer. Since the semiconductor substrate warps due to the residual stress caused by the thermal effects of the process, there is a problem that the amount of polishing is not constant in the subsequent polishing process, and the insulating layer cannot be separated with high accuracy.

この発明はかかる問題点を解決するためになされたもの
で、ポリシリコン層の長時間の形成を必要とせず、さら
に半導体基板に反りを生じさせない絶縁層分離された半
導体装置の製造方法を提供することを目的とする。
The present invention has been made to solve these problems, and provides a method for manufacturing a semiconductor device in which an insulating layer is separated, which does not require long-term formation of a polysilicon layer and does not cause warping of a semiconductor substrate. The purpose is to

[問題点を解決するための手段] この発明に係る製造方法は、従来のポリシリコン層を形
成する代わりに半導体基板の凹凸部に相補する凸凹部を
有した半導体基板を別途製造し、両者を絶縁膜を介して
接合した後研磨するものである。
[Means for Solving the Problems] In the manufacturing method according to the present invention, instead of forming a conventional polysilicon layer, a semiconductor substrate having an uneven portion complementary to the uneven portion of the semiconductor substrate is separately manufactured, and both are combined. After bonding via an insulating film, polishing is performed.

[作用〕 この発明においては従来のポリシリコン層に相当する部
分に別途製造した半導体基板を使用するので、その形成
に時間を要せず熱影響を受ける時間が激減するため半導
体基板に反りを生じさせることもない。
[Function] In this invention, a separately manufactured semiconductor substrate is used for the portion corresponding to the conventional polysilicon layer, so no time is required for its formation, and the time it is exposed to heat is drastically reduced, which prevents the semiconductor substrate from warping. I won't let you.

[実施例] 第1図はこの発明の一実施例における製造工程を示す断
面図である。
[Example] FIG. 1 is a sectional view showing a manufacturing process in an example of the present invention.

以下、図を参照してこの発明の製造方法を説明する。The manufacturing method of the present invention will be explained below with reference to the drawings.

まず、従来例と同じくたとえばシリコン基板1aの上に
熱酸化法またはCVD法等によって酸化膜2aを形成し
、これを写真製版等でバターニングするが、一方別途準
備されたシリコン基板1bの」二にも同様にバターニン
グされた酸化膜2bを形成する。
First, as in the conventional example, an oxide film 2a is formed on a silicon substrate 1a by a thermal oxidation method or a CVD method, and this is patterned by photolithography. Similarly, a patterned oxide film 2b is also formed.

このとき酸化膜2aおよび2bのバターニングは互いに
相補的なものである(第1図(a)参照)バターニング
された酸化膜2aおよび2bをマスクとしてシリコン基
板1aおよび1bをそれぞれ湿式または乾式のエツチン
グでエツチングする(第1図(b)参照)。
At this time, the patterning of the oxide films 2a and 2b is complementary to each other (see FIG. 1(a)). Using the patterned oxide films 2a and 2b as masks, the silicon substrates 1a and 1b are subjected to a wet or dry process, respectively. Etching is performed (see Fig. 1(b)).

酸化膜2aおよび2bを除去した後、シリコン基板1a
の方についてはその凹凸部全体に高濃度不純物を注入し
、拡散法等を用いて高濃度不純物拡散層3を形成する(
第1図(c)参照)。
After removing the oxide films 2a and 2b, the silicon substrate 1a
For the above case, a high concentration impurity is implanted into the entire uneven portion, and a high concentration impurity diffusion layer 3 is formed using a diffusion method or the like (
(See Figure 1(c)).

次に、シリコン基板1aの高濃度不純物拡散層3の上と
シリコン基板1bの上とにそれぞれCVD法等で絶縁層
となる酸化膜4aおよび4bを形成しく第1図(d)参
照)、さらにシリコン基板1aについては酸化膜4aの
上に5OG5を数100〜数1000人の厚さに塗布す
る(第1図(e)参照)。
Next, oxide films 4a and 4b which will become insulating layers are formed by CVD or the like on the high concentration impurity diffusion layer 3 of the silicon substrate 1a and the silicon substrate 1b, respectively (see FIG. 1(d)). As for the silicon substrate 1a, 5OG5 is coated on the oxide film 4a to a thickness of several hundred to several thousand layers (see FIG. 1(e)).

さらに、シリコン基板1aの凹凸部とシリコン基板1b
の凸凹部とを合致させるように密着させ、約600〜1
ooo°C程度で熱処理を施すと5OG5がガラス化さ
れ酸化膜4aおよび4bと化学結合することによって、
両者は一体に接合される(第1図(f)参照)。
Furthermore, the uneven portion of the silicon substrate 1a and the silicon substrate 1b
600~1.
When heat-treated at about ooo°C, 5OG5 is vitrified and chemically bonded with the oxide films 4a and 4b.
Both are integrally joined (see FIG. 1(f)).

最後に、一体となった基板を反転してシリコン基板1a
をシリコン基板1bの凸部まで研磨することによって絶
縁層となる酸化膜6で分離された半導体装置が完成する
(第1図(g)参照)。
Finally, invert the integrated substrate to form a silicon substrate 1a.
By polishing the silicon substrate 1b to the convex portion, a semiconductor device separated by an oxide film 6 serving as an insulating layer is completed (see FIG. 1(g)).

なお、上記実施例では半導体基板の凹凸部の形成はエツ
チング法によったが、他の方法であっても同様の効果を
奏することは言うまでもない。
In the above embodiment, the uneven portions of the semiconductor substrate were formed by an etching method, but it goes without saying that other methods can produce similar effects.

また、上記実施例では、5OG5をシリコン基板la側
に塗布したがシリコン基板lb側に塗布しても、または
両側に塗布しても同様の効果を奏する。
Further, in the above embodiment, 5OG5 was applied to the silicon substrate la side, but the same effect can be obtained even if it is applied to the silicon substrate lb side or both sides.

さらに、上記実施例では、接合時にSOGを使用してい
るが他のガラス化液体材料であってもよく、またSOG
においても砒素、リン、ボロン、アンチモン等の不純物
を含むものであってもよい。
Further, in the above embodiments, SOG is used during bonding, but other vitrified liquid materials may be used, and SOG
It may also contain impurities such as arsenic, phosphorus, boron, and antimony.

[発明の効果] この発明は以上説明したとおり、別途製造した2枚の半
導体基板を接合した後研磨加工を行なうので、従来のよ
うなポリシリコン層の形成にかかる膨大な時間が不要と
なり、またそのための影響であった半導体基板の反りの
問題も解消されるので、研磨量のばらつきのない精度の
良い絶縁層で分離された半導体装置の製造方法となる効
果がある。
[Effects of the Invention] As explained above, this invention performs polishing after bonding two separately manufactured semiconductor substrates, which eliminates the huge amount of time required to form a polysilicon layer as in the conventional method. Since the problem of warping of the semiconductor substrate caused by this is also resolved, the present invention has the effect of providing a method for manufacturing semiconductor devices separated by an insulating layer with high precision and no variation in polishing amount.

さらに、ポリシリコン層の形成時に生じる熱影響を受け
る時間が短縮されることから不純物拡散層の再拡散も最
小限に抑えられ、良好な電気特性を有した半導体装置が
製造できる効果がある。
Furthermore, since the time during which the polysilicon layer is exposed to heat effects during formation is shortened, re-diffusion of the impurity diffusion layer is also minimized, and a semiconductor device with good electrical characteristics can be manufactured.

【図面の簡単な説明】 第1図はこの発明の一実施例における工程断面図、第2
図は従来の製造方法による工程断面図である。 図において、la、lbはシリコン基板、2a。 2bは酸化膜、3は高濃度不純物拡散層、4a+4bは
酸化膜、5はSOG、6は酸化膜である。 なお、各図中同一符号は同一または相当部分を示す。
[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a cross-sectional view of a process in an embodiment of the present invention;
The figure is a process sectional view of a conventional manufacturing method. In the figure, la and lb are silicon substrates, and 2a. 2b is an oxide film, 3 is a high concentration impurity diffusion layer, 4a+4b is an oxide film, 5 is SOG, and 6 is an oxide film. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (9)

【特許請求の範囲】[Claims] (1)第1主面および第2主面を有する第1の半導体基
板の前記第1主面に凹凸部を形成する工程と、 前記第1の半導体基板の前記凹凸部に不純物の拡散層を
形成する工程と、 第1主面および第2主面を有する第2の半導体基板の前
記第1主面に前記第1の半導体基板の前記凹凸部と相補
する凸凹部を形成する工程と、前記第1の半導体基板の
前記凹凸部と、前記第2の半導体基板の前記凸凹部とを
絶縁層を介して接合する工程と、 接合された前記第1の半導体基板の前記第2の主面を接
合された前記第2の半導体基板が露出するまで研磨する
工程とを備えた、絶縁層によって分離された半導体装置
の製造方法。
(1) Forming an uneven portion on the first main surface of a first semiconductor substrate having a first main surface and a second main surface; and forming an impurity diffusion layer on the uneven portion of the first semiconductor substrate. a step of forming an uneven portion complementary to the uneven portion of the first semiconductor substrate on the first main surface of a second semiconductor substrate having a first main surface and a second main surface; a step of bonding the uneven portion of the first semiconductor substrate and the uneven portion of the second semiconductor substrate via an insulating layer; A method for manufacturing a semiconductor device separated by an insulating layer, comprising the step of polishing until the bonded second semiconductor substrate is exposed.
(2)前記凹凸部を形成する工程は、 前記第1の半導体基板の前記第1主面上にエッチングす
るためのマスクとして第1のパターンを有した第1の膜
を形成する工程と、 前記第1の膜をマスクとして前記第1主面をエッチング
する工程とからなる、特許請求の範囲第1項記載の半導
体装置の製造方法。
(2) The step of forming the uneven portion includes: forming a first film having a first pattern as a mask for etching on the first main surface of the first semiconductor substrate; 2. The method of manufacturing a semiconductor device according to claim 1, comprising the step of etching the first main surface using a first film as a mask.
(3)前記凸凹部を形成する工程は、 前記第2の半導体基板の前記第1主面上にエッチングす
るためのマスクとして、前記第1のパターンに相補的な
第2のパターンを有した第2の膜を形成する工程と、 前記第2の膜をマスクとして前記第1主面をエッチング
する工程とからなる、特許請求の範囲第2項記載の半導
体装置の製造方法。
(3) The step of forming the uneven portion includes using a second pattern complementary to the first pattern as a mask for etching on the first main surface of the second semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 2, comprising the steps of: forming a second film; and etching the first main surface using the second film as a mask.
(4)前記絶縁層は、前記第1の半導体基板の前記凹凸
部上と、前記第2の半導体基板の前記凸凹部上とに形成
される酸化膜である、特許請求の範囲第1項、第2項ま
たは第3項記載の半導体装置の製造方法。
(4) The insulating layer is an oxide film formed on the uneven portion of the first semiconductor substrate and on the uneven portion of the second semiconductor substrate, A method for manufacturing a semiconductor device according to item 2 or 3.
(5)前記第1の半導体基板と前記第2の半導体基板と
がガラス化液体材料の塗布によって接合される、特許請
求の範囲第4項記載の半導体装置の製造方法。
(5) The method of manufacturing a semiconductor device according to claim 4, wherein the first semiconductor substrate and the second semiconductor substrate are bonded by applying a vitrified liquid material.
(6)前記ガラス化液体材料は、スピン・オン・グラス
(SOG)である、特許請求の範囲第5項記載の半導体
装置の製造方法。
(6) The method for manufacturing a semiconductor device according to claim 5, wherein the vitrified liquid material is spin-on glass (SOG).
(7)前記スピン・オン・グラスは、不純物を含む、特
許請求の範囲第6項記載の半導体装置の製造方法。
(7) The method for manufacturing a semiconductor device according to claim 6, wherein the spin-on glass contains impurities.
(8)前記不純物は、砒素、リン、ボロンおよびアンチ
モンよりなる一群の元素から選択される、特許請求の範
囲第7項記載の半導体装置の製造方法。
(8) The method for manufacturing a semiconductor device according to claim 7, wherein the impurity is selected from a group of elements consisting of arsenic, phosphorus, boron, and antimony.
(9)前記スピン・オン・グラスと前記酸化膜とは、熱
処理されることによって化学結合する、特許請求の範囲
第6項、第7項または第8項記載の半導体装置の製造方
法。
(9) The method for manufacturing a semiconductor device according to claim 6, 7, or 8, wherein the spin-on glass and the oxide film are chemically bonded by heat treatment.
JP3486087A 1987-02-17 1987-02-17 Manufacture of semiconductor device Pending JPS63202034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3486087A JPS63202034A (en) 1987-02-17 1987-02-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3486087A JPS63202034A (en) 1987-02-17 1987-02-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63202034A true JPS63202034A (en) 1988-08-22

Family

ID=12425922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3486087A Pending JPS63202034A (en) 1987-02-17 1987-02-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63202034A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5484738A (en) * 1992-06-17 1996-01-16 International Business Machines Corporation Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits
US5681775A (en) * 1995-11-15 1997-10-28 International Business Machines Corporation Soi fabrication process
US6225154B1 (en) 1993-07-27 2001-05-01 Hyundai Electronics America Bonding of silicon wafers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413273A (en) * 1977-07-01 1979-01-31 Oki Electric Ind Co Ltd Semiconductor device
JPS5455181A (en) * 1977-10-12 1979-05-02 Hitachi Ltd Production of semiconductor substrate
JPS624338A (en) * 1985-06-29 1987-01-10 Toshiba Corp Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5413273A (en) * 1977-07-01 1979-01-31 Oki Electric Ind Co Ltd Semiconductor device
JPS5455181A (en) * 1977-10-12 1979-05-02 Hitachi Ltd Production of semiconductor substrate
JPS624338A (en) * 1985-06-29 1987-01-10 Toshiba Corp Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5484738A (en) * 1992-06-17 1996-01-16 International Business Machines Corporation Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits
US6225154B1 (en) 1993-07-27 2001-05-01 Hyundai Electronics America Bonding of silicon wafers
US6570221B1 (en) 1993-07-27 2003-05-27 Hyundai Electronics America Bonding of silicon wafers
US5681775A (en) * 1995-11-15 1997-10-28 International Business Machines Corporation Soi fabrication process

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