JPS5833703B2 - Handout Taisouchino Seizouhouhou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular, an object of the present invention is to provide a method for easily manufacturing a semiconductor device having a minute isolation region.

As an example of a semiconductor integrated circuit, as its constituent elements and element isolation regions become smaller and smaller, the minimum processing size (approximately 5μ
) is almost reaching its limit.

In order to achieve even higher integration, technology is being developed that uses electron beams and X-rays, which have shorter wavelengths than light, to process fine patterns instead of optical methods.
The current situation is that it still takes time for practical application.

In addition, when miniaturizing, simply reducing the size generally causes changes in the electrical characteristics of the constituent elements, so it is clear that the method of miniaturizing the isolation region is easier and more effective than increasing the degree of integration. It is.

The present invention provides a method of forming an element isolation region narrower than the minimum dimension that can be optically processed using a conventional optical photolithography technique, and its main point is to focus on the following phenomenon.

In other words, substances that cause plastic flow (e.g. high concentration phosphorus glass, etc.)
When a material is formed on an uneven surface of a semiconductor device and subjected to heat treatment to melt it (melt heat treatment), the melted fluid material becomes thinner at the stepped portions.

When this material is etched from the surface (for example, about 1/2 the thickness of other parts), it disappears from the step part and the underlying material begins to be exposed.

When this underlying material is exposed, the etching of the fluidized bed is stopped,
When the underlying material is etched with an etching solution that does not disturb the fluidized bed, only areas of the underlying material are opened.

Hereinafter, the present invention will be explained by way of examples with reference to the drawings.

Figure 1 shows an n-channel MOS IC (n-channel MOS IC).
The method of the present invention is applied to device isolation of 1MO8IC), and while the conventional technique forms an isolation region of 6 to 8 μm width, it is possible to form an isolation region of 2 to 3 μm width with the method of the present invention. .

FIG. 1a shows a semiconductor substrate (for example, P type, (10
The SiO2 film 2 is first formed on the substrate 1 by thermal oxidation (approximately 500 Ω-cm).

Next, using the gas phase reaction of SiH4 and NH,
5i3N, to form a film of about 1000 people.

Further, by using vapor phase decomposition of SiH4, a polycrystalline silicon film 4 of approximately 5000 layers is formed on the Si3['J] film.

When thermal oxidation is performed again in this state, an Si 02 film 5 is formed on the surface of the polycrystalline silicon film.

This S102 film will be used as a processing mask and a diffusion mask for the next polycrystalline silicon film, and its thickness is approximately 1,500 mm.

Next, the exposed Si02 film 5 on the surface of which the plurality of films described above are stacked is patterned using photolithography so as to alternately open adjacent regions where elements are to be formed.

Using this remaining SiOx film 5' as a mask, the adjacent polycrystalline silicon film 4 is coated with, for example, HF-HNO3.
By etching with an etching solution, the result is as shown in the figure.

When boron B is diffused in this state, the diffusion conditions are adjusted as shown in FIG.

Next, the remaining 5in2 film 5' on the polycrystalline silicon film
is removed with NH4F solution, and then the polycrystalline silicon film 4'' is etched with a selective etchant that etches only the region 4'' in which Boron is not diffused in the remaining polycrystalline silicon film 4', as shown in Figure d. Polycrystalline silicon patterns 4a□, 4a2, . . . with a micro width of about 1 μm are formed at the boundaries of the regions where each element is to be formed.

A selective etching solution for the polycrystalline silicon film has the following composition.

Next, as shown in Figure e, a boron-phosphorus-silicon glass (BP8G) film 6 (hereinafter abbreviated as BPSG film) which causes plastic flow by heat treatment is formed to a thickness of about 4000 mm.

This BPSG film is made of S t using the SiB4 oxidation method.
In the vapor phase growth of the 02 film, it is obtained by doping B2H6 and PH3 at the same time, and is similar to the phosphorus-silicon glass (PSG) produced when only PH3 is doped.
) The etching speed can be lower than that of a film, which is advantageous in terms of controlling the amount of etching in subsequent steps.

Next, when heat treatment is performed at, for example, 1000°C in a N2 atmosphere, the BPSG film melts and takes on the shape shown in Figure f.
The BPSG film thickness 6' is the step part of the polycrystalline silicon layer (the part indicated by the arrow in the figure) 6al, 6b', 6c'.
It becomes thinner with...

When the BPSG film is partially etched using, for example, an NH4F solution, some of the polycrystalline silicon films 4a□, 4a2 begin to be exposed from the stepped portions as shown in FIG.

A fine thin BPSG film remains on some of the polycrystalline silicon films 4a□, 4a2.

Next, when the polycrystalline silicon film is etched, the remaining BPSG film on the polycrystalline silicon film is also removed, and as shown in the figure, micro-width grooves 7a, 7 corresponding to the polycrystalline silicon film pattern are removed.
b... is opened.

FIG. 1 shows the result of etching the adjacent S t 3 N4 film using this BPSG film having micro grooves as a mask.

The Si3N4 film is etched using hot phosphoric acid solution or Freon gas plasma.

Next, S i B N, the underlying S exposed from the film pattern
When the iO2 film 2 is etched with the NH4F solution, the BPSG film is also etched at the same time, resulting in the structure shown in FIG. J.

Next, as shown in FIG. K, the exposed portions 1a and 1b of the silicon substrate 1 shown in FIG. P layers 8a and 8b for preventing channel inversion as shown in FIG. 1 are formed.

Next, by thermal oxidation, selective oxidation is performed using the SiB N4 film as a mask, and element isolation oxide films 9a and 9b are formed only in the minute openings, as shown in FIG.

Figure n shows the state in which the oxidation mask area is removed after oxidation,
The element isolation regions A and B have extremely narrow widths (2 to 3 μm) and are embedded in the semiconductor substrate.

An example of an n-channel MO8IC is formed in the A and B regions separated and formed as described above using a conventional technique, as shown in FIG. 2.

Compared to conventional element isolation methods, this has the remarkable advantage that element forming regions can be brought very close to each other, the effective area is improved by 40%, and high integration can be achieved.

[Brief explanation of drawings]

1A to 1A are cross-sectional views shown in the order of steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS.
The figure is a cross-sectional view of a MOS IC formed by applying an example of the method of manufacturing a semiconductor device of the present invention. Note that the same reference numerals in the drawings indicate the same or corresponding parts, respectively. 1... Semiconductor substrate, 3... Oxidation-resistant layer (
S i3 N4 film), 4...First member (polycrystalline silicon film), 4a□, 4a2... Composition change layer of first member, 6... Second member (BPSG
membrane), 7a, 7b......micro width groove, A, B
...Element isolation region.

Claims (1)

[Claims] 1. After depositing an oxidation-resistant layer on the main surface of the semiconductor substrate, and patterning the first member laminated on the oxidation-resistant layer to form a composition-changed layer on the sides of the pattern, at least this composition-change layer is left. the other first member is removed, and a second member is heated to cause plastic flow in the oxidation-resistant layer and the composition-change layer.
After coating the second member, heating is applied to flow the second member, and then the entire surface of the second member is etched to provide a partially exposed portion of the composition change layer, and from this exposed portion, the composition change layer is coated. The change layer is etched to form a groove, the oxidation-resistant layer exposed in the groove is etched to form an opening that exposes the semiconductor substrate, and the exposed semiconductor substrate is then oxidized to form a groove between the elements. A method of manufacturing a semiconductor device, comprising forming an isolation region.