JPS6218040A - Flattening of phosphosilicate glass film - Google Patents
Flattening of phosphosilicate glass filmInfo
- Publication number
- JPS6218040A JPS6218040A JP60157264A JP15726485A JPS6218040A JP S6218040 A JPS6218040 A JP S6218040A JP 60157264 A JP60157264 A JP 60157264A JP 15726485 A JP15726485 A JP 15726485A JP S6218040 A JPS6218040 A JP S6218040A
- Authority
- JP
- Japan
- Prior art keywords
- phosphosilicate glass
- psg
- flattening
- glass film
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は段差構造を有する基板面に設けた高濃度リンケ
イ酸ガラス膜(PSG)を平坦化することによって基板
の表面を平坦化させる方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for flattening the surface of a substrate by flattening a highly concentrated phosphosilicate glass film (PSG) provided on the surface of the substrate having a stepped structure. be.
従来の技術
PSGの溶融(フロー)による素子平坦化技術は一般的
に行なわれている。第2図& ”−Cはその一例である
。第2図aは相補型MO5半導体装置の製造工程におい
て、P型領域11と素子間分離のフィールド酸化膜12
ならびにゲート電極となる多結晶シリコン層13を形成
した図である。次にホトレジストをマスクにして、イオ
ン注入法にて第2図すのように、N型、P型のおのおの
の不純物拡散層14.15を形成する。次に第2図Cの
ように、熱酸化膜16を成長させ、更に、リン濃度8モ
ルチのPSG17を被着して、その後、17をフローさ
せる。更に、以降の工程は図示しないが、ホトレジスト
をマスクにしてコンタクトホールエツチングを実施し、
最後KAl配線を形成することにより相補型MO8半導
体装置の製造工程が終了する。2. Description of the Related Art Element flattening technology using melting (flow) of PSG is commonly practiced. Figure 2&''-C is an example of this. Figure 2a shows a P-type region 11 and a field oxide film 12 for element isolation in the manufacturing process of a complementary MO5 semiconductor device.
It is also a diagram in which a polycrystalline silicon layer 13 serving as a gate electrode is formed. Next, using a photoresist as a mask, N-type and P-type impurity diffusion layers 14 and 15 are formed by ion implantation as shown in FIG. Next, as shown in FIG. 2C, a thermal oxide film 16 is grown, and a PSG 17 with a phosphorus concentration of 8 molt is deposited, and then the PSG 17 is flowed. Furthermore, although subsequent steps are not shown, contact hole etching is performed using photoresist as a mask.
Finally, by forming the KAl wiring, the manufacturing process of the complementary MO8 semiconductor device is completed.
発明が解決しようとする問題点
しかし、この様にして行なわれるPSGl 7のフロー
は熱処理温度が1000′Cと高いために、この処理工
程でソース、ドレイン拡散層中の不純物が再度拡散され
、ソース、ドレイン拡散深さが伸びる。特にPチャンネ
ル素子において特に顕著で拡散深さは、0.6〜0.8
μmに達する。このため素子のチャンネル長が2μm以
下の相補型MOSLSIの微細化、高集積化を実現する
のは困難である。また、PSGl7のフローの際の熱処
理過程において、多結晶シリコン層やシリコン基板が酸
化され、さらにPチャンネル素子においてはソース、ド
レイン不純物拡散領域15へPSG17中のリンが拡散
する恐れもある。Problems to be Solved by the Invention However, since the PSGl 7 flow performed in this way requires a high heat treatment temperature of 1000'C, impurities in the source and drain diffusion layers are diffused again in this treatment step, and the source and drain diffusion layers are diffused again. , the drain diffusion depth increases. This is especially noticeable in P-channel devices, where the diffusion depth is 0.6 to 0.8.
reaching μm. For this reason, it is difficult to realize miniaturization and high integration of complementary MOSLSIs in which the channel length of the device is 2 μm or less. Furthermore, in the heat treatment process during flow of the PSG 17, the polycrystalline silicon layer and the silicon substrate may be oxidized, and there is also a possibility that phosphorus in the PSG 17 may be diffused into the source/drain impurity diffusion region 15 in the P-channel element.
本発明はこの様な問題点を解決するもので、90゜℃の
低温でPSGをフローさせる方法を提供するものである
。The present invention solves these problems and provides a method for flowing PSG at a low temperature of 90°C.
問題点を解決するための手段
この目的を達成するため、本発明のリンケイ酸ガラス被
膜の平坦化方法はリンケイ酸ガラスに水蒸気雰囲気中で
加熱処理を施す工程をそなえたものである。Means for Solving the Problems In order to achieve this object, the method for planarizing a phosphosilicate glass film of the present invention includes a step of subjecting phosphosilicate glass to a heat treatment in a steam atmosphere.
作 用
この平坦化方法によれば、900 ’Cの低温でPSG
を70−させるのでソース、ドレイン拡散層の深さはN
チャンネル側で0.3μm、Pチャンネル側でo、−6
μm程度に抑えることができ、短チャンネル化を実現し
、かつ、PSGの平坦化が可能となる。Function: According to this planarization method, PSG can be formed at a low temperature of 900'C.
Since the depth of the source and drain diffusion layers is set to 70-, the depth of the source and drain diffusion layers is N.
0.3 μm on the channel side, o, -6 on the P channel side
The thickness can be suppressed to about μm, making it possible to shorten the channel and flatten the PSG.
実施例
以下、本発明のリンケイ酸ガラス被膜の平坦化方法につ
いて図面を参照して説明する。EXAMPLE Hereinafter, the method for flattening a phosphosilicate glass film of the present invention will be explained with reference to the drawings.
同図において、P型領域1と素子間分離のフィールド酸
化膜を形成する。つぎに、ゲート電極となる多結晶シリ
コン層4を形成し、ホトレジストをマスクにしてイオン
注入法にてN型、P型おのおのの不純物拡散層8,9を
形成する。次に熱酸化膜6を酸素雰囲気中で900 ’
Cで30分間成長させ、さらに、窒化シリコン層6を4
0 n m被着させる。その上部にリン濃度8モルチの
PSG7を被着させる。これを大気圧中で例えば水素の
酸素に対する割合が1.8なる水蒸気雰囲気中で900
℃にて90分間フローを行なう。このホトレジストt−
マスクにしてコンタクトホールエツチングを実施する。In the figure, a P-type region 1 and a field oxide film for isolation between elements are formed. Next, a polycrystalline silicon layer 4 that will become a gate electrode is formed, and N-type and P-type impurity diffusion layers 8 and 9 are formed by ion implantation using a photoresist as a mask. Next, the thermal oxide film 6 is heated for 900' in an oxygen atmosphere.
C for 30 minutes, and then a silicon nitride layer 6 was grown for 4 minutes.
Deposit 0 nm. PSG7 with a phosphorus concentration of 8 molti is deposited on top of it. At atmospheric pressure, for example, in a water vapor atmosphere where the ratio of hydrogen to oxygen is 1.8,
Flow for 90 minutes at °C. This photoresist t-
Perform contact hole etching using a mask.
最後にAl配線を形成することにより相補型MO3半導
体装置が完成する。Finally, by forming Al wiring, a complementary MO3 semiconductor device is completed.
以上のように、本実施例によれば従来のフロー技術で問
題であったAl配線の断線、拡散長の増大あるいはPS
Gの低リン濃度化に関する問題を解決できる。更にPS
Gの下地に薄い窒化シリコン層を設けるので、多結晶シ
リコン層の表面酸化が防止され、PSG中のリンがソー
ス、ドレイン領域へ拡散することを防止するという効果
を有する0
以上説明したように本発明の方法を用いて素子平坦化を
行なうと、従来のフロー技術で問題があったAl配線の
断線、拡散長の増大あるいはPSGの低リン濃度化に関
する問題などの種々の問題をことごとく解決することが
可能である。As described above, according to this embodiment, problems such as disconnection of Al wiring, increase in diffusion length, and PS
This can solve the problem of lowering the phosphorus concentration of G. Further P.S.
Since a thin silicon nitride layer is provided under the G, surface oxidation of the polycrystalline silicon layer is prevented, and phosphorus in the PSG is prevented from diffusing into the source and drain regions. When device planarization is performed using the method of the invention, all of the various problems that occurred with conventional flow techniques, such as disconnection of Al wiring, increased diffusion length, and problems related to lowering the phosphorus concentration of PSG, can be solved. is possible.
第1図は本発明のフロー状態を示す図、第2図& ’=
Cは、従来の方法を説明するための図である。
1.11・・・・・・P型領域、2,12・・・・・・
フィールド酸化膜、3・・・・・・ゲート酸化膜、4,
13・・・・・・多結晶シリコン層、5.16・・・・
・・熱酸化膜、6・・・・・・窒化シリコン層、7.1
7・・・・・・リンケイ酸ガラス層(PSG )、8,
14・・・・・・N型拡散層、9,15・・・・・・P
型拡散層。Figure 1 is a diagram showing the flow state of the present invention, Figure 2 &'=
C is a diagram for explaining a conventional method. 1.11...P-type region, 2,12...
Field oxide film, 3... Gate oxide film, 4,
13... Polycrystalline silicon layer, 5.16...
...Thermal oxide film, 6...Silicon nitride layer, 7.1
7...phosphosilicate glass layer (PSG), 8,
14...N-type diffusion layer, 9,15...P
type diffusion layer.
Claims (5)
施す工程をそなえたリンケイ酸ガラス被膜の平坦化方法
。(1) A method for flattening a phosphosilicate glass film, which includes the step of subjecting phosphosilicate glass to heat treatment in a steam atmosphere.
とを特徴とする特許請求の範囲第1項に記載のリンケイ
酸ガラス被膜の平坦化方法。(2) The method for flattening a phosphosilicate glass film according to claim 1, wherein the heat treatment is performed at 900° C. under atmospheric pressure.
ン層上に形成されたものである特許請求の範囲第1項に
記載のリンケイ酸ガラス被膜の平坦化方法。(3) The method for flattening a phosphosilicate glass film according to claim 1, wherein the phosphosilicate glass is formed on a silicon nitride layer having a thickness of 100 mm or less.
び100mm以下の熱酸化膜上に形成されたものである
特許請求の範囲第1項に記載のリンケイ酸ガラス被膜の
平坦化方法。(4) The method for flattening a phosphosilicate glass film according to claim 1, wherein the phosphosilicate glass is formed on a base of a silicon nitride layer and a thermal oxide film of 100 mm or less.
なる特許請求の範囲第1項に記載のリンケイ酸ガラス被
膜の平坦化方法。(5) The method for flattening a phosphosilicate glass film according to claim 1, wherein the phosphosilicate glass has a composition with a phosphorus concentration of 8 mol%.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60157264A JPS6218040A (en) | 1985-07-17 | 1985-07-17 | Flattening of phosphosilicate glass film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60157264A JPS6218040A (en) | 1985-07-17 | 1985-07-17 | Flattening of phosphosilicate glass film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6218040A true JPS6218040A (en) | 1987-01-27 |
Family
ID=15645852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60157264A Pending JPS6218040A (en) | 1985-07-17 | 1985-07-17 | Flattening of phosphosilicate glass film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6218040A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5004704A (en) * | 1988-11-28 | 1991-04-02 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device having a phospho silicate glass layer as an interlayer insulating layer |
JPH04372808A (en) * | 1991-06-24 | 1992-12-25 | Kobe Steel Ltd | Method for measuring thickness of resin film of composite metal plate |
US6962855B2 (en) * | 2002-11-08 | 2005-11-08 | Samsung Electronics Co., Ltd. | Method of forming a porous material layer in a semiconductor device |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53131770A (en) * | 1977-04-21 | 1978-11-16 | Fujitsu Ltd | Production of semiconductor device |
JPS553700A (en) * | 1978-06-19 | 1980-01-11 | Rca Corp | Composite layer for stabilizing ic device |
JPS5812340A (en) * | 1981-07-16 | 1983-01-24 | Nec Corp | Manufacture of semiconductor device |
JPS5898934A (en) * | 1981-12-08 | 1983-06-13 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS58106847A (en) * | 1981-12-18 | 1983-06-25 | Nec Corp | Manufacture of semiconductor device |
JPS58197826A (en) * | 1982-05-14 | 1983-11-17 | Hitachi Ltd | Manufacture of semiconductor device |
-
1985
- 1985-07-17 JP JP60157264A patent/JPS6218040A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53131770A (en) * | 1977-04-21 | 1978-11-16 | Fujitsu Ltd | Production of semiconductor device |
JPS553700A (en) * | 1978-06-19 | 1980-01-11 | Rca Corp | Composite layer for stabilizing ic device |
JPS5812340A (en) * | 1981-07-16 | 1983-01-24 | Nec Corp | Manufacture of semiconductor device |
JPS5898934A (en) * | 1981-12-08 | 1983-06-13 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS58106847A (en) * | 1981-12-18 | 1983-06-25 | Nec Corp | Manufacture of semiconductor device |
JPS58197826A (en) * | 1982-05-14 | 1983-11-17 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5004704A (en) * | 1988-11-28 | 1991-04-02 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device having a phospho silicate glass layer as an interlayer insulating layer |
JPH04372808A (en) * | 1991-06-24 | 1992-12-25 | Kobe Steel Ltd | Method for measuring thickness of resin film of composite metal plate |
US6962855B2 (en) * | 2002-11-08 | 2005-11-08 | Samsung Electronics Co., Ltd. | Method of forming a porous material layer in a semiconductor device |
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