JPH01251658A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01251658A JPH01251658A JP7590888A JP7590888A JPH01251658A JP H01251658 A JPH01251658 A JP H01251658A JP 7590888 A JP7590888 A JP 7590888A JP 7590888 A JP7590888 A JP 7590888A JP H01251658 A JPH01251658 A JP H01251658A
- Authority
- JP
- Japan
- Prior art keywords
- base
- region
- protrusion
- emitter
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000013590 bulk material Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052710 silicon Inorganic materials 0.000 abstract description 18
- 239000010703 silicon Substances 0.000 abstract description 18
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 238000004904 shortening Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置、特にバイポーラトランジスタの製造方法に
関し、
改良された型のバイポーラトランジスタにおいて、エミ
ッタ・ベース間の距離をさらに小にする７ｉで、ベース
電極がシリコン基板とのコンタクトをとる部分の面積を
大にしてベース抵抗をさらに低減させる構造を製造する
方法を提供することを目的とし、
半導体基板表面に第１凸部を、前記基板のバルク材以外
の、かつ、エツチングにおいて該バルク材と選択比のあ
る物質で形成する工程、第１凸部側面に耐酸化性の、か
つ、前記バルク材のエツチングにおいて選択比をもつ第
２の物質の膜を形成する工程、第１凸部とその側面の膜
をマスクにして半導体基板をエツチングして第２凸部を
形成する工程、および第２凸部にベース領域とエミッタ
領域を形成する工程を含むことを特徴とする半導体装置
の製造方法を含み構成する。[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, particularly a bipolar transistor, in an improved type of bipolar transistor, the base electrode is connected to a silicon substrate in 7i, which further reduces the distance between the emitter and the base. The purpose of the present invention is to provide a method for manufacturing a structure that further reduces base resistance by increasing the area of a contacting part of the semiconductor substrate, and the first convex part is formed on a surface of a semiconductor substrate using a material other than the bulk material of the substrate, and forming a film of a second material that is oxidation-resistant and has a selectivity in etching the bulk material on the side surface of the first convex portion; The method is characterized by comprising the steps of etching the semiconductor substrate using the first protrusion and a film on its side face as a mask to form a second protrusion, and forming a base region and an emitter region in the second protrusion. The present invention includes a method for manufacturing a semiconductor device.
本発明は、半導体装置、特にバイポーラトランジスタの
製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, particularly a bipolar transistor.
第２図の断面図に示されるバイポーラトランジスタは知
られたものであり、図中、旧はｐ型シリコン基板、４２
はｎ１型埋没層、４３はｎ型のエピタキシャル層、４４
はｐ型のベース領域、４５はｎ＋型のエミッタ領域、４
６はｎ＋型のコレクタ領域、４７はｐ＋型のアイソレー
ション領域、４８はフィールド酸化膜、４９は絶縁膜、
５０． ５１．５２はそれぞれアルミニウム（八ｌ）の
コレクタ電極、エミッタ電極、ベース電極である。The bipolar transistor shown in the cross-sectional view of FIG.
is an n1 type buried layer, 43 is an n type epitaxial layer, 44
is a p-type base region, 45 is an n+ type emitter region, 4
6 is an n+ type collector region, 47 is a p+ type isolation region, 48 is a field oxide film, 49 is an insulating film,
50. 51 and 52 are a collector electrode, an emitter electrode, and a base electrode made of aluminum (8l), respectively.
第２図に示したバイポーラトランジスタにおいて、電流
は破線で矢印Ｉを付して示す線に沿ってコレクタ領域か
らエミッタ領域へ流れ、電子は実線で矢印■を付して示
す線に沿って流れるもので、ベース領域によって電流を
コントロールする構成となっている。この型の構造のバ
イポーラトランジスタの性能を高め高速化を実現するに
は、ベース領域およびエミッタ領域を縮小し、また、電
流をコントロールするのに関係する図にＲで模式的に示
す抵抗（ベース抵抗）を軽減してトランジスタの特性を
向上することが求められている。In the bipolar transistor shown in Figure 2, current flows from the collector region to the emitter region along the dashed line marked with arrow I, and electrons flow along the solid line marked with arrow ■. The structure is such that the current is controlled by the base region. In order to improve the performance and increase the speed of bipolar transistors with this type of structure, the base and emitter regions must be reduced, and the resistance (base resistance) shown schematically in the diagram related to current control (base resistance ) is required to improve the characteristics of transistors.
上記したベース抵抗の低減については、Ｎａｋａｍｕｒ
ａ ｅｔ ａｌ、 ＩＥＥＥ Ｔｒａｎｓ、 Ｖｏｌ、
ＥＤ−２９（１９８２） ＋ｐ、５９６およびその改
良としてに、Ｗａｓｈｉｏ ｅｔ ａｌ。Regarding the reduction of base resistance mentioned above, please refer to Nakamur
a et al, IEEE Trans, Vol.
ED-29 (1982) +p, 596 and its improvement, Washio et al.
１９８７１ＥＥＨｌ５ＳＣＣ、ρ、５８に発表された技
術があり、また、エミッタ領域とベース領域を自己整合
（セルファライン）で作るについては、第３図に示され
るトランジスタがある（Ｔ、５ａｋａｉ ｅｔ ａｌ＋
１９８３Ｓｙｍｐｏｓｉｕｍ ｏｎ ＶＬＳＩ Ｔ
ｅｃｈｎｏｌｏｇｙ ） ＋１なお第３図において、６
１はｐ型シリコン基板、６２はｎ型領域、６３はｎ＋型
領領域コレクタ領域）、６４はｐ＋型領領域ベース領域
）、６５はｎ＋型領領域エミッタ領域）、６６は窒化シ
リコン膜、６７は ＳｉＯ２膜、６８はｐ＋ポリシリコ
ン膜、６９はｎ＋ポリシリコン膜、Ｃ，Ｂ、Ｅはそれぞ
れコレクタ電極、ベース電極、Ｅはエミッタ電極を示す
。かかる構造によって、前記したベース領域とエミッタ
領域の縮小、ベース抵抗の低減化が図られている。There is a technology announced in 19871EEHl5SCC, ρ, 58, and there is also a transistor shown in Figure 3 for making the emitter region and base region by self-alignment (self-alignment) (T, 5akai et al+
1983Symposium on VLSI T
technology ) +1 In addition, in Figure 3, 6
1 is a p-type silicon substrate, 62 is an n-type region, 63 is an n + type region (collector region), 64 is a p + type region (base region), 65 is an n + type region (emitter region), 66 is a silicon nitride film, 67 68 is a p+ polysilicon film, 69 is an n+ polysilicon film, C, B, and E are a collector electrode and a base electrode, respectively, and E is an emitter electrode. With this structure, the aforementioned base region and emitter region can be reduced and base resistance can be reduced.
第３図のトランジスタは、ベース領域とベース電極およ
びエミッタ電極の関係がセルファラインで決定していな
いために、位置合せ余裕が必要となり、ベース領域全体
が大きくなりトランジスタの高速化に影習する容量が減
らない問題がある。In the transistor shown in Figure 3, since the relationship between the base region and the base electrode and emitter electrode is not determined by the self-alignment line, alignment margin is required, and the entire base region becomes large, which increases the capacitance that affects the speeding up of the transistor. There is a problem that the number of people is not decreasing.
そこで本発明は、改良された型のバイポーラトランジス
タにおいて、エミッタ・ベース間の距離をさらに小にす
る一方で、ベース電極がシリコン基板とのコンタクトを
とる部分の面積を大にしてベース抵抗をさらに低減させ
る構造を製造する方法を堤供することを目的とする。Therefore, in an improved type of bipolar transistor, the present invention further reduces the distance between the emitter and the base while increasing the area of the part where the base electrode makes contact with the silicon substrate to further reduce the base resistance. The purpose is to provide a method for manufacturing a structure that
上記課題は、半導体基板表面に第１凸部を、前記基板の
バルク材以外の、かつ、エツチングにおいて該バルク材
と選択比のある物質で形成する工程、第１凸部側面に耐
酸化性の、かつ、前記バルク材のエツチングにおいて選
択比をもつ第２の物質の膜を形成する工程、第１凸部と
その側面の股をマスクにして半導体基板をエツチングし
て第２凸部を形成する工程、および第２凸部にベース領
域とエミッタ領域を形成する工程を含むことを特徴とす
る半導体装置の製造方法によって解決される。The above-mentioned problems include a step of forming the first convex portion on the surface of the semiconductor substrate using a material other than the bulk material of the substrate and which has a selectivity with the bulk material during etching; and a step of forming a film of a second material having a selectivity in etching the bulk material, etching the semiconductor substrate using the first protrusion and the crotch of the side surface as a mask to form the second protrusion. The present invention is solved by a method of manufacturing a semiconductor device, which includes a step of forming a base region and an emitter region in the second convex portion.
第１図（ａｌ〜（Ｊ）を参照すると、シリコン半導体基
板表面に該半導体基板のバルク材以外の材料で、該バル
ク材のエツチングにおいて選択比をもつ材料で第１の凸
部１４を形成しく同図（ａ））、次に窒化シリコン膜１
５（以下には単に窒化膜という）を凸部１４の側面に残
す工程を実施しく同図（ｂｌ）、凸部１４と窒化膜１５
をマスクにして第１の凸部１４に対し自己整合的に第２
の凸部１６を形成する。さらに、第２の凸部１６の側面
に窒化膜１７を残す工程を実施し、シリコン基板に酸素
を含む雰囲気中で熱処理を行ってフィールド酸化膜１８
を形成し、窒化膜１５゜１７を除去する（同図（ｄ））
。第２の凸部１６をベース領域とし、第１の凸部の底部
分をエミッタ領域とすることにより、ベース領域、エミ
ッタ領域、ベース電極部、エミッタ電極部はすべて自己
整合で形成する。Referring to FIGS. 1A to 1J, first convex portions 14 are formed on the surface of a silicon semiconductor substrate using a material other than the bulk material of the semiconductor substrate and having a selectivity in etching the bulk material. (a) in the same figure, then silicon nitride film 1
5 (hereinafter simply referred to as a nitride film) on the side surface of the convex portion 14. In the same figure (bl), the convex portion 14 and the nitride film 15
The second convex portion 14 is self-aligned with the first convex portion 14 using the mask as a mask.
A convex portion 16 is formed. Furthermore, a step of leaving the nitride film 17 on the side surface of the second convex portion 16 is carried out, and a heat treatment is performed on the silicon substrate in an atmosphere containing oxygen to form the field oxide film 18.
is formed, and the nitride film 15° 17 is removed (FIG. 1(d)).
. By using the second convex portion 16 as a base region and the bottom portion of the first convex portion as an emitter region, the base region, emitter region, base electrode portion, and emitter electrode portion are all formed in a self-aligned manner.
上記した方法によると、ベース領域とエミッタ領域はセ
ルファラインで形成され位置合せ余裕が必要でなくなる
のでそれの微細化が達成され、さらにベース電極引出し
部は従来例よりもより広い面積で高濃度のベース領域と
コンタクトをとるので、ベース抵抗が低減されるのであ
る。According to the above method, the base region and the emitter region are formed by self-alignment lines, and alignment margins are no longer required, so miniaturization of the base region and emitter region can be achieved.Furthermore, the base electrode lead-out portion has a larger area than the conventional example, and has a high concentration. Since contact is made with the base region, the base resistance is reduced.
以下、本発明実施例を図面により具体的に説明する。 Embodiments of the present invention will be specifically described below with reference to the drawings.
第１図は本発明にかかるバイポーラトランジスタの製造
工程を示す。FIG. 1 shows the manufacturing process of a bipolar transistor according to the present invention.
第１図（ａｌ参照：
第１図（ｊ）に示されるｐ型の半導体基板（シリコン基
板） １１にｎ＋型の埋没層１２を形成し、次いでエピ
タキシャル成長によってｎ型のエピタキシャル層１３を
成長するのであるが、第１図（ａｌ〜（Ｊ）においては
エピタキシャル層１３のみを図示する。図に示される如
く、シリコン基板表面に、シリコン基板のバルク材以外
の材料で、かつ、当該バルク材、すなわちシリコンのエ
ツチングにおいて選択比をもつ材料で第１の凸部１４を
形成する。そのためには、５０００人の厚さに化学気相
酸Ｗ（ＣＶＤ）法または熱酸化で５ｉ０２膜を形成し、
その上に耐酸化膜として窒化シリコンを１５００人の厚
さに成長し、全面に塗布しバターニングしたレジストを
マスクにして窒化シリコンとＳｉＯ２をエツチングして
図示の第１凸部１４を形成する。従って、凸状部１４は
下層のＳｉＯ＋膜１４ａと上層の窒化膜１４ｂからなる
。FIG. 1 (see al.: An n+ type buried layer 12 is formed on the p-type semiconductor substrate (silicon substrate) 11 shown in FIG. 1(j), and then an n-type epitaxial layer 13 is grown by epitaxial growth. However, only the epitaxial layer 13 is shown in FIGS. The first convex portion 14 is formed using a material that has a selectivity in silicon etching.For this purpose, a 5i02 film is formed to a thickness of 5,000 yen by chemical vapor phase oxidation (CVD) or thermal oxidation.
Silicon nitride is grown thereon to a thickness of 1500 nm as an oxidation-resistant film, and the silicon nitride and SiO2 are etched using a resist that has been applied and buttered over the entire surface as a mask to form the first convex portion 14 shown in the figure. Therefore, the convex portion 14 consists of a lower layer SiO+ film 14a and an upper layer nitride film 14b.
第１凸部１４の大きさは後工程で形成するエミッタ拡大
窓に対応させる。５ｉＯｚ膜の上に窒化膜を設ける理由
は、後の熱処理において、ＳｉＯ２膜だけであると５ｉ
Ｏｚは酸素を通すため第１凸部１４の下のシリコン基板
が酸化され、そうなるとそれを除去する工程が必要とな
るだけでなく、基板の表面がえぐられた形状になること
もあるので、それを防止するためである。The size of the first convex portion 14 is made to correspond to the emitter enlargement window formed in a later process. The reason why the nitride film is provided on the 5iOz film is that in the subsequent heat treatment, if only the SiO2 film is used, the 5i
Because Oz allows oxygen to pass through, the silicon substrate under the first protrusion 14 is oxidized, which not only requires a process to remove it, but also causes the surface of the substrate to be hollowed out. This is to prevent
第１図（ｂｌ参照：
全面に窒化シリコンを３０００人の厚さに成長し、ＣＨ
Ｆ ３ガスを用いる反応性イオンエツチング（Ｒｅａｃ
ｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ、 ＲＩＢ ）で全
面エツチングするごとにより、第１凸部１４の側面に窒
化膜１５を残す。Figure 1 (see BL: Silicon nitride is grown on the entire surface to a thickness of 3000 nm, and CH
Reactive ion etching using F3 gas (Reac
By etching the entire surface using tive ion etching (RIB), the nitride film 15 is left on the side surface of the first convex portion 14.
第１図ｆＣ）参照：
第１凸部１４と窒化膜１５をマスクにしてシリコン基板
をｌ１ＩＥでエツチングしてシリコン基板に第２凸部１
６を形成する。例えば塩素系のガスを用いるエツチング
で、窒化膜はシリコンに対して２０倍の選択比をもつか
ら、シリコン基板がエツチングされても窒化膜はほとん
どエツチングされない。エツチングする深さは約３００
０人とする。Refer to FIG. 1fC): Using the first convex portion 14 and the nitride film 15 as a mask, the silicon substrate is etched by IIE, and the second convex portion 1 is etched on the silicon substrate.
form 6. For example, in etching using chlorine-based gas, the nitride film has a selectivity of 20 times that of silicon, so even if the silicon substrate is etched, the nitride film is hardly etched. Etching depth is approximately 300
Assume 0 people.
第１図ｆｄ）参照：
全面に窒化シリコンを１５００人の厚さに成長し、Ｃｌ
ＩＦ５を用いるＲＩＥで第２凸部１６の側面に窒化膜１
７を残す。このとき、前記のＲＩＥに用いるレジストを
バターニングしてコレクタ領域を形成するだめの窒化膜
１７ａを残す。See Figure 1 (fd): Silicon nitride is grown on the entire surface to a thickness of 1,500 nm, and Cl
A nitride film 1 is formed on the side surface of the second convex portion 16 by RIE using IF5.
Leave 7. At this time, the resist used in the RIE is patterned to leave a nitride film 17a that will form the collector region.
第１図（１１）参照：
９００℃程度の温度でシリコン基板の熱酸化を行って約
６０００人の厚さのフィールド酸化膜Ｉ８を形成する。Refer to FIG. 1 (11): The silicon substrate is thermally oxidized at a temperature of about 900° C. to form a field oxide film I8 having a thickness of about 6000 μm.
次いで、りん酸ボイルで窒化膜をすべて除去し、コレク
タ領域形成部に例えぼりん（Ｐ＋）をイオン注入してコ
レクタ領域１９を形成する。Next, all of the nitride film is removed using phosphoric acid boiling, and ions of eborin (P+), for example, are implanted into the collector region forming portion to form the collector region 19.
第１図（ｆ）参照：
ボロンを高濃度にドープした多結晶シリコン（ポリシリ
コン）ｌ＊２０を全面に６０００人程度に、かつ、第１
凸部の５ｉ０２膜１４ａの厚さよりも若干厚めに成長す
る。その上にレジスト（例えば０ＦＰＲ−８００なる商
品名のレジスト）を８０００人の厚さに塗布して表面を
平坦化した後に、ガスはＣｈを用い、ＯＦ）’Ｒ−８０
０のレジストとポリシリコン膜２０のエツチングレート
がほぼ同一になる条件でＲ［を実施して第１凸部１４の
上のポリシリコンをエツチングする。ポリシリコンは後
述するベース電極引出し部となるものであるので、この
部分は導電性をもつメタルであってもよく、１列えばＡ
ｆｆ ／Ｗ 、 ｉ ／誓Ｓｉｘ、 Ａβ／ＭｏＳ
ｉｘなと゛も１月いることができる。See Figure 1(f): Polycrystalline silicon (polysilicon) l*20 doped with boron at a high concentration is covered with about 6,000 layers, and the first
It grows to be slightly thicker than the thickness of the 5i02 film 14a on the convex portion. After applying a resist (for example, a resist with the trade name 0FPR-800) to a thickness of 8,000 mm on top of it and flattening the surface, use Ch gas as the OF)'R-80.
The polysilicon on the first convex portion 14 is etched by performing R[ under the conditions that the etching rate of the 0 resist and the polysilicon film 20 are almost the same. Since the polysilicon serves as the base electrode lead-out part, which will be described later, this part may be made of conductive metal.
ff/W, i/Six, Aβ/MoS
ix can also stay in January.
上記した方法に代えて知られた研磨法を用いてもよい。A known polishing method may be used instead of the method described above.
第１図（ｇｌ参照：
第１凸部１４の５ｉＯ２１ＥＱ１４ａをＨＦ系のエッチ
ャントを用いるウェットエツチングで除去して凹部２１
を形成し、しかる後にポリシリコン膜２０の表面を熱酸
化して約２０００人の厚さのＳｉＯ２膜２２全２２する
。このとき、露出したシリコン基板表面にも熱酸化Ｓｉ
Ｏ２膜が形成されるので、全面に窒化膜を成長させ、そ
の上に回転塗布で有機酸化膜を付け、図示の凹部２１の
上面窒化膜をエツチングする。熱酸化後に窒化膜は除去
する。次いで、ボロン（Ｂ”）を矢印で示す如くにイオ
ン注入する。FIG. 1 (see GL: 5iO21EQ14a in the first convex portion 14 is removed by wet etching using an HF-based etchant, and the concave portion 21
After that, the surface of the polysilicon film 20 is thermally oxidized to form a SiO2 film 22 with a thickness of approximately 2000 nm. At this time, thermally oxidized Si is also applied to the exposed silicon substrate surface.
Since the O2 film is formed, a nitride film is grown on the entire surface, an organic oxide film is applied thereon by spin coating, and the nitride film on the upper surface of the recess 21 shown in the figure is etched. After thermal oxidation, the nitride film is removed. Next, boron (B'') ions are implanted as indicated by the arrows.
第１図（ｈｌ参照：
全面にレジスト（図示せず）を塗布し、それをパターニ
ングし、 ５１０２１１ｍ２２とポリシリコン膜２０を
順にエツチングし、熱処理を施して、ポリシリコン膜２
０に含まれるｐ型不純物（ボロン）をシリコン基板中に
拡散させ、第２凸部にｐ型領域２３とｐ＋型領領域２４
形成する。FIG. 1 (see HL): Apply a resist (not shown) to the entire surface, pattern it, etch the 510211m22 and the polysilicon film 20 in order, and perform heat treatment to form the polysilicon film 2.
A p-type impurity (boron) contained in 0 is diffused into the silicon substrate, and a p-type region 23 and a p+-type region 24 are formed in the second convex portion.
Form.
第１図（１）参照：
エミッタ電極をさらに細くするために、ＣｖＯ３ｉ０２
を約１５００人成長させ、ＲＩＥで凹部２１の側面に５
ｉ０２膜２５を残す。続いて砒素（Ａｓ”）をイオン注
入し、熱処理を施してｎ“領域を形成しエミッタ領域２
６とする。See Figure 1 (1): In order to make the emitter electrode even thinner, CvO3i02
About 1500 people were grown, and 5
The i02 film 25 is left. Next, arsenic (As") is ion-implanted and heat treated to form an n" region and emitter region 2.
Set it to 6.
第１図（３１参照：
次いでＳｉＯ２膜２２全２２ス電極窓を開孔し、全面に
例えばＡｆを被着し、それをバターニングしてベース電
極２７、エミッタ電極２８、コレクタ電極２９を形成し
てバイポーラトランジスタを完成する。FIG. 1 (see 31) Next, all 22 base electrode windows of the SiO2 film 22 are opened, and, for example, Af is deposited on the entire surface, which is then patterned to form a base electrode 27, an emitter electrode 28, and a collector electrode 29. Complete the bipolar transistor.
このようにして形成したバイポーラトランジスタにおい
ては、ベース電極引出し部３０は、広い領域にわたって
ｐ＋型領領域２４接触しているので、コンタクト抵抗が
軽減する。また、ベース電極引出し部３０は前記の如く
ｐ＋型領領域コンタクトがとられているので、ベース電
極窓の形成には難しい位置合せを必要としない。In the bipolar transistor formed in this manner, the base electrode extension portion 30 is in contact with the p+ type region 24 over a wide area, so that the contact resistance is reduced. Further, since the base electrode extension portion 30 is in contact with the p+ type region as described above, difficult alignment is not required to form the base electrode window.
以上のように本発明によれば、ベース領域の縮小により
ベース・コレクタ間容量が低減され、ベース電極引出し
部はｐ＋型領領域広い面積にわたって接触しているので
ベース抵抗が軽減され、さらにはベース・エミッタおよ
びベース・コレクタ間の距離を小さくできるので素子寸
法を小さ（で゛きる、などの効果がある。As described above, according to the present invention, the capacitance between the base and the collector is reduced by reducing the base region, and since the base electrode lead-out portion is in contact with the p+ type region over a wide area, the base resistance is reduced.・Since the distance between the emitter and base-collector can be reduced, the device size can be reduced.
第１図ｆａｔ〜（Ｊｌは本発明実施例断面図、第２図は
従来のバイポーラトランジスタ断面図、第３図は改良型
バイポーラトランジスタ断面図である。
第１図において、
１１はシリコン基板、
１２は埋没層、
１３はエピタキシャル層、
１４は第１凸部、
１４ａは５ｉ０２膜、
１４ｂは窒化膜、
１５は窒化膜、
１６は第２凸部、
１７と１７ａは窒化膜、
１８はフィールド酸化膜、
１９はコレクタ領域、
２０はポリシリコン膜、
２工は凹部、
２２は ５ｉ０２膜、
２３はｐ型領域、
２４はｐ＋型領領域
２５は ５ｉＯｚ膜、
２６はエミッタ領域、
２７はベース電極、
２８はエミッタ電極、
２９はコレクタ電極、
３０はベース電極引出し部
を示す。
特許出願人 富士通株式会社
代理人弁理士 久木元 彰1 is a sectional view of an embodiment of the present invention, FIG. 2 is a sectional view of a conventional bipolar transistor, and FIG. 3 is a sectional view of an improved bipolar transistor. In FIG. 1, 11 is a silicon substrate; 12 is a buried layer, 13 is an epitaxial layer, 14 is a first protrusion, 14a is a 5i02 film, 14b is a nitride film, 15 is a nitride film, 16 is a second protrusion, 17 and 17a are a nitride film, 18 is a field oxide film , 19 is a collector region, 20 is a polysilicon film, 2 is a recess, 22 is a 5i02 film, 23 is a p-type region, 24 is a p + type region 25 is a 5iOz film, 26 is an emitter region, 27 is a base electrode, 28 29 shows the emitter electrode, 29 shows the collector electrode, and 30 shows the base electrode extraction part. Patent applicant Akira Kukimoto, Fujitsu Limited representative patent attorney
Claims (1)
ルク材以外の、かつ、エッチングにおいて該バルク材と
選択比のある物質で形成する工程、第１凸部（１４）側
面に耐酸化性の、かつ、前記バルク材のエッチングにお
いて選択比をもつ第２の物質の膜（１５）を形成する工
程、 第１凸部（１４）とその側面の膜（１５）をマスクにし
て半導体基板をエッチングして第２凸部（１６）を形成
する工程、および 第２凸部にベース領域（２３、２４）とエミッタ領域（
２６）を形成する工程を含むことを特徴とする半導体装
置の製造方法。[Scope of Claims] A step of forming a first protrusion (14) on the surface of a semiconductor substrate using a substance other than the bulk material of the substrate and which has a selectivity with the bulk material during etching, 14) Forming a second material film (15) on the side surface that is oxidation resistant and has a selectivity in etching the bulk material, the first protrusion (14) and the film (15) on the side surface thereof. A step of etching the semiconductor substrate using as a mask to form the second convex portion (16), and forming base regions (23, 24) and emitter regions (23, 24) on the second convex portion.
26) A method for manufacturing a semiconductor device, comprising the step of forming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7590888A JPH01251658A (en) | 1988-03-31 | 1988-03-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7590888A JPH01251658A (en) | 1988-03-31 | 1988-03-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01251658A true JPH01251658A (en) | 1989-10-06 |
Family
ID=13589907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7590888A Pending JPH01251658A (en) | 1988-03-31 | 1988-03-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01251658A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329699B2 (en) | 1996-10-21 | 2001-12-11 | Nec Corporation | Bipolar transistor with trenched-groove isolation regions |
-
1988
- 1988-03-31 JP JP7590888A patent/JPH01251658A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6329699B2 (en) | 1996-10-21 | 2001-12-11 | Nec Corporation | Bipolar transistor with trenched-groove isolation regions |
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