JPS6018951A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To remove reactive currents in an external base region by forming the base region in an I<2>L element by implanting p type impurity ions, forming an emitter region and a collector region by implanting n<+> type ions while using a polycrystalline Si layer as a mask and shaping both in a self-alignment manner. CONSTITUTION:An n<+> type buried layer 2 is diffused and formed to the surface layer section of a p<-> type Si substrate 1, an n<-> type layer 3 is grown on the whole surface containing the buried layer 2 in an epitaxial manner, and a p<-> type region 10a as an injector and a p<-> type region 10b as an intrinsic base are formed by implanting B ions while using an SiO2 film 9 in a predetermined pattern as a mask. A polycrystalline Si layer 11 is deposited on the whole surface, B<+> ions are implanted to the layer 11 and the layer 11 is given conductivity, and windows corresponding to collector and emitter forming regions are bored to the layer 11 while being positioned on the region 10b. Sections corresponding to the windows in an SiO2 film 12 generated at that time are removed, and coated newly with thin SiO2 films 14, and As<+> ions are implanted through the films 14 to form n<+> type emitter and collector regions 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for forming a graft base of an I''L (implanted integrated logic) element in a self-aligned manner.

[Background technology]

A gate circuit is composed of a pair of complementary transistors.
As shown in FIG. 1, for example, an n-type epitaxial silicon 7 layer 3 having an n-type buried layer 2 is formed on a silicon substrate 1, and the surface of this n-type epitaxial silicon layer 3 is formed by injector (Kpnp) of a transistor ( A p-type region 4 is formed to serve as an implantation part (injection part), and a p-type region 5 is formed opposite to this to serve as a base of a multi-gate inverter (reverse NPN transistor). The pnp transistor t'i functions as a current source and load, and the plurality of collectors of the npn transistor serve as outputs.

In the I''L npn inverter, it is desirable to lower the impurity concentration Np of the p-type inverter 5, which is the base, in order to improve the reverse direction 1[, current amplification factor (βi).For this reason, refer to the same figure. The applicant has previously developed a graft base structure in which the base portion (5a) near where the collector 6 is formed is a low-concentration intrinsic base and the surrounding area is a high-concentration extrinsic base (5b).

In order to obtain such a graft base structure, the applicant of the present application injected low concentration impurity B (boron) into the entire surface as shown in Figure 2.
7 to form a p-type layer 5a for the intrinsic paste, and then pass through an oxide film mask formed on the surface as shown in FIG. Impurity B is diffused to form a p-type region 5b which will become an extrinsic base, and then, as shown in FIG. 4, a high concentration impurity As (arsenic) is diffused through a newly formed oxide film mask 8 to form an intrinsic base p- A part of the surface of the mold layer 5a becomes a collector.

However, in the process described above, the intrinsic base area is large considering the alignment margin of the masks 7 and 8 for external base diffusion and collector diffusion, and as shown in FIG. In other words, as shown by the arrow in the figure, the base reactive current I' increases and βi
It has been made clear by the applicant that a problem arises in that no improvement in performance can be expected.

[Purpose of the invention]

One object of the present invention is to provide a method for manufacturing a semiconductor device in which a graft base can be formed by self-alignment in I''LVC.

Another object of the present invention is to provide a semiconductor device that eliminates reactive current in the base and enables high-speed operation.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a low-concentration second conductivity type, e.g., p-type layer is formed as an intrinsic base on the surface of a substrate of a first conductivity type semiconductor, such as n-type silicon, and a high-concentration second conductivity layer is formed on the surface of the substrate adjacent to this p-type layer. A conductivity type, for example, a p-type region is formed as an external base, and a highly concentrated first conductivity type, for example, an n-type region, is formed on the surface of the p-type layer to form an emitter (or collector).
A method for manufacturing a semiconductor device, wherein the external base region is formed of a polycrystalline semiconductor, for example, a polysilicon layer with a high concentration of H<2 conductivity type, for example, p
The emitter (or collector) is formed by diffusion of the 10-type impurity onto the substrate surface, and the p-type impurity becomes an intrinsic paste.
The graft base is formed in a self-aligned manner by diffusing n0 type impurities into the − type layer using the polysilicon layer as a mask.

[Example 1] FIGS. 5 to 13 show an example of the present invention, which is a process sectional view showing the manufacturing process of I2L having a graft base.

(1) As shown in FIG. 5, a semiconductor substrate is prepared in which an n-type silicon layer 3 having an n-type buried layer 2 is epitaxially grown on a p-type silicon substrate (substrace) 1.

(As shown in Figure 21m'6, B (boron) is ion-implanted into the substrate at a low concentration using the oxide film (Si02 film) 9 formed on the surface of n-type silicon J@3 as a mask, and annealed. p-type J@10a, 1.O by diffusing
form b. Part of this p-type layer (10'-a
) It becomes the injector, and the other part (10b) becomes the true pace.

(As shown in FIG. 31J7, silicon is deposited to form a polysilicon layer 11 to a suitable thickness, for example, about 1 μm, over the entire surface. Thereafter, high concentration KB+ is ion-implanted into the polysilicon layer.

(4) As shown in FIG. 8, a portion of the polysilicon layer 11 is etched away by a photoresist process (not shown) to open a window on the base surface at a portion to become a collector (or emitter).

(5) By heating to 700 to 900° C. in an oxidizing atmosphere, the surface of the polysilicon layer is oxidized to form a thick (2000 years) oxide film (Si02 film) 12 as shown in FIG. B (boron) in the polysilicon layer
is diffused into the surface of the silicon substrate immediately below to form a p-1-type region 13. Part of this p+ type region (13a)
is the injector, and the other part (13b) is the external base. At this time, the surface of the substrate on which the polysilicon layer is not formed is also oxidized to form a thin (200-300λ) oxide film 14.

(6) A thin oxide film 1 on the substrate surface where a polysilicon layer is formed by etching with a hydrofluoric acid etchant.
4 is removed, but the thick oxide film 1 on the surface of the polysilicon layer is removed.
It remains as 2. Next, As (arsenic) ions are implanted to introduce As in a self-aligned manner onto the surface of the substrate where no polysilicon layer is formed.1-8 After this, As is diffused into the substrate by heat treatment as shown in FIG. Then, an n+ type region 15 which becomes a collector (or emitter) is formed.

(7) PSG (phosphorus silicate glass) film 1 on the surface
6 is deposited, then contact photoetching is performed to open a window at the electrode extraction portion, aluminum is laminated by vapor deposition, and this aluminum is patterned and etched to form an ohmic connection in each region as shown in FIG. 11. Form electrodes (Inj, B, Ink, C2). Note that the base electrode B is drawn out from the polysilicon 811.

In step (5), the oxidation rate of the polysilicon layer doped with impurities at a high concentration and the single crystal silicon that is not doped at a high concentration is high in the former and extremely low in the latter.
There is a difference in the oxide film thickness, and therefore the subsequent collector (
Since the emitter diffusion can be formed in a self-aligned manner, the object of the invention described above can be achieved.

〔effect〕

According to the present invention described in the above embodiments, the following effects cannot be obtained.

(It To form the graft base in a self-aligned manner,
The base area can be reduced, the reactive current from the emitter can be reduced by 1, and the reverse current amplification factor βi S- can be improved.

(2) Since the base electrode can be drawn out from the polysilicon layer without being taken out directly from the external base, the total surface area can be reduced.

(In 31I2L, the process margin is expanded due to the improvement in βi of the inverter.

[Example 2] In a normal npn (npn) transistor as shown in FIG. 12, the base resistance rbb' is made small (,
It may be necessary to either increase the impurity concentration of the p-type region 17, which serves as the base 07), or to reduce the distance between the base 07), the emitter, and the terminal 8).

However, there is a problem in that increasing the base impurity concentration reduces the withstand voltage. The present invention can be applied as a method of reducing the distance between base and emitter.

FIG. 13 shows another embodiment using the process of a semiconductor device having a graft base according to the present invention.

In the figure, 19 is a p-type region which becomes an intrinsic base, and 2
0 is a p-type region which becomes an external base and is formed on the substrate surface.
It is formed by diffusing doped B (boron) into the polysilicon layer 22.

21 is an n-type region which becomes an emitter, and after oxidizing the polysilicon layer 22, using this as a mask, As (arsenic) is applied.
On-implant, diffused and formed in a self-aligned manner.

By connecting aluminum to the polysilicon layer 22, the base electrode (B) can be drawn out, the base-emitter interval can be reduced, and the entire transistor can be made smaller and faster.

[Application field]

The present invention is effective when applied to an IC process having I2L, and can also be applied to a high-speed process for ordinary npn) transistors.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an example of I2L. FIGS. 2 to 4 are process cross-sectional views showing the conventional manufacturing process of I2L having a graft base. FIG. 5 to FIG. 11 are process cross-sectional views showing a manufacturing process of I2L having a graft base, which is an embodiment of the present invention. FIG. 12 is a cross-sectional view showing an example of a general transistor. FIG. 13 is a sectional view of a transistor having a graft base structure, which is another embodiment of the present invention. 1: silicon substrate, 2: n-type buried layer, 3: n-type epitaxial silicon layer, 4: injector p-type region, 5
: Pace p-type region of inverter, 5a: Intrinsic base, 5
b: external base, 6: collector n-type region of inverter, 7, 8, 9: oxide film mask, 10a: p-type layer (injector), 10R: p-type layer (intrinsic base), 11:
polysilicon layer (doped with boron), 12-thickness oxide film, 13a: p+ type region injector), 13b
: p-type region (external base), 14: thin oxide film, 15
: n-type region (collector), 16: PSG film, emitter), 19: p-type region (intrinsic base), 20: p-type region (external base), 21: n-type region (emitter),
22: Polysilicon layer. Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] 1. A low concentration second conductivity type layer is formed as an intrinsic base on the entire surface of a first conductivity type semiconductor substrate, and a high concentration second conductivity type layer is formed on the substrate surface adjacent to this second conductivity type layer. A method for manufacturing a semiconductor device in which a region of the external base region is formed, and a highly concentrated first conductivity type region is formed on the surface of the low concentration second conductivity type layer to serve as an emitter (or collector), is formed by diffusion of high concentration second conductivity type impurities in a polycrystalline semiconductor layer partially formed on the substrate surface, and the emitter (or collector) is formed by a low concentration second conductivity type impurity serving as an intrinsic base. A method for manufacturing a semiconductor device, characterized in that the polycrystalline semiconductor layer is used as a mask to diffuse a first conductivity type impurity into the layer in a self-aligned manner. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the intrinsic base and the extrinsic base are formed as bases of inverse transistors in I2L (integrated injection logic). 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the semiconductor substrate is made of silicon, and has a first conductivity type of n type and a second conductivity type.