JPS5984464A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a logical gate of uniform characteristics without depending on the difference of distance between a collector and a base terminal by a method wherein a base electrode is provided in self-alignment to the collector, thus shortening the interval, and the clearance between the base and a constant current circuit element, and each injector region are connected by means of a low resistant conductor. CONSTITUTION:An n<-> epitaxial layer 3 on a p type Si substrate wherein an n<+> layer is buried is insulated and isolated 102, and an SiO2 103, an Si3N4 double layer film, and a p<-> layer 6a, p<+> layer 71-9a are selectively provided and covered with a B doped poly Si 601. SiO2's 104 are partially formed by using Si3N4 films 203, a window is bored through the part of an Si 611, ions are implanted by masking 302, and resulting in the formation of a p<-> layer 10. An n<+> layer is completed by removing the mask 302 and annealing. When SiO2's 106 are formed by removing the SiO2's 104, the side surface of the layer 611 is formed thickly. Windows are bored through layers 7b and 9b by RIE using a mask 303, and covered with PtSi's 501, 511, and 521. Finally, it is covered with a PSG401, a window is bored, and an Al wiring 13 is laid. By this constitution, even when there are differences between each collector position and the distance of the base, an I<2>L of uniform characteristics can be obtained, and the action becomes speedy.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, particularly a base formed in a part separated from other parts in an isolation region within a semiconductor substrate, which is used as an input terminal, and has a plurality of The present invention relates to a method of manufacturing a logic gate circuit device comprising a transistor whose collector is an output terminal, and a constant current circuit element that supplies a constant current to the base of the transistor.

The following is an explanation of the integrated book Injection Logic.
gic) circuit device (hereinafter referred to as rIIL-ICJ).

) will be explained using an example.

[Prior Art J Figures 1(a) to 1(e) are cross-sectional views showing the main manufacturing steps of a conventional IIL IC in order to better understand its structure. However, what is shown here is the output (fa
This is the case where there is one n-out).

That is, in this IIL IC, as is generally done in bipolar ICs, a p-type silicon substrate (1) is doped with a high n-type impurity concentration (referred to as n+ type, hereinafter referred to as "n+ type").

) After forming the buried layer (2), the n-type image impurity concentration (
It is called n-type, and will be referred to hereinafter. ) An epitaxial layer (3) is grown, and then an oxide film (101) and a nitride film (201), which is an oxidation-resistant film, are sequentially formed and patterned into a predetermined shape. Using this as a mask, an n-type epitaxial layer is formed. After removing (3) by etching to a predetermined depth,
A p-type ion implantation layer (4) for a channel cut prevention layer is formed by ion implantation, and selective oxidation is performed using the nitride film (201) as a mask to form an isolation oxide film (102) [Fig. a)]. Next, the nitride film (201) and the oxide film (
After removing the thin oxide film (101), a thin oxide film (101) is removed.
03), boron ions are implanted through this through a required resist mask (the resist mask is not shown at this stage) to selectively implant the n-type epitaxial layer (3). After forming the p-type layer (6), a resist mask (301) with the required pattern is formed again, and boron ions are implanted through the oxide film (103) using this to form the n-type epitaxial layer (3). P+ type layers (7), (8), and (9) are formed on the substrate [Fig. 1(b)]. Next, after removing the resist mask (301), a phosphorus glass film ('401) is grown on the entire upper surface by the CVD method.

p-type layer (6) and p+ type M<1), (s),
(9) is annealed at the same time, and the p-type layer (6
a) and p+ type layers (7a), (8a), and (9a) are formed [FIG. 1(C)]. Next, p-type/1ff(6
A window is formed in the phosphorus glass film (401) and the oxide film (103) in a part above a), and n-type impurities are introduced from there,
By annealing, an n1 degree fi (10a) is formed, and a p-type M (6a>) is formed as a p-type layer (6a).
b), p + type Jm (7a), (8a), (9a) (
7b), (8b).

(9b) respectively [Fig. 1(d)]. Subsequently, windows are formed on each of the p-type layers (7b) and (9b), and electrode wiring is performed through the metal silicide layer (501) together with the window portion above the n+-type layer (10a). ) the injector electrode (11) is connected to the p+ type/1l (7b) which is the emitter of the transistor;
Connect the input electrode (12) to the terminal M (9b) for taking out the electrode connected to 6b), and connect the output electrode 1 (13) to the n+ type layer (10a) which is the collector of the reverse operation npn) transistor. Then, the IIL gate of is completed [Fig. 1(e)].

The basic one-output IIL gate has been shown above, and FIG. 2 is a plan view of this conventional IIL gate having three outputs and two interconnections between gates. (13), (14) )
, (15) are respectively the first collector CI+second collector CI
The three output electrodes connected to the collector C2 and the third collector C3, (21) and (22) are inter-gate wirings. The three collectors CI+C2+03 are arranged in order from the input (base) electrode (12). Now, as shown in FIG. 3, the current amplification factor βU of the reverse operation npn transistor is greatly reduced in the high current region where the collector current IcO is far from the base electrode (12). This is thought to be because the collector whose base resistance is far from the base electrode becomes larger. Also, the gate propagation delay time tpd and power consumption Pd of
It is known that there is a power delay characteristic as shown in FIG. (For example, Semiconductor Transistor Research Group, IEICE Technical Report 5SD76-89. p37: Hi
gh 5peed IIL with 5elf -A
ligatedDouble)ifuaion I
njector CS2L ) ).

Here, if the transistor characteristics are the same (with the same base area and the same pnp), the relationship tpdmin ``βU'' holds as shown in Figure 5, so as shown in Figure 6, where is the collector far from the base electrode? The larger the distance from the electrode (-8), the larger the minimum delay time tpdmin.
As shown in Table 1, the performance of the L gate varies among the output electrodes, and is limited by the large delay time of the output electrode that is farthest from the base electrode.

Furthermore, even if the manufacturing method is the same, the current amplification factor βU is proportional to the ratio S c /S H of the collector area SC to the base surface MSa, as shown in FIG. In the conventional structure, the second
As shown in the figure, the base region consisting of the p- shadow region (6b) and the connected p+ type regions 8b) and (9b) extends below the gate interconnections a (21) and (22). As shown in Table 1, the base surface MSn is large, so the ratio Sc/Ss with the collector area Sc becomes very small, the current amplification factor βU becomes small, and even the collector C1 closest to the base electrode has a minimum delay. Time tPdmi
n increases, and the power supply current l1nj is further reduced to 200/j
The delay speed tpd also increases when it is set to about A/gate.

Table 1 and FIG. 8 show the minimum gate delay time tpdmi depending on the relative position of each terminal. This is a diagram showing that the distances between the same collection bases are different. -B, the minimum delay time tpdmin is smaller when the injector electrode is closer to the collector electrode (curve B) than when the injector electrode is closer to the base electrode (curve A). Figure 9 is a schematic sectional view for explaining the configuration and operation in the former case (injector base-collector arrangement) and Figure 10 in the latter case (injector collector base arrangement R), and ■ is a schematic cross-sectional view for explaining the configuration and operation of the latter case (injector collector base arrangement R). , B is a base terminal, C is a collector terminal, and E is a grounded emitter terminal. In both Figures 9 and 10, Figure (a) shows the current when the gate output switches from a low level to a high level (L→H), and Figure (b) shows the current when the gate output switches from a high level to a low level (L→H). The arrow indicates the current when H-+L). The I (npn, which operates in the opposite direction to -+L) transistor is in the ON state, and the operation is completed. When n flows, this means that the base current l1nj supplied from the injector is npn
) to act as the base current of the transistor,
pnp as a base current supply source) npn as a switching transistor from the collector junction of the transistor
The distance to the active base region of the gingister is smaller in the case of FIG. 10, the base current is supplied earlier, and the npn transistor turns on faster in the case of FIG. 10 than in the case of FIG.

Furthermore, since the transistor (L-+H means Hpn) is in the OFF state, IIL is a saturation type logic (however, if a Schottky clamp (5chottky clamp) is used, the saturation is small. ], and the switching transistor (npn) transistor changes from a deep ON state to an O state.
To shift to the FF state, excess charges (holes) accumulated in the active region must be removed from the base terminal. On the other hand, the base current l1nj always flows in from the injector and flows out to the base terminal. Follow゛C
1 If there is an active base region between the base terminal and the injector as shown in Figure 1O, excess charge will drift to the base terminal and flow through with the flow of the above-mentioned inj, but as shown in Figure 9, the excess charge will drift to the base terminal and flow through. If there is an active base region apart from the flow, excess charge can only flow by diffusion;
It takes a longer time to remove the excess charge than in the case of FIG. 10, and as a result, the L-+H switching is also faster in FIG. 10 than in the case of FIG.

However, it will be appreciated that the operating speed of the gate will be faster with the injector collector based arrangement.

However, in the conventional IIL structure, it is difficult to adopt this arrangement when the number of collector outputs increases.

[Summary of the invention]

This invention has been made in view of the above points, and is a low-resistance electric circuit connecting a base terminal constituting an input terminal, each base region corresponding to each collector, and a constant current circuit element that supplies a constant current to the base. By providing this, even if there are multiple collectors, there will be no difference in characteristics between them, and by connecting each injector region corresponding to each collector with a low resistance electric path, it will also be possible to - The aim is to obtain an IC with excellent characteristics by forming it in an aligned manner.

[Embodiments of the invention]

11(a) to (y) are cross-sectional views showing the main stages of the manufacturing process in order to better understand the structure of one embodiment of the present invention, and FIG. 1(a) = (e) and Equivalent parts are indicated by the same symbols. In this embodiment as well, FIGS. 1(a) and (b)' in the conventional example! , are processed in exactly the same way. Thereafter, a nitride film (202) is deposited to form the base region of the lateral pnp transistor (n-
Nitrided B (202) except for epitaxial layer (3)
After opening a window in the oxide II (103), a polysilicon film (601) is deposited on the entire upper surface, low concentration boron ions are implanted, and annealing is performed. At this time, p single layer (6a), p'' type layer C7a), (8a),
(9a) is formed [FIG. 11(a)]. Next, the dielectric film (203) is de-positioned to cover the polysilicon film (611) in the collector region, the p++H (9a'), and the isolation oxide film (102) in Vj4 contact with the polysilicon film (611) in the collector region. (621) and p++H (7
Leaving the nitride film on the polysilicon film (631) extending from above a) to the adjacent isolation oxide jK (102), selective oxidation is performed using this patterned nitride film (203> as a mask) to form polysilicon. Oxide film (104)
[Fig. 11(b) J0] Next, a window is opened in the polysilicon film (611), and the polysilicon film (611) is completely converted to
A resist film (3) is applied to cover the (621) and (631) parts.
02) and implants arsenic ions to form an n+ type layer (IOCt P- type*(6a)) on a part of the surface portion of the collector layer (FIG. 11(C)).Next, The resist film (302) is removed and annealed.
pn) While completing the n+ type collector layer (10a) of the transistor, the p- type layer (6b) and the p+ type Ff#
Complete 4(7b), (8b), and (9b).

After that, after removing the entire oxide film (104), polysilicon J]IN is oxidized at a low temperature and becomes a highly concentrated n+ layer.
A thick oxide film is formed on the (61i,') surface and a thin oxide film is formed on the silicon surface and the polysilicon film (621) and (631) surface [FIG. 11(d)]. Next, a thick oxide film (
106), a resist film (AO3) is first applied to cover the polysilicon U (611) of the collector.
Polysilicon films (621), (631
) and a part of the thin oxide film (105) on the substrate surface are removed (FIG. 11(e)). Resist film (30
3) After removal, the remaining thin oxide film (10
After removing only 5), the entire nitride film (203) is removed using hot phosphoric acid, etc., and Pt is applied to the entire upper surface of the ridge.

A silicide-forming metal film (not shown) such as Pd, W, or Mo is formed and sintered to form a metal silicide film (not shown).
501), (511), and (521) are formed only on the silicon and polysilicon surfaces [Fig. 11(f)
].

Next, only the metal film is removed using, for example, aqua regia, and a passivation LN (401) (for example, a phosphorus glass film or a plasma nitride film) is deposited thereon, and then a required resist mask (not shown) is used to A window for contact will be opened.

After that, using low resistance metals such as At and Au, as before,
This embodiment is completed by forming the connection wiring (13), as shown in FIG. 11 (7). The plane pattern diagram at this time is the 12th
As shown in the figure.

Now, the first advantage of this embodiment is that the distance Dc- between the collector (output) electrode and the base (input) electrode is
B is so small that it can be almost ignored. That is,
In the conventional device, the width of the At wiring extends beyond the width of the contact part of the electrode, so the above distance rLaD C-B
could not be made smaller due to restrictions on wiring width. In this example, the base electrode wiring is pushed out onto the isolation oxide film (102) by using a low resistance polysilicon film (621) and a metal silicide film (521), so there are no restrictions like in the conventional device. , as shown in FIG. 12, a metal silicide film (521) is formed on a polysilicon film (621).
The end of the metal sisoside Jl (501) connected with the oxide film (106) is in contact with the end of the oxide film (106).
The remaining width of 6) is substantially the same as above. -6, so the value can be made negligibly small.

FIG. 13 shows xo, ? which has the output of the structure of this invention.
- FIG. As can be seen from the figure, n
For each collector of the pn transistor, the base electrode (
12) is a polysilicon IQ (621) whose resistance has been lowered by a metal silicide film (521), and the current source is a pnp
) is connected to the collector of the transistor, and each injector is similarly connected to the electrode (11) through a silicide film on the polysilicon film (631), and there is no electrical difference between the collectors, as shown in Table 2. As shown, the characteristics are also the same.

Furthermore, since the base electrode wiring consists of the polysilicon film (621) on the non-active region and the metal silicide film (521) thereon, the gate spacing m (21), (22), which was essential in the conventional structure, is The base diffusion layer (6
b), (8b), (9b) No need for power! : ;'
j L The base area S8 itself has a large ratio S C/'S B to the collector surface M S c which is small, and therefore the current amplification factor βU also becomes large. Also, since the injector collector base arrangement explained in Fig. 10 can be done,
Gate operation speed can be increased.

Table 2 Although the above embodiment describes a gate isolation method using selective oxidation, this invention can also be applied to other ordinary gate isolation methods and color separation methods using high impurity concentration regions. Although the case where the layer has a graft structure has been described, the present invention can also be applied to a buried base structure.

〔Effect of the invention〕

As described in detail above, in this invention, the base electrode is formed in a self-line manner with respect to the collector, and the collector-base distance is made very small. We connected the constant current source circuit element to the constant current source circuit element using a low resistance conductor made of polysilicon film, and also connected each injector using the same low resistance conductor, so the position of each collector and the base terminal were Even if there is a difference in distance, the characteristics are made uniform, and an excellent logic gate IC can be obtained. Furthermore, with the above configuration, an injector collector base arrangement can be realized and the operating speed can be increased.

[Brief explanation of drawings]

Figures 1 (a) to (e) are cross-sectional views showing the main steps in the manufacturing process of a conventional AI L-IC, and Figure 2 is a cross-sectional view of the conventional I
The plan view of the IL-IC, Figures 3 and 4, show the relationship between the collector current Ic and the current amplification factor, and the power consumption Pd, of a conventional IIL gate having three collectors CB, C2, and C3. Figure 5 is a diagram showing the relationship between current amplification factor βU and minimum delay time jpchnin, and Figure 6 is a diagram showing the relationship between collector and base electrode distance Do and minimum delay time. time tpd
Figure 147 shows the relationship between the collector base surface well ratio S. A diagram showing intercropping between / S rl and current amplification factor βU,
Figure 8 shows the minimum delay time t, p depending on the relative position of each terminal.
dmi. Figure 9 is a schematic sectional view to explain the configuration and operation in the case of an injector base-collector arrangement, 1 Figure 10 is a diagram showing the configuration and operation in the case of the injector collector base arrangement. Schematic sectional views for explanation; FIGS. 11(a) to (2) are sectional views showing states at main stages of manufacturing an embodiment of the present invention; FIG. 12 is a plane view in FIG. 11(P). Figure 813 is a plan view of this embodiment. (6b)...Base layer, (8b), (9b) ・
... Base extraction layer, (10a) ... Collector layer, (11) ... Injector terminal, (12) ...
...Base terminal (electrical wiring), (13), (14)
, (15)... Collector terminal (post wiring), (21
), (22)...Inter-wiring between logic gate circuit devices,
(501), (,511), (521), (531
)・Contest・Metal silicide film, (601), (611
), (621), (631) ... ・Polysilicon film. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - Fig. 1 Fig. 1 Fig. 2 b Fig. 8 Dc-e (Pm) Fig. 11 Fig. 11 Fig. 12 Fig. 11 ■Year:,' +14 +3('i,l゛Licensing Agency IX☆ 1 Case description Patent Application No. 57-195442 25 and Ming's name (Ru, Method of Manufacturing Semiconductor Integrated Circuit Devices 3.1 Yamamasa) 1- and name (601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama 4, Agent 5, Detailed explanation of the invention in the specification subject to amendment (6, Contents of amendment (1) Specification In lines 3 to 5 of page 15, ``Only form...on top'' is corrected as follows: [After forming only, remove only the metal film with, for example, aqua regia [Figure 11 ( f)]. Then, on top of it” (21, same page, line 19, “low resistance” is deleted.

Claims (2)

[Claims] (1) A transistor that is formed in a separated region in a semiconductor substrate and is separated from other parts, and has a base as an input terminal and a plurality of collectors as output terminals, and a fixed box and current to the base of this transistor. In a device having a logic gate circuit device comprising a constant current circuit element to be supplied, a first step of forming a first conductivity type layer surrounded by an isolation region and constituting an emitter region on the surface of a semiconductor substrate; 1. A second step of forming a base layer of a second conductivity type and an emitter layer of a constant current circuit element in the barrel-shaped layer; a third step of forming a two-layer film consisting of an oxide film and a nitride film so as to at least cover the semiconductor substrate; a fourth step of forming a silicon film of the second conductivity type over the two-layer film, the semiconductor substrate surface, and the isolation region; a fifth step of forming a nitride film only on the surface of the silicon film corresponding to a portion that will become a collector region, a portion that will become a base electrode, and a portion that will become an emitter electrode of a constant current circuit element; a sixth step of converting the film selectively and completely into an oxide film in that part; a seventh step of introducing a first conductivity type impurity into the silicon film in the collector region and further forming a first conductivity type layer serving as a collector in the base region from the silicon film; and removing the converted oxide film. Eighth step, an oxide film formed on the side wall of the silicon film of the collector portion containing the first conductivity type impurity by low temperature oxidation on the semiconductor substrate surface and the base and the silicon film surface that will become the emitter electrode of the constant current circuit element. a ninth step of forming a relatively thick oxide film; a tenth step of selectively removing the oxide film formed on the surface of the silicon film that will become the base and emitter electrode of the constant current circuit element; anisotropic etching; an eleventh step of removing a thin oxide film on the substrate surface except for an oxide film on the side wall of the silicon film of the collector; a twelfth step of removing the entire nitride film; and a metal silicide on the silicon film and the substrate silicon surface. A semiconductor integrated circuit device comprising a thirteenth step of forming a passivation film, a fourteenth step of opening a window for electrode wiring after forming a passivation film, and a fifteenth step of forming a low resistance metal wiring. Production method. (2) A method for manufacturing a semiconductor integrated circuit device according to claim 1, characterized in that a polycrystalline silicon film is used as the silicon film.