JP3333863B2 - Manufacturing method of bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a self-aligned N
The present invention relates to a method for manufacturing a bipolar transistor in which a PN transistor and a ring-base type lateral PNP transistor are formed on the same substrate.

[0002]

2. Description of the Related Art Bipolar transistors have been increased in speed with miniaturization using a self-alignment method, and have been used mainly in fields requiring ultra-high-speed operation. However, CMOS is also being used in fields requiring large-scale, high-speed operation, taking advantage of the improvement in operation due to miniaturization and the advantages of high integration. Therefore, even in the case of a bipolar transistor, a region where the CMOS is not good, such as a high-speed operation region exceeding 1 GHz, is targeted.
In addition, in order to coexist with CMOS, application to a field where low voltage is required has become indispensable.

For example, in portable devices and the like, it is necessary to lower the voltage in order to reduce power consumption as much as possible. In such a field, it is required to form a circuit capable of operating at a low voltage and at a high speed, and a corresponding process technology is also required. As a method corresponding to these, NPN
At the same time as the transistor, a PNP transistor may be integrated and formed on the same substrate.

Here, the following two types are conventionally used for integrating an NPN transistor and a PNP transistor. First, there is a case where a vertical NPN transistor and a PNP transistor are integrated. The planar type N
This is a case where a PN transistor and a lateral PNP transistor are integrated.

[0005]

Conventionally, the above-mentioned configuration has the following problems.
First, when a vertical transistor is integrated, the NPN transistor, which determines most of the performance of the transistor, has a vertical structure, and thus has a high-speed performance of 30 GHz or more. However, when a vertical NPN transistor and a vertical PNP transistor are formed on the same substrate, the respective portions cannot be formed identically, and are formed alternately.

For example, since the introduction of the impurity into the base of the NPN transistor and the introduction of the impurity into the base of the PNP transistor cannot be performed at the same time, one of them is formed first and then the other is formed. In this case, the previously formed impurity-introduced portion is also subjected to the heat treatment in the impurity introduction to be formed later, so that more heat is applied than necessary. That is, when a vertical NPN transistor and a PNP transistor are integrated, there is a problem that the process is very complicated and a stable transistor cannot be formed.

In view of the above, a planar-type NPN
In the case where the transistor and the lateral PNP transistor are integrated, there is no limitation on the process as described above, and the transistor can be stably manufactured at an easy process cost. However, since the NPN transistor is of a planar type, there is a problem that the performance of the transistor is as low as several GHz.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems.
An object of the present invention is to enable a PN transistor to be stably manufactured with high speed performance.

[0009]

According to the method of manufacturing a bipolar transistor of the present invention, a base lead layer into which an impurity connected to a P-type base of an NPN transistor is introduced on a substrate and a P-type transistor connected to a lateral PNP transistor collector are provided. Collector extraction layer into which the impurity of the shape is introduced,
And after forming an insulating layer overlying them, the emitter, base,
A step of performing ion implantation for forming a base of an NPN transistor in a state where a first mask pattern is formed on a region where a collector is to be formed, and removing the first mask pattern
After that, the NPN transistor and the lateral PNP transistor
Forming, for each of the transistors, an emitter opening for connecting an emitter extraction layer to be formed thereon and a region where the emitter is to be formed on the insulating layer; and thereafter, depositing and forming a semiconductor layer on the insulating layer And the lateral PN
The emitter of the P transistor, a base, in a state of forming a second mask pattern on the region in which the collector is formed, a step of introducing an impurity to be N-type semiconductor layer, the second Ma <br/> Sukupatan Introducing a p-type impurity into the semiconductor layer with the third mask pattern formed on the region where the base of the NPN transistor is formed after the removal;
After removing the third mask pattern, a heat treatment is performed to diffuse the impurity introduced into the semiconductor layer, thereby forming an NPN transistor.
Forming an emitter of each of the transistor and the lateral PNP transistor, and diffusing an impurity introduced into the collector extraction layer to form a collector of the lateral PNP transistor. Therefore, the NPN transistor has a vertical structure in which the impurity diffusion region serving as the emitter is formed on the surface of the substrate in the impurity diffusion region serving as the base of the substrate.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram and a plan view showing a configuration of a bipolar transistor according to the present invention. In FIG. (A), (b), 1 is P ^- form of the substrate, 2 an N ⁺
Impurity introducing layer, 3 is an insulating layer for element isolation, 4 is an N ⁻ -type impurity layer, 5 is an insulating layer made of silicon oxide,
Reference numeral 6 denotes an insulating layer made of silicon nitride. Further, 7 is an emitter, 7a is an emitter extraction layer made of polysilicon into which boron is introduced, 8 is a collector, 8a is a collector extraction layer made of polysilicon into which boron is introduced,
Reference numeral 9 denotes a base, 9a denotes a base extraction layer into which phosphorus is introduced, 10 denotes an insulating film for separating each extraction layer from others, 11 denotes an emitter electrode, 12 denotes a collector electrode, and 13 denotes a base electrode.

In FIG. 1C, reference numeral 7 'denotes an emitter, 7a' denotes an emitter lead-out layer made of phosphorus-doped polysilicon, 8 'denotes a collector, and 8a' denotes a phosphorus-doped polysilicon. Collector drawer layer,
9 'is a base, 9a' is a base lead layer made of polysilicon into which boron is introduced, and the other is a base drawing layer shown in FIG.
Is the same as

FIG. 1A shows a cross section of a lateral PNP transistor, and FIG. 1B is a plan view showing an arrangement of an emitter 7 and a collector 8 thereof. FIG. 1 (c) shows NP
FIG. 1D is a plan view showing the arrangement of an emitter 7 and a base 8 of the N transistor. Actually, the NPN transistor shown in FIG. 1C is formed next to the lateral PNP transistor shown in FIG.

As shown in FIG. 1, the structure of a lateral PNP transistor is similar to that of an NPN transistor. The major difference is in the direction in which the current flows from the emitters 7 and 7 '. In the case of the NPN transistor, the current flows in a direction perpendicular to the surface of the substrate 1, but the lateral PN shown in FIG.
In a P transistor, the current flows in a direction parallel to the substrate 1.

Here, the width of the bases 9 and 9 'for determining the performance of the transistor can be determined in a self-aligned manner as will be described later, so that a fine structure can be easily obtained. Of course, the base width can be determined arbitrarily because it can be determined by dimensional control by photolithography. Further, the lateral PNP transistor shown in FIG. 1 has a ring shape in which the emitter 7 and the collector 8 are arranged on a concentric ellipse as shown in FIG. This makes it difficult for the breakdown voltage to occur.

These transistors are manufactured in substantially the same steps as those of conventionally known high performance self-aligned NPN transistors. Further, the following two steps are added according to the present invention. First, a separate step of ion implantation for forming the base. Second, a separate step of ion implantation for forming an emitter. When the base width is controlled by photolithography, an emitter opening step by selective etching using a mask pattern formed by photolithography is added to the above-described step.

Referring to FIG. 2, a main part of a method for manufacturing a bipolar transistor according to the present invention will be described. Here, the manufacturing process will be described with reference to the upper part of the emitters 7 and 7 'in FIG. Here, FIG.
(A), (c), (e), (g), and (i) show the emitter formation region of the NPN transistor.
(D), (f), (f '), (h), and (j) show the emitter formation region of the lateral PNP transistor.
FIGS. 2A and 2B show the insulating layers 5 on the substrate 1.
6, a predetermined portion on the emitter forming region formed so as to be sandwiched between the insulating layers 3 (FIG. 1) is opened, and the base extraction layer 9a '(FIG. 1C) and the collector extraction layer 8a ( FIG. 1A shows a state in which an insulating layer 21 made of silicon oxide has been formed after being formed. Note that the insulating layer 21 is a portion to be the insulating film 10 in FIG.

First, as a separate step of ion implantation for forming the base, the lateral PNP in the above-described state is used.
A resist pattern 22 is formed on the transistor portion, and boron ions are implanted, for example (FIG. 2A,
(B)). Then, by performing a heat treatment or the like after removing the resist pattern 22, a base 9 ′ (FIG. 1C) is formed. Thereafter, as shown in FIGS. 2C and 2D, an oxide film 23 is formed, and a polysilicon film 24 is formed thereon.
Is formed (FIGS. 2E and 2F). Here, the concentration of the base 9 may be adjusted by selectively ion-implanting the lateral PNP transistor portion. When a finer lateral PNP transistor is formed in a self-aligned manner, the characteristics can be improved by adjusting the base concentration in this manner.

The oxide film 23 and the polysilicon film 24 are anisotropically etched to form an emitter opening 25 (FIGS. 2E and 2F). And FIG.
(G) and (h), a polysilicon layer 26 is deposited and formed thereon, and a resist pattern 27 is formed on the lateral PNP transistor portion (FIG. 2 (h)). I do. In this ion implantation, arsenic may be used.

Next, after removing the resist pattern 27,
As shown in FIGS. 2I and 2J, a resist pattern 28 is formed on the NPN transistor portion (FIG. 2I), and for example, boron is ion-implanted. By the above, NP
This means that phosphorus has been introduced into the polysilicon layer 26 on the N transistor portion and boron has been introduced into the polysilicon layer 26 on the lateral PNP transistor portion.

Then, after this, the emitter extraction layer 7a
(FIG. 1A) and the emitter extraction layer 7a '(FIG.
By patterning the polysilicon layer 26 so as to have the shape of (c) and performing heat treatment, the impurities are diffused from the respective portions to form the emitter 7 and the emitter 7 '. Note that, as shown in FIG. 2F ', the emitter opening 25 may be formed by selective etching using a resist pattern 29 having a portion where the emitter opening 25 is opened as a mask.

FIGS. 3, 4 and Table 1 below are characteristic diagrams showing characteristics of the bipolar transistor manufactured as described above. FIG. 3 shows the D of the lateral PNP transistor when the emitter opening is manufactured in a self-aligned manner.
FIG. 4 shows the DC characteristics of the lateral PNP transistor when the emitter opening is formed by selective etching by photolithography. Table 1 shows the high-frequency characteristics of the lateral PNP transistor when the emitter opening is formed by selective etching by photolithography.

[0022]

As is clear from FIGS. 3, 4 and Table 1, it can be understood that according to the above embodiment, a high-speed bipolar transistor can be easily manufactured. As is apparent from the above description, it can be understood that the above-described embodiment can be realized regardless of the shape of the base extension portion.

[0024]

As described above, according to the present invention, ion implantation for forming a base of an NPN transistor is selectively performed, and impurities are separately implanted into semiconductor layers on respective regions in forming an emitter. This was thermally diffused to form an emitter. Therefore, N
In the PN transistor region, an impurity diffusion region serving as an emitter is formed on the surface of the substrate in the impurity diffusion region serving as the base of the substrate, and has a vertical structure. On the other hand, the formation of the impurity regions serving as the emitter and the collector is performed in the same heat treatment step. As a result, there is an effect that the NPN transistor and the PNP transistor can be stably manufactured with high speed performance.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a bipolar transistor according to the present invention.

FIG. 2 is an explanatory view showing a main part of a method for manufacturing a bipolar transistor according to the present invention.

FIG. 3 is a characteristic diagram showing characteristics of a bipolar transistor manufactured according to the present invention.

FIG. 4 is a characteristic diagram showing characteristics of a bipolar transistor manufactured according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Impurity introduction layer, 3, 5, 6 ... Insulating layer, 4
... impurity layer, 7, 7 '... emitter, 7a, 7a' ... emitter extraction layer, 8, 8 '... collector, 8a, 8a' ...
Collector lead-out layer, 9, 9 '... base, 9a, 9a'
... Base extraction layer, 10 ... Insulating film, 11 ... Emitter electrode, 12 ... Collector electrode, 13 ... Base electrode, 21 ... Insulating layer, 22, 27, 28, 29 ... Resist pattern, 23
... an oxide film, 24 ... a polysilicon film, 25 ... an emitter opening, 26 ... a polysilicon layer.

────────────────────────────────────────────────── (5) References JP-A-3-159130 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/082 H01L 29/73 H01L 21 / 8228 H01L 21/331

Claims (1)

(57) [Claims] 1. A method of manufacturing a bipolar transistor in which an NPN transistor and a ring-base type lateral PNP transistor are integrated on the same substrate, wherein impurities connected to the P-type base of the NPN transistor are formed on the substrate. After forming the introduced base extraction layer, the collector extraction layer connected to the lateral PNP transistor collector into which a P-type impurity is introduced, and an insulating layer overlying them, the emitter of the lateral PNP transistor, base,
Performing ion implantation for forming a base of the NPN transistor in a state where a first mask pattern is formed on a region where a collector is to be formed; and removing the first mask pattern, and then removing the NPN transistor.
Transistor and lateral PNP transistor
Te, wherein the insulating layer, forming an emitter opening portion for connecting the region where the emitter contact layer and the emitter formed on this is formed, thereafter, depositing a semiconductor layer on the insulating layer And a step of performing an emitter, a base,
In state of forming a second mask pattern on the region in which the collector is formed, a step of introducing an impurity to be N-type to the semiconductor layer, after removing the second mask pattern, the base of said NPN transistor A step of introducing a P-type impurity into the semiconductor layer in a state where a third mask pattern is formed on the region where is formed, and after removing the third mask pattern, performing a heat treatment, By diffusing impurities introduced into the semiconductor layer
The NPN transistor and the lateral PNP transistor
Forming a collector of the lateral PNP transistor by forming an emitter of each of the transistors and diffusing an impurity introduced into the collector lead-out layer.