JPH0473300B2 - - Google Patents
Info
- Publication number
- JPH0473300B2 JPH0473300B2 JP57189545A JP18954582A JPH0473300B2 JP H0473300 B2 JPH0473300 B2 JP H0473300B2 JP 57189545 A JP57189545 A JP 57189545A JP 18954582 A JP18954582 A JP 18954582A JP H0473300 B2 JPH0473300 B2 JP H0473300B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- transistor
- collector
- oxide film
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 229910021332 silicide Inorganic materials 0.000 claims description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 18
- 150000004767 nitrides Chemical class 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 5
- 238000000605 extraction Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 230000003321 amplification Effects 0.000 description 7
- 238000003199 nucleic acid amplification method Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Bipolar Integrated Circuits (AREA)
Description
〔発明の技術分野〕
この発明は半導体集積回路装置、特にインテグ
レーテツド・インジエクシヨン・ロジツク
（Integrated Injection Logic）回路装置（以下
「IIL・IC」という。）及びその製造方法に関する
ものである。
〔従来技術〕
第１図ａ〜ｅは従来のIIL・ICの構造をよりよ
く理解するためにその製造主要工程における状態
を示す断面図である。ただし、ここで示すのは出
力（fan−out）１個の場合である。
すなわち、このIIL・ICはバイポーラICで一般
に行なわれているように、ｐ型シリコン基板１上
にｎ形高不純物濃度（n+形と言い、以下これに
準ずる。）埋込み層２を形成したのち、ｎ形低不
純物濃度（n-形と言い、以下これに準ずる。）エ
ピタキシヤル層３を成長させ、ついで酸化膜１０
１と耐酸化膜である窒化膜２０１とを順次形成し
て、所定形状にパターニングし、これをマスクに
してn-形エピタキシヤル層３を所定深さだけエ
ツチング除去してから、イオン注入法によりチヤ
ネルカツト防止層用ｐ型イオン注入層４を形成
し、窒化膜２０１をマスクとして選択酸化を行な
つて分離酸化膜１０２を形成する〔第１図ａ〕。
次に、窒化膜２０１と酸化膜１０１とを除去した
のち、あらためて薄い酸化膜１０３を形成したの
ち、これを通し、所要のレジストマスク（この段
階でのレジストマスクは図示せず。）を介してホ
ウ素イオンを注入して、n-形エピタキシヤル層
３に選択的にp-形層６を形成した後に、あらた
めて所要パターンのレジストマスク３０１を形成
し、これを用いて酸化膜１０３を通してホウ素イ
オンを注入して、n-形エピタキシヤル層３にp+
形層７，８，９を形成する〔第１図ｂ〕。次にレ
ジストマスク３０１を除去後、全上面にCVD法
によつてリンガラス膜４０１を成長させた上で、
このリンガラス膜４０１、p-形層６およびp+形
層７，８，９のアニーリングを同時に行なつて
p-形層６ａおよびp+形層７ａ，８ａ，９ａを形
成させる〔第１図ｃ〕。次に、p-形層６ａの上の
一部にリンガラス膜４０１および酸化膜１０３に
窓をあけ、ここからｎ形不純物を導入し、アニー
ルすることによつてn+形層１０ａを形成すると
ともに、p-形層６ａをp-形層６ｂに、p+形層７
ａ，８ａ，９ａを７ｂ，８ｂ，９ｂにそれぞれ成
長させる〔第１図ｄ〕。つづいて、p+形層７ｂお
よび９ｂ上にそれぞれ窓をあけ、上記n+形層１
０ａの上の窓の部分とともにそれぞれ金属シリサ
イド層５０１を介して電極配線を行ない、pnpト
ランジスタのエミツタであるp+形層７ｂにイン
ジエクタ電極１１を、pnpトランジスタのコレク
タであり、かつ逆方向動作npnトランジスタのベ
ースであるp-形層６ｂにつながる電極取出し用
p+形層９ｂにインプツト電極１２を、さらに、
逆方向動作npnトランジスタのコレクタであるn+
形層１０ａにアウトプツト電極１３をそれぞれ接
続形成して、このIILゲートを完成させる〔第１
図ｅ〕。
以上基本的な１出力のIILゲートを示したが、
第２図はこの従来構造になる３出力と２本のゲー
ト間配線とを有するIILゲートの平面図で、１３，
１４，１５がそれぞれ第１のコレクタC1、第２
のコレクタC2、第３のコレクタC3につながれた
３つのアウトプツト電極、２１，２２はゲート間
配線である。３つのコレクタC1，C2，C3はイン
プツト（ベース）電極１２から近い順に配列され
ている。さて、逆動作npnトランジスタの電流増
幅率βuは第３図に示すようにベース電極１２か
ら遠いコレクタほどコレクタ電流Icの高電流域で
大きく低下する。これはベース抵抗がベース電極
から遠いコレクタほど大きくなるからであると考
えられる。また、IILのゲート伝播遅延時間tpdと
消費電力Pdとの間には第４図に示されるような
電力遅延特性のあることが知られている。（例え
ば、半導体トランジスタ研究会．信学技報SSD76
〜89 p37：High Speed IIL with Self−
Aligned Double Diffusion Injector〔S2L〕）。
ここで同一ベース面積、同一pnpトランジスタ
特性であれば第５図に示すようにtpdnio∝βu1/2の
関係が成立するので、第６図に示すようにベース
電極から遠いコレクタほど（コレクタとベース電
極との距離DC-Bが大きいほど）最小遅延時間
tpdnioが大きくなる。よつて、このように従来の
製造方法によるIILゲートの性能には第１表にそ
の一例を示すように各アウトプツト電極間で特性
の差異があり、ベース電極に最も遠いアウトプツ
ト電極の大きい遅延時間で制約される。さらに同
一製造法であつても、電流増幅率βuは第７図に
示すようにコレクタ面積SCのベース面積SBに対す
る比SC／SBに比例する。従来の構造では第２図に
示したようにp-形領域６ｂとこれにつながるp+
形領域８ｂ，９ｂとからなるベース領域がゲート
間配線２１，２２の下にまでわたつて存在し、第
１表に示すようにベース面積SBが大きく、従つて
コレクタ面積SCとの比SC／SBが非常に小さくな
り、電流増幅率βuが小さくなり、ベース電極に
最も近いコレクタC1でも最小遅延時間tpdnioは大
きくなり、さらに、電源電流Iiojを200μA／gate
程度としたときの遅延速度tpdも大きくなる。
[Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, particularly an integrated injection logic circuit device (hereinafter referred to as "IIL-IC") and a manufacturing method thereof. [Prior Art] Figures 1a to 1e are cross-sectional views showing the main manufacturing steps of a conventional IIL/IC in order to better understand its structure. However, what is shown here is the case of one output (fan-out). That is, this IIL IC is manufactured by forming an n-type high impurity concentration (referred to as n + type, hereinafter referred to as this) buried layer 2 on a p-type silicon substrate 1, as is generally done in bipolar ICs. , an n-type low impurity concentration (referred to as n - type, hereinafter referred to as this) epitaxial layer 3 is grown, and then an oxide film 10 is grown.
1 and a nitride film 201, which is an oxidation-resistant film, are sequentially formed and patterned into a predetermined shape. Using this as a mask, the n - type epitaxial layer 3 is etched to a predetermined depth, and then etched by ion implantation. A p-type ion implantation layer 4 for a channel cut prevention layer is formed, and selective oxidation is performed using the nitride film 201 as a mask to form an isolation oxide film 102 (FIG. 1a).
Next, after removing the nitride film 201 and the oxide film 101, a thin oxide film 103 is formed again, and this is passed through a required resist mask (the resist mask at this stage is not shown). After implanting boron ions to selectively form the p - type layer 6 on the n - type epitaxial layer 3, a resist mask 301 with the desired pattern is formed again, and this is used to implant boron ions through the oxide film 103. by implanting p + into the n - type epitaxial layer 3.
Form layers 7, 8, 9 (FIG. 1b). Next, after removing the resist mask 301, a phosphor glass film 401 is grown on the entire upper surface by CVD method, and then
This phosphorus glass film 401, the p - type layer 6 and the p + type layers 7, 8, and 9 are annealed simultaneously.
A p - type layer 6a and p + type layers 7a, 8a, 9a are formed [FIG. 1c]. Next, a window is formed in the phosphor glass film 401 and the oxide film 103 in a part above the p - type layer 6a, and an n type impurity is introduced therethrough, and annealing is performed to form an n + type layer 10a. At the same time, the p - type layer 6a becomes the p - type layer 6b, and the p + type layer 7
A, 8a, and 9a are grown into 7b, 8b, and 9b, respectively [Figure 1 d]. Next, windows are opened on each of the p + type layers 7b and 9b, and the above n + type layer 1 is opened.
Electrode wiring is carried out through the metal silicide layer 501 along with the upper window part of 0a, and an injector electrode 11 is connected to the p + type layer 7b which is the emitter of the pnp transistor, and an injector electrode 11 is connected to the p + type layer 7b which is the collector of the pnp transistor and which operates in the reverse direction. For taking out the electrode connected to the p - type layer 6b which is the base of the transistor
An input electrode 12 is provided on the p + type layer 9b, and further,
n + , which is the collector of a reverse-operating npn transistor
Output electrodes 13 are connected to the shaped layer 10a to complete this IIL gate [first
Figure e]. The above shows a basic 1-output IIL gate, but
Figure 2 is a plan view of this conventional IIL gate with three outputs and two inter-gate wirings.
14 and 15 are the first collector C 1 and the second collector C 1 , respectively.
The three output electrodes 21 and 22 connected to the collector C 2 and the third collector C 3 are inter-gate wirings. The three collectors C 1 , C 2 , and C 3 are arranged in the order of distance from the input (base) electrode 12 . Now, as shown in FIG. 3, the current amplification factor βu of the reverse operation npn transistor decreases more greatly in the high current range of the collector current I c as the collector is farther away from the base electrode 12. This is thought to be because the base resistance increases as the collector is farther away from the base electrode. Further, it is known that there is a power delay characteristic as shown in FIG. 4 between the gate propagation delay time t pd of IIL and the power consumption P d . (For example, Semiconductor Transistor Research Group. IEICE Technical Report SSD76
~89 p37: High Speed IIL with Self−
Aligned Double Diffusion Injector〔S 2 L〕). Here, if the base area is the same and the pnp transistor characteristics are the same, the relationship t pdnio ∝βu 1/2 holds true as shown in Figure 5. Therefore, as shown in Figure 6, the farther the collector is from the base electrode (the collector The larger the distance D CB from the base electrode) the minimum delay time
t pdnio becomes larger. Therefore, in the performance of IIL gates manufactured using conventional manufacturing methods, there are differences in characteristics between each output electrode, as shown in Table 1. be restricted. Furthermore, even if the manufacturing method is the same, the current amplification factor βu is proportional to the ratio S C /S B of the collector area S C to the base area S B , as shown in FIG. In the conventional structure, as shown in FIG. 2, there is a p - type region 6b and a p +
A base region consisting of shaped regions 8b and 9b exists under the inter-gate wirings 21 and 22, and as shown in Table 1, the base area S B is large, and therefore the ratio S to the collector area S C is large. C /S B becomes very small, the current amplification factor βu becomes small, the minimum delay time t pdnio becomes large even in the collector C 1 closest to the base electrode, and the power supply current I ioj is reduced to 200 μA/gate.
The delay speed t pd also increases.
この発明は以上のような欠点を除去することを
目的とし、半導体集積回路装置、特にIIL・ICに
おいて、各コレクタに対応する各ベース領域を、
各コレクタ電極配線及び論理ゲート回路配線に対
して直角な方向に配線された、金属シリサイド膜
を重ねたポリシリコン膜で構成された低抵抗導体
を介して定電流回路素子へ接続し、各インジエク
タも同様の低抵抗導体を介して接続することによ
つて、複数個のコレクタ相互の特性差異をなくし
て優れた特性の論理ICを実現でき、しかもイン
ジエクタ−コレクタ−ベース配置を実現して動作
速度を速くすることができるものである。
また半導体集積回路装置の製造方法、特に
IIL・ICの製造方法において、そのベース電極を
セルフアライン的に形成することにより、ベー
ス・コレクタ間距離を小さくでき、素子の小型化
を実現できるものである。
〔発明の実施例〕
第１１図ａ〜ｅはこの発明の一実施例の構造を
よく理解するためにその製造工程の主要段階にお
ける状態を示す断面図で、第１図ａ〜ｅと同等部
分は同一符号で示す。この実施例においても、従
来例における第１図ａおよびｂまでの工程は全く
同様に処理する。その後、レジストマスク３０１
を除去して、酸化膜１０３の上に窒化膜２０２を
デポジシヨンして、横形pnpトランジスタのベー
ス領域となる領域上以外の窒化膜２０２、酸化膜
１０３を除去したのちに、全上面にポリシリコン
膜６０１をデポジシヨンする〔第１１図ａ〕。次
に、ポリシリコン膜６０１の上に窒化膜２０３を
デポジシヨンして、この窒化膜２０３に所要のパ
ターニングを施し、この窒化膜２０３をマスクと
して選択酸化を行ない、マスクされなかつた部分
のポリシリコン膜６０１を酸化膜１０４に変化さ
せ、コレクタ層を形成すべきp-形層６ａの上に
ポリシリコン膜６１１を、インジエクタ側（図の
左側）の分離酸化膜１０２の上にポリシリコン膜
６２１を、ベース側（図の右側）の分離酸化膜１
０２の上にポリシリコン膜６３１を残す〔第１１
図ｂ〕。次に、この酸化膜１０４をマスクとして
ヒ素イオンを注入してコレクタ層となるべきn+
形層１０をp-形層６ａの表面部の一部に形成し
た後に酸化膜１０４を全面除去し、低温酸化を施
して、基体表面に薄い酸化膜１０５を、ポリシリ
コン膜６１１，６２１，６３１の各側面に酸化膜
１０６を形成する〔第１１図ｃ〕。ここで、周知
のように、高濃度に不純物を拡散させたシリコン
膜およびポリシリコン膜は増速酸化され通常基板
より酸化膜は厚くなり、さらにその効果は低温酸
化ほど顕著である。次に、基体上の薄い酸化膜１
０５のみを除去する。このとき異方性エツチング
が可能なリアクテイブエツチング法を使用すれ
ば、ポリシリコン膜６１１，６２１，６３１の側
面の酸化膜１０６を残して基体上の酸化膜１０５
のみを容易にエツチング除去できる。さらに、窒
化膜２０３を熱リン酸等で全面除去してポリシリ
コン６１１，６２１，６３１の頂面を露出させ
る。このとき、窒化膜２０２も除去されるが、横
形pnpトランジスタのベース領域は酸化膜１０３
で保護されている。その後に全上面にPt，Pd，
Ｗ，Moなどのシリサイド金属膜（図示せず）を
形成し、シンタリングを行ない、金属シリサイド
膜５０１，５１１をそれぞれシリコンおよびポリ
シリコンの表面のみに形成し、つづいて、例えば
王水によつて金属膜を除去する〔第１１図ｄ〕。
つづいて、その上にパツシベーシヨン膜４０１
（例えばリンガラス膜）をデポジシヨンした後、
所要のレジストマスク（図示せず）を用いてコン
タクトの窓明けを行ない、その後にレジストマス
クを除去して、Al，Auなどの低抵抗金属で従来
と同様に接続用配線１１，１２，１３を形成し
て、この実施例は完成する。第１２図はこの実施
例の平面パターン図で、ベース電極１２は金属シ
リサイド膜５０１によつて基板に接続され、金属
シリサイド膜５１１で低抵抗化されたポリシリコ
ン膜６３１に配線されており、インジエクタ電極
１１は同様に金属シリサイド膜５０１によつて基
板に接続され、金属シリサイド膜５１１で低抵抗
化されたポリ膜６２１に配線されている。また、
コレクタ層１０もポリシリコン膜６１１によつて
コレクタ電極１３に接続される。
さて、この実施例の第１の利点は、コレクタ
（アウトプツト）電極１３とベース（インプツト）
電極１２との距離DC-Bが酸化膜１０６のセルフ
アラインで決まる数千Åと非常に小さくできるこ
とである。すなわち、従来装置ではAl配線の幅
が当該電極のコンタクト部の幅よりもはみ出して
いるので、上記距離DC-Bは配線幅で制約を受け
て小さくできなかつた。この実施例では金属シリ
サイド膜５０１を利用してベース電極配線を形成
しており、かつセルフアライン的に金属シリサイ
ド膜を形成しているので、従来装置におけるよう
な制約はなくなり、第１１図ｅにＡで示した部位
で、金属シリサイド膜５０１の端部は直接酸化膜
１０６の端部と接しており、この酸化膜１０６の
膜厚が実質的に上記DC-Bとなるので、その値を
小さくできる。なお、この第１１図ｅの段階のこ
の実施例の平面図を第１２図に示す。
第１３図はこの発明の構造になる出力３個を有
するIILゲートの一例を示す平面図である。図か
ら判るように、npnトランジスタの各コレクタに
ついて、ベース電極１２を金属シリサイド膜で低
抵抗化されたポリシリコン膜６３１で、電流源で
あるpnpトランジスタのコレクタに連結されてお
り、各インジエクタも同様にポリシリコン膜６２
１上のシリサイド膜で電極１１に接続されてい
て、各コレクタ間に電気的差異はなくなり、第２
表に示すように特性も同一となる。更に、ベース
電極配線が非活性領域上のポリシリコン膜６３１
とその上の金属シリサイド膜とによつているの
で、従来構造では必須であつたゲート間配線２
１，２２の直下のベース拡散層６ａ，８ａ，９ａ
が不用となり、ベース面積SB自体が小さくなりコ
レクタ面積SCとの比SC／SBが大きく、従つて電流
増幅率βuも大きくなる。また、第１０図で説明
したインジエクタ−コレクタ−ベース配置にでき
るので、ゲート動作速度を速くできる。
The purpose of this invention is to eliminate the above drawbacks, and in semiconductor integrated circuit devices, especially IIL/IC, each base region corresponding to each collector is
Each injector is connected to the constant current circuit element through a low resistance conductor made of a polysilicon film overlaid with a metal silicide film, which is wired in a direction perpendicular to each collector electrode wire and logic gate circuit wire. By connecting them through similar low-resistance conductors, it is possible to eliminate the characteristic differences between multiple collectors and realize a logic IC with excellent characteristics.Moreover, it is possible to realize an injector-collector-base arrangement and increase operating speed. It can be done quickly. Also, methods for manufacturing semiconductor integrated circuit devices, especially
In the IIL IC manufacturing method, by forming the base electrode in a self-aligned manner, the base-collector distance can be reduced and the device can be made smaller. [Embodiment of the Invention] Figures 11a to 11e are cross-sectional views showing the main stages of the manufacturing process in order to better understand the structure of an embodiment of the present invention, and show the same parts as Figures 1a to 1e. are indicated by the same symbol. In this embodiment as well, the steps up to a and b in FIG. 1 in the conventional example are processed in exactly the same way. After that, the resist mask 301
is removed, a nitride film 202 is deposited on the oxide film 103, and after removing the nitride film 202 and the oxide film 103 except on the region that will become the base region of the lateral pnp transistor, a polysilicon film is deposited on the entire upper surface. 601 (FIG. 11a). Next, a nitride film 203 is deposited on the polysilicon film 601, this nitride film 203 is patterned as required, selective oxidation is performed using this nitride film 203 as a mask, and the unmasked portions of the polysilicon film are 601 to an oxide film 104, a polysilicon film 611 is placed on the p - type layer 6a where the collector layer is to be formed, a polysilicon film 621 is placed on the isolation oxide film 102 on the injector side (left side in the figure), Isolation oxide film 1 on the base side (right side of the figure)
Leaving the polysilicon film 631 on 02 [11th]
Figure b]. Next, using this oxide film 104 as a mask, arsenic ions are implanted to form the n +
After the shaped layer 10 is formed on a part of the surface of the p - type layer 6a, the oxide film 104 is completely removed and low-temperature oxidation is performed to form a thin oxide film 105 on the surface of the substrate and polysilicon films 611, 621, 631. An oxide film 106 is formed on each side surface (FIG. 11c). Here, as is well known, silicon films and polysilicon films in which impurities are diffused at a high concentration are oxidized at an accelerated rate, making the oxide film thicker than that of a normal substrate, and this effect is more pronounced as the temperature of oxidation becomes lower. Next, a thin oxide film 1 on the substrate
Remove only 05. At this time, if a reactive etching method capable of anisotropic etching is used, the oxide film 106 on the side surfaces of the polysilicon films 611, 621, 631 is left and the oxide film 105 on the substrate is etched.
can be easily removed by etching. Further, the entire surface of the nitride film 203 is removed using hot phosphoric acid or the like to expose the top surfaces of the polysilicon 611, 621, and 631. At this time, the nitride film 202 is also removed, but the base region of the lateral pnp transistor is covered with the oxide film 103.
protected. After that, Pt, Pd,
A silicide metal film (not shown) such as W or Mo is formed and sintered to form metal silicide films 501 and 511 only on the surfaces of silicon and polysilicon, respectively. The metal film is removed [FIG. 11d].
Next, a passivation film 401 is placed on top of it.
After depositing (e.g. phosphorus glass film),
A contact window is opened using a required resist mask (not shown), and then the resist mask is removed and the connection wirings 11, 12, 13 are formed using a low resistance metal such as Al or Au in the same manner as before. This embodiment is then completed. FIG. 12 is a planar pattern diagram of this embodiment, in which the base electrode 12 is connected to the substrate through a metal silicide film 501, wired to a polysilicon film 631 whose resistance has been reduced by a metal silicide film 511, and an injector. The electrode 11 is similarly connected to the substrate through a metal silicide film 501 and wired to a poly film 621 whose resistance is lowered by the metal silicide film 511. Also,
Collector layer 10 is also connected to collector electrode 13 through polysilicon film 611. Now, the first advantage of this embodiment is that the collector (output) electrode 13 and the base (input)
The distance D CB from the electrode 12 can be made very small, several thousand Å, which is determined by the self-alignment of the oxide film 106 . That is, in the conventional device, since the width of the Al wiring protrudes beyond the width of the contact portion of the electrode, the distance D CB cannot be reduced due to the restriction of the wiring width. In this embodiment, the metal silicide film 501 is used to form the base electrode wiring, and since the metal silicide film is formed in a self-aligned manner, there are no restrictions as in the conventional device, and as shown in FIG. At the part indicated by A, the end of the metal silicide film 501 is in direct contact with the end of the oxide film 106, and the thickness of this oxide film 106 is substantially equal to the above D CB , so the value can be reduced. . Incidentally, a plan view of this embodiment at the stage of FIG. 11e is shown in FIG. 12. FIG. 13 is a plan view showing an example of an IIL gate having three outputs having the structure of the present invention. As can be seen from the figure, for each collector of the npn transistor, the base electrode 12 is connected to the collector of the pnp transistor, which is a current source, by a polysilicon film 631 whose resistance has been lowered by a metal silicide film, and the same applies to each injector. polysilicon film 62
It is connected to the electrode 11 by the silicide film on the collector 1, and there is no electrical difference between the collectors, and the
As shown in the table, the characteristics are also the same. Furthermore, the base electrode wiring is connected to the polysilicon film 631 on the non-active region.
and the metal silicide film on it, so the inter-gate wiring 2, which was essential in the conventional structure,
Base diffusion layers 6a, 8a, 9a directly under 1, 22
is no longer needed, the base area S B itself becomes smaller, the ratio S C /S B to the collector area S C becomes larger, and the current amplification factor βu also becomes larger. Further, since the injector-collector-base arrangement described in FIG. 10 can be used, the gate operation speed can be increased.
以上のように、この発明によれば半導体集積回
路装置、特にIIL・ICにおいて、各コレクタに対
応する各ベース領域を、各コレクタ電極配線及び
論理ゲート回路配線に対して直角な方向に配線さ
れた、金属シリサイド膜を重ねたポリシリコン膜
で構成された低抵抗導体を介して定電流回路素子
へ接続し、各インジエクタも同様の低抵抗導体を
介して接続する構成としたから、複数個のコレク
タ相互の特性差異がなくなり優れた特性の論理
ICを実現でき、しかもインジエクタ−コレクタ
−ベース配置が実現でき動作速度を速くすること
ができるという効果を有する。
また半導体集積回路装置の製造方法、特に
IIL・ICの製造方法において、そのベース電極を
セルフアライン的に形成するようにしたから、ベ
ース・コレクタ間距離を小さくでき、素子の小型
化を実現できるという効果を有する。
As described above, according to the present invention, in a semiconductor integrated circuit device, particularly an IIL/IC, each base region corresponding to each collector is wired in a direction perpendicular to each collector electrode wiring and logic gate circuit wiring. , it is connected to the constant current circuit element through a low resistance conductor made of a polysilicon film overlaid with a metal silicide film, and each injector is also connected through the same low resistance conductor, so multiple collectors The logic of excellent characteristics that eliminates mutual characteristic differences
It has the effect that an IC can be realized, an injector-collector-base arrangement can be realized, and the operating speed can be increased. Also, methods for manufacturing semiconductor integrated circuit devices, especially
In the IIL IC manufacturing method, since the base electrode is formed in a self-aligned manner, the base-collector distance can be reduced, and the device can be miniaturized.
第１図は従来のIIL−ICの製造主要工程におけ
る状態を示す断面図、第２図は３つのコレクタを
有する従来のIIL−ICの平面図、第３図および第
４図は３つのコレクタC1，C2，C3を有する従来
のIILゲートのコレクタ電流ICと電流増幅率βuと
の関係および消費電力Pdとゲート伝播遅延時間
tpdとの関係をそれぞれ示す図、第５図は電流増
幅率βuと最小遅延時間tpdnioとの関係を示す図、
第６図はコレクタとベース電極との距離DC-Bと
最小遅延時間tpdとの関係を示す図、第７図はコ
レクタ−ベース面積比SC／SBと電流増幅率βuと
の関係を示す図、第８図は各端子の関係位置によ
つて最小遅延時間tpdnioが異なることを示す図、
第９図はインジエクタ−ベース−コレクタの配置
の場合の構成とその動作を説明するための模式断
面図、第１０図はインジエクタ−コレクタ−ベー
ス配置の場合の構成とその動作を説明するための
模式断面図、第１１図はこの発明の一実施例を製
造する主要段階における状態を示す断面図、第１
２図はこの実施例の平面図、第１３図はこの発明
を適用した３出力のIILの一例を示す平面図であ
る。
図において、１は半導体基体、６ａはベース
層、７ａはインジエクタ層、８ａ，９ａはベース
取出し層、１０はコレクタ層、１１はインジエク
タ電極配線、１２はベース電極配線、１３，１
４，１５はコレクタ電極配線、１０１，１０３，
１０４，１０５，１０６は酸化膜、１０２は分離
領域、２０１，２０２，２０３は窒化膜、４０１
はパツシベーシヨン膜、５０１，５１１は金属シ
リサイド膜、６０１，６１１，６２１，６３１は
ポリシリコン膜である。なお、図中同一符号は同
一または相当部分を示す。
Figure 1 is a cross-sectional view showing the main manufacturing process of a conventional IIL-IC, Figure 2 is a plan view of a conventional IIL-IC with three collectors, and Figures 3 and 4 are three collectors C. Relationship between collector current I C and current amplification factor βu, power consumption Pd, and gate propagation delay time of a conventional IIL gate with 1 , C 2 , and C 3
Figure 5 is a diagram showing the relationship between current amplification factor βu and minimum delay time t pdnio .
Figure 6 shows the relationship between the distance D CB between the collector and base electrodes and the minimum delay time t pd , and Figure 7 shows the relationship between the collector-base area ratio S C /S B and the current amplification factor βu. Figure 8 is a diagram showing that the minimum delay time tpdnio differs depending on the relative position of each terminal,
Fig. 9 is a schematic sectional view for explaining the configuration and its operation in the case of an injector-base-collector arrangement, and Fig. 10 is a schematic cross-sectional view for explaining the configuration and its operation in the case of the injector-collector-base arrangement. 11 is a sectional view showing the state at the main stage of manufacturing an embodiment of the present invention,
FIG. 2 is a plan view of this embodiment, and FIG. 13 is a plan view showing an example of a three-output IIL to which the present invention is applied. In the figure, 1 is a semiconductor substrate, 6a is a base layer, 7a is an injector layer, 8a and 9a are base extraction layers, 10 is a collector layer, 11 is an injector electrode wiring, 12 is a base electrode wiring, 13, 1
4, 15 are collector electrode wiring, 101, 103,
104, 105, 106 are oxide films, 102 is an isolation region, 201, 202, 203 are nitride films, 401
is a passivation film, 501 and 511 are metal silicide films, and 601, 611, 621, and 631 are polysilicon films. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
する第１のトランジスタと、この第１のトランジ
スタの上記ベースへ定電流を供給する第２のトラ
ンジスタとからなる論理ゲート回路装置を有する
半導体集積回路装置の製造方法において、 (1) 半導体基板表面に第１のトランジスタのベー
ス層と第２のトランジスタのインジエクタ領域
を形成するステツプと、 (2) 上記半導体基体表面に酸化膜と窒化膜を選択
的に形成するステツプと、 (3) 全上面にポリシリコン膜、窒化膜をデポジシ
ヨンするステツプと、 (4) 上記窒化膜をパターニング後この窒化膜をマ
スクとして選択酸化し、上記第１のトランジス
タのコレクタ領域および分離酸化膜上に、第１
のトランジスタのベースおよび第２のトランジ
スタのインジエクタ電極取り出し配線領域に、
ポリシリコンを残すとともに、マスクされなか
つた部分を酸化膜とするステツプと、 (5) 上記酸化膜をマスクとして上記ポリシリコン
に不純物を導入拡散し、コレクタ層を形成する
ステツプと、 (6) 上記酸化膜を除去後、低温酸化を行い上記ポ
リシリコン膜側壁に厚い酸化膜を形成するステ
ツプと、 (7) 上記ステツプで生じた薄い酸化膜を除去した
後上記窒化膜を除去するステツプと、 (8) 上記半導体基体の表面およびポリシリコン膜
の表面に金属シリサイドをセルフアラインにて
形成するステツプと、 (9) 全面にパツシベーシヨン膜を形成後コンタク
トを設け、第１のトランジスタのベース電極取
り出し領域と、第２トランジスタのインジエク
タ電極取り出し領域を、コレクタ電極配線およ
び論理ゲート配線に対して直角な方向に配設さ
れた金属シリサイド膜を重ねたポリシリコン膜
よりなる低抵抗導体配線を形成するステツプ とを含むことを特徴とする半導体集積回路装置の
製造方法。[Claims] 1. A logic gate circuit device comprising a first transistor whose base is an input terminal and whose collector is an output terminal, and a second transistor which supplies a constant current to the base of the first transistor. A method of manufacturing a semiconductor integrated circuit device comprising: (1) forming a base layer of a first transistor and an injector region of a second transistor on a surface of a semiconductor substrate; (2) forming an oxide film and a nitride film on a surface of the semiconductor substrate; (3) Depositing a polysilicon film and a nitride film on the entire upper surface; (4) After patterning the nitride film, selectively oxidizing the nitride film using the nitride film as a mask; A first layer is formed on the collector region of the transistor and on the isolation oxide film.
In the base of the transistor and the injector electrode lead-out wiring area of the second transistor,
(5) using the oxide film as a mask, introducing and diffusing impurities into the polysilicon to form a collector layer; (6) forming a collector layer using the oxide film as a mask; After removing the oxide film, low-temperature oxidation is performed to form a thick oxide film on the side walls of the polysilicon film; (7) after removing the thin oxide film generated in the step, the nitride film is removed; 8) forming metal silicide on the surface of the semiconductor substrate and the surface of the polysilicon film by self-alignment; (9) forming a passivation film on the entire surface and then providing a contact to form a base electrode extraction region of the first transistor; , a step of forming a low resistance conductor wiring made of a polysilicon film overlapping a metal silicide film disposed in a direction perpendicular to the collector electrode wiring and the logic gate wiring in the injector electrode extraction region of the second transistor; A method of manufacturing a semiconductor integrated circuit device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57189545A JPS5978560A (en) | 1982-10-26 | 1982-10-26 | Semiconductor integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57189545A JPS5978560A (en) | 1982-10-26 | 1982-10-26 | Semiconductor integrated circuit device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5978560A JPS5978560A (en) | 1984-05-07 |
| JPH0473300B2 true JPH0473300B2 (en) | 1992-11-20 |
Family
ID=16243101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57189545A Granted JPS5978560A (en) | 1982-10-26 | 1982-10-26 | Semiconductor integrated circuit device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5978560A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5466784A (en) * | 1977-11-08 | 1979-05-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS55125651A (en) * | 1979-03-22 | 1980-09-27 | Nec Corp | Production of semiconductor integrated circuit |
| JPS568846A (en) * | 1979-07-03 | 1981-01-29 | Nec Corp | Semiconductor integrated circuit |
-
1982
- 1982-10-26 JP JP57189545A patent/JPS5978560A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5466784A (en) * | 1977-11-08 | 1979-05-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS55125651A (en) * | 1979-03-22 | 1980-09-27 | Nec Corp | Production of semiconductor integrated circuit |
| JPS568846A (en) * | 1979-07-03 | 1981-01-29 | Nec Corp | Semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5978560A (en) | 1984-05-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5017503A (en) | Process for making a bipolar transistor including selective oxidation | |
| US5065208A (en) | Integrated bipolar and CMOS transistor with titanium nitride interconnections | |
| KR100196085B1 (en) | High preformance semiconductor devices and their manufacture | |
| US4735912A (en) | Process of fabricating a semiconductor IC device | |
| JPH0654795B2 (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
| US4803174A (en) | Bipolar transistor integrated circuit and method of manufacturing the same | |
| JPH0241170B2 (en) | ||
| US6596600B1 (en) | Integrated injection logic semiconductor device and method of fabricating the same | |
| US5063168A (en) | Process for making bipolar transistor with polysilicon stringer base contact | |
| EP0193934A2 (en) | Semiconductor integreated circuit device and method of manufacturing the same | |
| JPS60202965A (en) | Method of producing improved oxide defined transistor and structure obtained as its result | |
| JPH04102335A (en) | Manufacturing process of bipolar transistor having self-alignment contact | |
| JPS63261746A (en) | Manufacture of bipolar type semiconductor integrated circuit device | |
| JPH0645537A (en) | Manufacture of integrated circuit | |
| JPS60163452A (en) | Integrated circuit with bipolar device and field effect device and method of producing same | |
| US4974046A (en) | Bipolar transistor with polysilicon stringer base contact | |
| US5280188A (en) | Method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and a plurality of MOS transistors | |
| JPH0473300B2 (en) | ||
| JPS6248388B2 (en) | ||
| EP0251927B1 (en) | Bipolar transistor with polysilicon stringer base contact | |
| JP3207883B2 (en) | Manufacturing method of bipolar semiconductor device | |
| JPH07130898A (en) | Semiconductor device and manufacture thereof | |
| JPH0136710B2 (en) | ||
| JPS63284854A (en) | Semiconductor device and its manufacture | |
| JP2697631B2 (en) | Method for manufacturing semiconductor device |