JPS568846A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attempt a sharp reduction of wiring resistance in an element and between elements of a semiconductor integrated circuit by a method wherein a metallic silicified material layers is prepared on electrodes of element, on the surface of polycrystalline Si layers constituting inter-element wirings and on the surface of regions of wiring in the element. CONSTITUTION:P<+>-type layers 32 and filed oxide films 33 constituting channel stoppers are formed on a P-type Si substrate 31. Gate insulating films 34 and polycrystalline Si layers 36 to form gate electrodes or inter-element wirings are prepared in element regions, and N-type impurity layers 37 to form source electrodes or drain electrodes are prepared on the surface of substrate to form element regions neighboring to this polycrystalline Si layers 36. Then N-type impurity diffusion layers 38 to serve as wiring in the element are prepared being connected to the layers 37, and the surface of polycrystalline Si layers 36 and the diffusion layers 38 are covered with low resistance metallic silicified material layers 39. As the layer resistance of layers 39 are smaller at least one digit compared with the layer resistance of Si layers 36 and layers 38, the resistance values in the elements and the inter-element wirings can be sharply reduced.