JPS54107270A - Semiconductor device and its production - Google Patents

Semiconductor device and its production

Info

Publication number
JPS54107270A
JPS54107270A JP1423278A JP1423278A JPS54107270A JP S54107270 A JPS54107270 A JP S54107270A JP 1423278 A JP1423278 A JP 1423278A JP 1423278 A JP1423278 A JP 1423278A JP S54107270 A JPS54107270 A JP S54107270A
Authority
JP
Japan
Prior art keywords
type
layer
production
semiconductor device
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1423278A
Other languages
Japanese (ja)
Other versions
JPS6238869B2 (en
Inventor
Hideto Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1423278A priority Critical patent/JPS54107270A/en
Publication of JPS54107270A publication Critical patent/JPS54107270A/en
Publication of JPS6238869B2 publication Critical patent/JPS6238869B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To obtain a semiconductor element which has a good characteristic with a small leak current and is integrated at a high density, for example, a N channel- type Si gate MOSFET with the good rate of indefectible elements. CONSTITUTION:Oxide Si layer 202, gate insulating layer 203, gate electrode 204 and wiring layer 205 are formed on the surface of p-type Si substance 201. Next, arsenic is ion-injected to form source and drain diffusion layers 206 and 207. Next, windows 208 and 209 are formed, and phosphorus is diffused in a high temperature, thereby forming N-type diffusion regions 210 and 211.
JP1423278A 1978-02-10 1978-02-10 Semiconductor device and its production Granted JPS54107270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1423278A JPS54107270A (en) 1978-02-10 1978-02-10 Semiconductor device and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1423278A JPS54107270A (en) 1978-02-10 1978-02-10 Semiconductor device and its production

Publications (2)

Publication Number Publication Date
JPS54107270A true JPS54107270A (en) 1979-08-22
JPS6238869B2 JPS6238869B2 (en) 1987-08-20

Family

ID=11855317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1423278A Granted JPS54107270A (en) 1978-02-10 1978-02-10 Semiconductor device and its production

Country Status (1)

Country Link
JP (1) JPS54107270A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63149877U (en) * 1987-03-20 1988-10-03

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50106588A (en) * 1974-01-29 1975-08-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50106588A (en) * 1974-01-29 1975-08-22

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5793114A (en) * 1993-12-17 1998-08-11 Sgs-Thomson Microelectronics, Inc. Self-aligned method for forming contact with zero offset to gate
US6107194A (en) * 1993-12-17 2000-08-22 Stmicroelectronics, Inc. Method of fabricating an integrated circuit
US6284584B1 (en) 1993-12-17 2001-09-04 Stmicroelectronics, Inc. Method of masking for periphery salicidation of active regions

Also Published As

Publication number Publication date
JPS6238869B2 (en) 1987-08-20

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