JPS5989458A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce base resistance by bringing an emitter layer and a base electrode extracting section close in a self-alignment manner and forming a double base structure. CONSTITUTION:An n<+> type layer 2 as a collector buried layer is formed to a p<-> type silicon substrate 1, and an n<-> type epitaxial layer 3 is grown on the layer 2. An isolation oxide film 102 is formed, a p type layer 4 for a channel cut is formed, and a base region 6 is formed. A nitride film 202 is formed on an oxide film 103 as a protective film. An n type impurity is diffused from polysilicon films 611, 612 to form an emitter layer 7 and a collector drawing layer 8, and an oxide film 104 is removed. Oxide films are formed to the side surfaces of the base layer 6 and the film 611, 612. The oxide film of the layer 6 is removed, and metallic silicide films 501, 511, 512 are formed to the surfaces of the exposed base layer 6 and films 611, 612.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device. This invention relates to improvements in forming methods.

[Prior art]

In general, transistors in B-P and C are formed in electrically independent islands by pn junction isolation, oxide film isolation using selective acid technology, triple diffusion, or the like. Here, a method for forming an npn transistor using an oxide film separation method will be described. Of course, when using the above-mentioned various separation methods other than this, further pnl)
) It can also be applied to transistors.

FIGS. 1(a) to 1(,) are cross-sectional views showing the main process steps of a conventional manufacturing method. The conventional method will be briefly explained below with reference to this figure. P-type (p
After selectively forming a highly impurity-concentrated n-type (n-type) layer (2) that will become the collector buried layer on the silicon substrate (11), an n-type epitaxial layer (3) is grown on top of it. [Figure 1 (a)]] The underlying oxide film (101) is applied to the film.
A thick isolation oxide film (102) is formed by performing selective oxidation using the nitride film (201) formed above as a mask. At this time, a p-type layer for channel cut is formed below this isolation oxide film (102). (4) is formed at the same time [Fig. 1(b)
]. Next, the crab film (201) used as a mask for the selective oxidation described above is removed together with the underlying oxide film (101), an oxide film (103) for ion implantation protection is formed again, and a photoresist film (this Using the photoresist film (not shown) as a mask, the p-type layer (not shown) is used as a mask.
5), the above photoresist film is removed, a new photoresist film (SOl) is formed, and using this as a mask, a p-type layer (6) which will become an active base layer is formed by ion implantation [Fig. C)]. Subsequently, the photoresist film (301) is removed and a passivation film (401) generally made of phosphosilicate glass (PSG) is removed.
tt is deposited and a heat treatment is performed that combines the annealing of the base ion-implanted layers (5) and (6) and the baking of the PS () film (401) to form the intermediate external base layer (51) and the active base. After forming the layer (61), the PSG film (401)
Necessary openings (70) and (80) are formed in the ion implantation method to form an n-type layer (7) to become an emitter layer and an n-type layer (8) to become a collector electrode extraction layer. Figure 1 (d)]. After that, each ion implantation layer is annealed to complete the external base layer (52) and the active base layer (62), as well as to form the emitter layer (71) and the collector electrode extraction layer (81).
An opening (50) for taking out the base electrode is formed, and each opening (50) (70) and (80) is made of metal silicide [platinum silicide (PT-ken), palladium silicide ( pa-st) etc.] membrane (5
01) and then base electrode wiring +91. Emitter electrode wiring (10) and collector electrode wiring (forming a river).

FIG. 2 is a plan pattern diagram of a transistor manufactured by this conventional method. By the way, the frequency characteristics of a transistor depend on the pace collector capacitance, base resistance, etc., and it is necessary to reduce these in order to improve the frequency characteristics. In the above structure, a p-type external base layer (52) was provided to reduce the pace resistance;
This has the disadvantage of increasing the collector capacity. Furthermore, the base resistance is determined by the emitter layer (71) and the base electrode opening (50).
), and in the conventional one, the distance between the base electrode wiring (9) and the emitter electrode wiring (10) and the distance between each electrode wiring +91 and each opening (50) of the Dot + (70
), and even if the precision of photoetching is improved and the spacing between the electrode wirings is reduced, the above-mentioned protrusion will inevitably remain.

[Summary of the invention]

This invention has been made in view of the above points, and provides a method for manufacturing a transistor with a double paste structure in which the emitter layer and the base electrode lead-out portion are close to each other in a self-aligned manner, and the paste resistance is small. This is what we provide.

[Embodiments of the invention]

FIGS. 3(a) to 3(f) are cross-sectional views showing the main process steps of an embodiment of the semiconductor device manufacturing method according to the present invention. In the same figure, (601), (611)
.

(612) is a polysilicon film, (202>, (203
) C nitride film, (104), (10 is an oxide film formed by oxidizing a polysilicon film, (105) is an oxide film formed by low-temperature oxidation of a substrate, (501), (511)
, (512) is a metal silicate film.

Next, the manufacturing process of the semiconductor device with the above configuration will be explained. First, as shown in FIG. 3(a), after selectively forming an n-type layer (2) to serve as a collector buried layer on a p-type silicon substrate (1) in the same manner as in the conventional method, An n-type epitaxial layer (3) is grown, and an isolation oxide film (3) is grown.
102) and at the same time form a p-type layer (
4) and further form a base region (6) by ion implantation, the oxide film (6) used as a protective film at this time is removed.
A nitride film (202) is formed on the collector layer (3) and the base layer (6), leaving only this part and the rest so that the exposed part to the substrate surface of the junction between the collector layer (3) and the base layer (6) is protected. After removing by etching, a polysilicon film (601) is deposited on the entire upper surface including the nitride film (202).

Next, as shown in FIG. 3(b), a polysilicon film (6
A nitride film (203) is deposited on 01), and the nitride film (203) is patterned so that a portion above the area where the emitter layer and the collector extraction layer are to be formed remains. Using as a mask, the polysilicon film (601) is selectively oxidized to form the polysilicon film (611) on the emitter layer formation region, leaving the polysilicon film (612) on the collector extraction layer formation region, and oxidizing the other regions. The polysilicon film (601) is made into an oxide film (104). At this time, the polysilicon film (
611) is a polysilicon film (611) on the collector lead layer formation region so as not to overlap the protective nitride film (202).
2) is formed to form a part of the nitride film (202).
Then, n-type ions are implanted from the top surface into the polysilicon films (611) and (612). Here, the ion implantation region is determined by the masking effect of the oxide film (104).
) is used as a mask during ion implantation, so a thickness of about 3000 A is sufficient.If the polysilicon film (601) is thick, it is better to thin it by etching it a little and then perform selective oxidation. It's efficient. Next, as shown in FIG. 3(C), the polysilicon film (61
1) After diffusing n-carving blunt from (612) to form an emitter layer (7) and a collector lead-out layer (8), the oxide film (104) is completely removed.

Next, as shown in FIG. 3(d), the upper surface is subjected to low-temperature oxidation to form oxide i (105) on the surface of the exposed base layer (6) and the side surfaces of the polysilicon layers (611) and (612). An oxide film (106) is formed thereon. As is well known at this time, in low-temperature oxidation, the oxide film (106) on the polysilicon is thick and the oxide film (105) on the silicon substrate is thin.

Next, as shown in FIG. 3(e), anisotropic etching such as reactive ion etching (R-E) is performed to remove the oxide film (1C+6) on the side surfaces of the polysilicon films (611) and (612). ) on the surface of the base layer (6), the nitride film (203) is completely removed using hot phosphoric acid, etc. (at this time, the nitride film '
(202) is also partially removed, but the collector-base junction is protected by the oxide film (103). ) The base layer (6) and polysilicon film (611) exposed in this way
and metal silicide film (501) on the surface of (612)
.

(511) and (512) are formed, respectively. Subsequently, as shown in FIG. 3(f), an unapassivation film (401) made of phosphosilicate glass is formed, holes are made at the required positions, and base electrode wiring (9j, emitter) made of aluminum is formed. Electrode arrangement @ (101 (Fig. 3 (f)
) not shown. ], and a collector electrode wiring circle is formed. FIG. 4 is a plan pattern diagram of the transistor thus obtained.

In the transistor thus obtained, the emitter layer (7) is a polysilicon film (61:L) on which a metal silicide film (511) is superimposed on the emitter electrode wiring (10).
Unlike the conventional example, the opening position for the base electrode wiring (9) in the cutting film (40, 1) is located near the polysilicon film (611). The base electrode wiring (9) is a metal silicide film (50
1) and is separated from the emitter region in a self-aligned manner by an oxide film (106). Further, the base metal silicide (501) surrounds the emitter region as shown in the figure, forming a so-called double base structure. In the conventional double base structure, the base electrode and aperture area are large, which has the disadvantage of increasing capacitance, but this invention does not require special electrodes or apertures, does not increase capacitance, and reduces base resistance. Can be lowered.

FIG. 5 is a plan pattern diagram showing another example of a transistor formed by the method of the present invention, in which an oxide film (103)
By passing under the polysilicon Q (611) part of the emitter region and leaving it on the boundary between the isolation oxide film (U02) and the silicon island, a so-called walled emitter structure can be prevented.

This walled-emitter structure refers to a structure in which the emitter-base junction is in contact with the isolation oxide film (102) as shown in Figure 4. In this walled-emitter structure, the junction is made by a collector-emitter pipe (C-Epipe). Although defects are likely to occur, this can be avoided with the structure shown in FIG.

It is of course possible to further reduce the emitter width by utilizing the side-etching effect caused by over-etching in the patterning of the nitride film during the formation of the selective oxidation mask described above. Also, more than npn
) Although the case of a transistor has been described, it goes without saying that the same can be done for a pnp transistor. Furthermore, for isolation between elements, the various isolation methods described above can be applied.

〔Effect of the invention〕

As explained above, according to the method of manufacturing a semiconductor device according to the present invention, the emitter layer is connected to the emitter electrode wiring through the metal silicide film on the polysilicon film used for diffusion formation of the emitter layer. The base electrode wiring is connected by a metal silicide film extending from the emitter layer to a position separated by the thickness of the oxide film formed by oxidizing the side surface of the polysilicon film above it, and is connected in a self-aligned manner. It has a double base structure that allows for extremely low penis resistance. Furthermore, since the emitter is diffused through the polysilicon film, it can be formed shallowly and accurately. Furthermore, since selective oxidation is used to leave this polysilicon film on the emitter layer formation region, the emitter width can be made narrower than in the past.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the state at the main mold stage for explaining a conventional manufacturing method of a semiconductor device, FIG. 2 is a plan view of a transistor obtained by the above-mentioned conventional manufacturing method, and FIG.
The figure is a cross-sectional view showing the main stages of the method according to an embodiment of the present invention, FIG. 4 is a plan view of an example of a transistor used in the method of this embodiment, and FIG. FIG. 7 is a plan view of another example. In the figure, (l) is a silicon substrate, (3) is a collector layer, (6) is a base layer, (71 is an emitter layer, (8j is a collector electrode 9 extraction layer, [9+, (to+,
(u) is a low resistance metal wiring, (yuos) is a silicon oxide film, (yu04), (105), (yuoa) is an oxide film,
(202) is a silicon film, (203) is a mask (]
(11) and (401) are passivation films, (50
1), (511), (512) are metal silicide films, (601). (611) and (612) are polysilicon films. Note that the same reference numerals in the figures indicate the same or equivalent parts.0 Agent: Shin Kuzuno - (1 other person) Figure 1 Figure 1 Figure 2 Figure 3 Figure 3 Commissioner of the Japan Patent Office 1. Display of incident Patent application No. 57-201292 2
, Title of the invention: Method for manufacturing semiconductor devices 3, Relationship with the case of the person making the amendment Patent applicant Representative: Hitoshi Katayama Department 4, Agent address: 2-2-3-5, Marunouchi 2-chome, Chiyoda-ku, Tokyo, Subject of amendment Column 6 of Claims and Detailed Description of the Invention of the Specification, Contents of Amendment (1) The claims of the Specification are corrected as shown in the attached appendix. (2) In the 5th line of page 11 of the specification, the words ``not necessary'' should be corrected to ``not necessary.'' 7. A document showing the scope of claims after the list of attached documents has been corrected. One or more copies of the claims. The first conductivity type region to be the collector layer and the second conductivity type region to be the base layer in a part of its surface area. a first step of sequentially forming a silicon oxide film and a silicon nitride film in a region including a junction between the first conductivity type region and the second conductivity type region on the surface of the silicon substrate on which the conductivity type region is formed; , forming a silicon film directly on the surface of the silicon substrate including on the silicon nitride film, and oxidizing the portion of the silicon film except on the portion where the emitter layer and the collector electrode extraction layer are to be formed by a selective oxidation method. In the second step, using the oxide film obtained in the second step as a mask, impurities of the first conductivity type are added at a high concentration to the silicon film on the portion where the emitter layer and the collector electrode extraction layer are to be formed. a third step of diffusing the impurity from the silicon film into the silicon substrate to form the emitter layer; a fourth step of removing the oxide film; A fifth step of performing low-temperature oxidation using the same mask again as a mask to form a thick oxide film on the side walls of the silicon film and a thin oxide film on the surface of the silicon substrate exposed in the fourth step; A seventh step of forming a metal silicide film on the upper surface of the silicon film exposed in the oxidation step and the surface of the silicon substrate is performed on the side wall of the silicon film, and after depositing a silicide film on the entire upper surface, the metal silicide film is deposited on the entire upper surface. A method for manufacturing a semiconductor device, comprising an eighth step of opening a required electrode window on the silicide film and forming a low-resistance metal wiring connected to the metal silicide film through the electrode window. 0 (2) A method for manufacturing a semiconductor device according to claim 1, characterized in that a polysilicon film is used as the silicon film.

Claims (1)

[Claims] fi+ The above first conductivity type on the surface of a silicon substrate in which a first conductivity type region to become a collector layer and a second conductivity type region to become a base layer are formed in a part of the surface portion thereof. A first step of sequentially forming a silicon oxide film and a silicon nitride film in a region including a junction between the region and the second conductivity type region, directly on the surface of the silicon substrate including the top of the silicon nitride film; A second step of forming a silicon film and oxidizing the silicon film by selective oxidation method except for the area where the emitter layer and the collector electrode layer are to be formed. A third step of diffusing impurities of the first conductivity type at a high concentration into the silicon film above the portions where the emitter layer and the collector electrode extraction layer are to be formed using the oxide film as a mask, from the silicon film to the silicon substrate; A fourth step of removing the oxide film after diffusing the impurities and forming the emitter layer, and performing low-temperature oxidation using the mask used for selective oxidation in the second step again as a mask to remove the silicon film. A fifth step of forming a thick oxide film on the side walls and a thin oxide film on the surface of the silicon substrate exposed in the fourth step, after removing the mask used in the fifth step, a sixth step of removing the thin oxide film on the surface of the silicon substrate while leaving an oxide film on the side walls of the silicon film; After the seventh step of forming a metal silicide film and depositing a passivation film on the entire top surface, a required electrode window is opened on the metal silicide film, and the metal silicide film is exposed through the electrode window. A method for manufacturing a semiconductor device, comprising an eighth step of forming connected low-resistance metal wiring. (2) A method for manufacturing a semiconductor device according to claim 1, characterized in that a polysilicon film is used as the silicon film.