JPS62114268A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a transistor having preferable frequency characteristic by opening a base contacting hole for forming a metal silicide film of a leading active base layer with a second silicon film as a mask to reduce a distance between a base electrode leading contacting hole and an emitter layer. CONSTITUTION:After a nitride film 203 is formed on a polysilicon film 602, it is selectively etched to allow the polysilicon film portions 602, 603 which become diffusion sources including the film 203 to remain, and with a resist film 302 as a mask a base contacting hole is opened. The film 302 is disposed in the film 602 of an emitter layer formation, with a part of the film 602 as a mask, the base contact and an oxide film 106, a PSG film 401 on a polysilicon film 601 continued thereto are removed by etching.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to an improvement in a method for forming an electrode lead portion of a transistor in a bipolar semiconductor integrated circuit device (hereinafter referred to as SIP/IC). It is something.

[Prior Art] Generally, transistors in an 81P-IC are formed in electrically independent islands by pH junction separation, oxide film separation using selective oxidation, or triple diffusion. Here, npn l-
A method for forming a transistor will be described. of course,
This method can also be applied to cases where the above-mentioned various separation methods other than oxide film separation are used.

FIGS. 4A to 4E are cross-sectional views showing the main process steps of a conventional method for manufacturing a semiconductor device. This manufacturing method will be briefly explained below.

After selectively forming an n-type (+)+ type) layer 2 with a high degree of impurity to serve as a collector buried layer on a p-type (p-type) silicon substrate 1 with a low impurity concentration, an n- A shaped epitaxial layer 3 is grown (FIG. 4A). Next, the underlying oxide film 1
Using the nitride film 201 formed on the surface of 01 as a mask, selective oxidation is performed to form a thick 1I1 film 102. At this time, a p-type layer 4 for channel cutting is simultaneously formed under this isolation oxide film 102. (Figure 4B). next,
The nitride g! used as a mask for the selective oxidation mentioned above. 201
Underlay oxidation 1! ! 101 and oxide 11103 for ion implantation protection are formed again, and photoresist WA (7 photoresist preparation at this stage is not shown).
Using this as a mask, remove the p+ type layer 5, which will become the external base layer, and remove the photoresist film, form a new photoresist layer 301, and use this as a mask to form prt3Fm6, which will become the active base layer, by ion implantation. form (Figure 4C).

Next, Photoresist I! ! 301 is removed and a passivation film 401, typically made of phosphoric-1-glass (PSG), is deposited to form the base ion-implanted layer 5.6.
After performing a heat treatment that also serves as 7-annealing and baking of PSG JI 401 to form an intermediate stage external base layer 51 and active base layer 61, emitter electrodes (main extraction contact holes 705 and collector A contact hole 80 for electrical equipment extraction is formed, and an n+ type layer 7 to be an L mix 1 and an n+ type 118 to be a collector electrode extraction layer are formed by ion implantation (FIG. 4D).

After that, each ion implantation layer is annealed to form the external base 1.
After completing ii52 and active base layer 62 and forming emitter layer 71 and collector electrode lead-out 1181, contact hole 50 for base electrode lead-out is formed, and each contact hole 50, 70, and 80 is provided with a hole to prevent the electrode from being handled. metal silicide [platinum silicide (Pt)]
-8i>, palladium silicide (Pd-8i)
etc. 111501, aluminum<AH
9. Base bridge wiring with low resistance metal such as >. In front of emitter electrode wiring 10 and collector electrode! 1111 (Fig. 4E).

FIG. 5 is a plan pattern diagram of a transistor manufactured by this conventional manufacturing method.

[Problems to be Solved by the Invention] By the way, the frequency characteristics of a transistor depend on the base-collector capacitance, base resistance, etc., and it is necessary to reduce these in order to improve the frequency characteristics. In the above structure, the p+ type external base layer 52 is provided in order to reduce the base resistance, but this has the problem of increasing the base-collector capacitance. Furthermore, the base resistance also depends on the distance between the emitter layer 71 and the contact hole 50 for taking out the base electrode, as shown in FIG. This is the total distance of the protrusion of each electrode wiring 9, 10 from each contact hole 50, 70. Even if the accuracy of photoetching is improved and the electrode wiring spacing is reduced, the protrusion described above cannot be avoided. There was a problem that remained.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device in which the base resistance and base-collector capacitance can be reduced, and at least the emitter resistance can be reduced.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention is such that the base electrode is taken out directly from the active base layer through the double layer of the first silicon film and the metal silicide film, and In this method, a part of the emitter electrode is formed of a second silicon film, and using this second silicon film as a mask, a contact hole is formed for forming the metal silicide film of the active base layer.

[Function] In this invention, the base of the base electrode is located within the distance between the base'Ni electrode extraction contact hole and the emitter layer.
There is no need to incorporate the protrusion from the contact hole for taking out the Fu81i and the protrusion of the emitter electrode from the contact hole for taking out the emitter electrode, and the above distance can be shortened and the base resistance can be reduced.

Furthermore, since an external base layer with a high impurity concentration is not provided, an increase in base-collector capacitance does not occur. In general, since at least the emitter iw is formed of the second silicon film and the metal silicide film, the emitter resistance can be reduced.

[Fruitful example] Hereinafter, embodiments of the present invention will be explained with reference to the drawings.

In the description of this embodiment, the description of the conventional technology and the parts related to the molding tank will be omitted as appropriate.

1A to 11 are cross-sectional views showing the main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. To explain this manufacturing method, the 4th B
Up to the state shown in the figure, an n'' type collector is buried in a p-type silicon substrate 1, an oxide film for isolation 102, and a p-type layer for channel cutting 4. After forming the nitride film 201 and the underlying oxide film 11101 in the fourth BI!l, an oxide film 103 for protecting ion implantation is formed again, and a p-type 1i6 film, which will become the active base layer, is formed through a photoresist mask (not shown). is formed by ion implantation, and the base Ti
Oxidation near the area that should become the contact hole for pole extraction! ! I
103 and apply polysilicon ill 601 to the entire surface including the removed part! II@ (Figure 1A). Next, p-type impurities are introduced into the entire surface of the polysilicon film 601, and then sintering is performed to
After using the shape 6 as an active base 161 at an intermediate stage, polysilicon Nu 601 is selectively etched and removed, and oxidation is performed once again to form an oxide film 1 at the position where the oxide film 103 was.
05. Oxide film 1 is formed on the surface of the remaining polysilicon film 601.
06 is formed, and then a PSG film 401 is formed on the entire surface (FIG. 1B). Emitter IIJ is then etched by selective etching using a photoresist mask (not shown).
A film 10 in the region to become the rectifier electrode extraction layer
5. Remove PSGil1401 and polysilicon IK6
Avoid depositing 0.2. After this, an invasive drive is performed by ion-implanting n-type impurities into the polysilicon film 602 at a high concentration, and from this polysilicon film 602, the n-type m71 J5 and Form the n+ layer 81 that should become the collector electrode extraction layer (
Figure 1C). Next, after forming nitride m203 on the surface of polysilicon 111602 by low-pressure CVD or the like, selective etching is performed to leave only the polysilicon film portions 602 and 603, including this nitride film 203, which served as the diffusion source. Then, a base contact hole is formed using the resist film 302 as a mask (FIG. 1D). At this point, the resist film 302 is replaced with the polysilicon film 60 for forming the emitter layer.
This polysilicon II! 6
Oxidation of the base contact and the subsequent surface of the polysilicon film 601 using 02 as a partial mask! 1106. P.S.G.
i! 401 is removed by etching. Furthermore, when this oxide film etching is performed by an anisotropic etching RIE (reactive ion etching) method, the resist film left when the polysilicon 1602 and 603 is selectively etched is left behind and this oxide film is etched. Nitriding during film etching 191203. Polysilicon [1602,6
This may prevent the decrease in m of 03.

In addition, here, polysilicon [1603 was left on the surface of the collector electrode extraction layer 81, but the collector electrode extraction layer W! Since J81 is diffused, it is also possible to remove the polysilicon film 603. Low temperature (800℃~900℃
) to form a polysilicon film 60 of n0 layers.
2. Thick oxide I1108 is applied to the sidewalls of 603, and the active base layer 62 of the p-type layer and the polysilicon film 601 of the p+-type layer are
A thin oxide film 107 is formed on the surface (FIG. 1E). This takes advantage of the fact that silicon and polysilicon containing n+ type impurities such as phosphorus and arsenic at temperatures as high as 111 degrees undergo rapid oxidation at low temperatures.Next,
After forming a nitride film on the surface using low pressure CVD, etc., if anisotropic etching such as RIE is performed on the entire surface, 11010 oxide is formed.
Nitride II only on the sidewalls of 7.108! 204 remain (first
Figure F). Next, acid etching is performed to remove the nitride film 20.
3.Remove the entire surface of 204, and then remove the polysilicon film 601.
By washing out the thin oxide film 107 remaining on the surface of polysilicon! 11601.602.6
The surface of 03 appears (Figure 1G). Here, the nitride film 204 was formed in the IIIJ chamber of the polysilicon films 602 and 603 because the thick oxide film 108 formed on the side walls of the polysilicon films 602 and 603 was replaced by the thin oxide film 108 on the surface of the polysilicon film 601! This is to prevent the song from becoming weaker when washing out the J107. Also, nitrogen 1
Instead of forming the filler film 204, it is also possible to wash out the thin oxide film 107 by RIE.This can simplify the manufacturing process, but it is necessary to pay sufficient attention to the etching accuracy bJm. Yes. Pt, P
d, Ti.

After forming a metal layer (not shown) such as W or MO to form a metal silicide between the silicon 6 and the polysilicon film on the entire surface by vapor deposition or sputtering, sintering is performed to form metal silicide films 501 and 502. The exposed surface of active base 1162 and polysilicon film 60
After forming on the surface of 1,602,603, the metal layer is removed by etching with aqua regia etc., leaving a metal silicide film.
1st HIM). Next, nitride 1202 for passivation
After covering the nitride film 202 (which may also be a nitride film),
After performing selective etching to form a contact hole bO for taking out the base electrode, a contact hole 70 for taking out the emitter electrode, and a contact hole 80 for taking out the collector electrode, the base electrode wiring 9.
Emitter electrode wiring 10 and collector electrode lead-out 11 are formed respectively (FIG. 11 2) As another example, when forming a polysilicon film 601 that will become a part of the base electrode, as shown in 21i!J, By excessively etching the oxide film 103 in FIG. 1A, a polysilicon film 6 is formed on the side wall of the silicon island 3.
01 comes into contact with the polysilicon [
The contact surface 90 of 1601 with the active base layer 62 is small, and the base area can be reduced. For etching of butyric acid 1103, it is best for the diffusion M63 from the polysilicon film 601 to be approximately the same depth as the active base layer 62 from the viewpoint of breakdown voltage. Furthermore, by forming polysilicon 11601 before forming active base 11162, active base li! The depth of the active base layer 62 can be controlled and prevention of crystal defects in the active base layer can be improved.

FIG. 3 is a plane pattern diagram of a conventional transistor manufactured in this manner and corresponding to FIG. 5, in which the emitter 11
71 and the metal silicide 11501 connected to the base electrode 9 via the polysilicon film 601
D2 is determined by the overlap between the window opening for diffusion (corresponding to 71) and the polysilicon film 602 that serves as the diffusion source, so it is smaller than the conventional distance shown in FIG. can. Therefore, not only is the base resistance reduced by that amount, but it is also
(several 10 ohms/hole to 100 ohms/hole) instead of metal silicide group 501 (several ohms/hole to several 10 ohms/hole), which has a low resistivity, so it is small. In addition, the collector electrode is formed using a polysilicon film 603. The emitter electrode is formed by a metal silicide film 502 and a polysilicon film 602. Metal silicide 91502
, the contact resistance is small, resulting in collector resistance.

Emitter resistance can be reduced. Furthermore, since the l11+ type external base layer 52 is not used and the active base layer 62 itself is slightly smaller, the base-collector capacitance is also reduced. Therefore, the frequency characteristics of the transistor are improved.

[Effects of the Invention] As described above, according to the present invention, the base electrode is formed in the double layer of the first silicon film and the metal silicide film on the isolation region in contact with the lead-out active base layer, and a part of the emitter electrode was formed using a second silicon film, and using this second silicon film as a mask, a base contact hole was formed for forming the metal silicide film of the above-mentioned lead-out active base layer. By reducing the distance to the layer, the base resistance can be reduced. Furthermore, since at least the emitter electrode is formed of the second silicon film and the metal silicide group, the contact resistance is reduced.
As a result, emitter resistance can be reduced. Furthermore, since an external base layer with a high impurity concentration is not provided, the base-collector capacitance can be reduced. Therefore, there is an effect that a transistor with good frequency characteristics can be obtained.

[Brief explanation of drawings]

1A to 11 are cross-sectional views showing the main process steps of a method for manufacturing a semiconductor device, which is an example of the present invention. FIG. 2 is a sectional view showing a state in one main step of a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 3 is a plan pattern diagram of a transistor manufactured by the manufacturing method of the present invention. FIGS. 4A to 4E are cross-sectional views showing the main process steps of a conventional method for manufacturing a semiconductor device. FIG. 5 is a plan pattern diagram of a transistor manufactured by a conventional manufacturing method. In the figure, 1 is a p-type silicon substrate, 2 is an n" type collector buried layer, 3 is an n-type epitaxial layer, 4 is a p-type layer for channel cut, 6 is a p-type layer, 9 is a base electrode wiring, 10 is the emitter electrode wiring, 11 is the flutter electrode wiring,
61.62 is the active base layer, 63 is the diffusion layer, 71.81
is an n+ type layer, 50 is a contact hole for extracting the base electrode, 7
0 is a contact hole for emitter i pole number output, 80 is a contact hole for taking out the collector electric bridge, 90 is a contact surface, 102 is an oxide film for isolation, 103, 105. 10G is an oxide film, 107 is a thin oxide film, 108 202 is a nitride film for passivation, 203 and 204 are nitride films, 302 is a resist film, 401 is a PSG film, 501 and 502 are metal silicide films, and 601. 602 and 603 are polysilicon films. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A first step of forming a first conductivity type layer surrounded by isolation regions and constituting a collector region on the surface of a semiconductor substrate, and a base of a second conductivity type formed on a part of the surface of the first conductivity type layer. a second step of forming a first silicon film from a part of the surface of the base layer to a surface of the isolation region in contact with the base layer; a fourth step of forming a silicon oxide film on the surface of the first conductivity type layer and the first silicon film, selectively etching the silicon oxide film to form a collector electrode extraction layer of the first conductivity type layer; a fifth step of removing the silicon oxide film on the surface of the portion to be formed and the surface of the portion where the emitter layer is to be formed, the exposed surface of the portion where the collector electrode extraction layer is to be formed, and the exposed emitter layer; A second silicon film is formed on the surface of the portion where the collector is to be formed and on the surface of the silicon oxide film, and impurities of the first conductivity type are introduced into the second silicon film at a high concentration, and then annealing is performed to form the collector. The second layer is applied to the portion where the electrode extraction layer is to be formed and the portion where the emitter layer is to be formed.
a sixth step of diffusing impurities of the first conductivity type from the silicon film to form the emitter layer and the collector electrode extraction layer; a first silicon nitride film is formed on the surface of the second silicon film; a seventh step of selectively removing the first silicon nitride film and the second silicon film so as to leave at least a portion where the first silicon nitride film and the second silicon film cover the emitter layer; process,
an eighth step of selectively removing the silicon oxide film on the surface of the base electrode extraction region of the base layer and the surface of the first silicon film; A ninth step of forming a thick silicon oxide film on the side walls and a thin silicon oxide film on the surface of the base electrode extraction region exposed in the eighth step and the surface of the first silicon film at a relatively low temperature. a tenth step of washing out the thin silicon oxide film after removing the first silicon nitride film; a surface of the exposed base electrode extraction region;
an eleventh step of forming a metal silicide film on the exposed surface of the first silicon film and the exposed second silicon film; A protective film is formed on the surface of the exposed region, and a base electrode is formed on the first silicon film, an emitter electrode is formed on the emitter layer, and a collector is formed on the collector electrode extraction layer through the openings provided in the protective film. A method of manufacturing a semiconductor device, comprising a twelfth step of forming an electrode. (2) After the first step, the first silicon film is formed by forming a polycrystalline silicon film on the surface of the entire region, introducing impurities of a second conductivity type into the polycrystalline silicon film, and then patterning the film. Claims in which the polycrystalline silicon film is formed by leaving a part of the surface of the portion of the first conductivity type layer where the base layer is to be formed to the surface of the isolation region in contact with the first conductivity type layer. 2. A method for manufacturing a semiconductor device according to item 1. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the second silicon film is a polycrystalline silicon film. (4) After the ninth step, a second silicon nitride film is formed on the surface of the thick silicon oxide film and the first silicon nitride film, and a difference between the first and second silicon nitride films is formed. After performing directional etching to leave a silicon nitride film on the surface of the second silicon film and the thick silicon oxide film, the thin silicon oxide film is washed out, and then the silicon nitride film is removed. A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is removed.