JPS60103669A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the base resistance so as to deteriorate the cut-off frequency and the collector junction capacitance by a method wherein the first base contact is provided in part on a base region, a metallic Si alloy layer being provided thereon, and the second base contact being then provided thereon. CONSTITUTION:After an n<+> buried layer 12 is formed in a p type substrate 11, an epitaxial layer 13 is formed and isolated by an oxide film 14, and an n<+> type collector lead-out layer 15 is formed. The pattern to serve as a graft base region 16 is formed, thereafter a polycrystalline Si layer (poly Si layer) 18 and an Si nitride film 20 are deposited; then, the pattern made of a resist 33 is formed only on the region where emitter and collector contacts are formed. After removal of the resist, newly a resist pattern is formed only at the part to serve as the emitter and collector contacts and heat-treated as required, and thus the phosphorus or arsenic in a poly Si layer 19 is diffused into the Si. Al is adhered by evaporation ane the like, thus forming patterns 30-32 to completion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a transistor with good high frequency characteristics and a method for manufacturing the same.

[Prior art]

An example of a conventional high-speed transistor is shown in FIG.

FIG. 1(A) is an overall view, in which 1 is a substrate, 2 is a buried collector, 3 is an oxide film, 4 is an epitaxial region, and 5 is a low-resistance heath region (usually called a graft base region). , 6 is the active base region, 7
8 is an emitter region, 8 is an aluminum wiring, and 9 is a collector contact region.

FIG. 1(B) is an enlarged view of a part of the transistor shown in FIG. 1(A), where A1°A2&
'End LB of the LA1 wiring 8. B is the end on the emitter side of the base contact hole, and E is the end on the base side of the emitter contact (or emitter-base junction).

For transistors that operate at high frequencies, cutoff wavenumber (cut off frequency) is a characteristic value that indicates high frequency characteristics.
Although it is essential to have a structure with high ft, it is even more important to increase the maximum repetition frequency (f□X) in order to improve the high frequency characteristics on the circuit. . This fyuaX'work'nax
Therefore, in order to make s fmixt high, not only the cutoff wave number f, but also the minimum value for base resistance r bb' and collector junction capacitance Crc' It is necessary to limit the

These three are not independent from each other in terms of transistor structure, so it is important to select a structure 7 that provides a good balance between the three. This will be explained using the transistor shown in FIG. 1 as an example.

f, 4-high (one of the methods is to make the junction depth of the active base region 6 and emitter region T shallow (and the effective base width W,
Y! - There is a way to reduce the sheet resistance, but in that case, the sheet resistance value of the active base region 6 must be selected to be high, usually several hundred to several thousand Ω/hole, for reasons such as preventing junction leakage.
rbbI increases. In order to improve this problem, a method of using the graft base region 5 to prevent the base resistance rbb' from increasing can be adopted.

It is desirable that the graft base region 5 has as low a resistance as possible, and that the diffusion end C is located as close to the emitter region T as possible. However, lowering the resistance depends on the collector junction capacitance C? . In addition, if the position of the diffusion end C is in contact with T directly below the emitter, the base-emitter capacitance increases, which degrades the cutoff layer wavenumber f and Y, and increases emitter-base junction leakage. Since this results in deterioration of the DC% property, a value of several tens to hundreds of Ω/hole is usually adopted as the sheet resistance and a value of about 2 to 3 μm as the distance between C and E.

By the way, other parameters governing the base resistance rbb' include the distance between the base contact and the emitter and the resistance directly below the emitter.

The former depends on pattern resolution and overlay accuracy, i.e.
Distance between AI wiring 8 (distance between At-A2) and emitter
Distance between each contact on the base and the end of AI wiring 8 (B-
A1 and A2-E). Normally, the distance between Al and A2 is about 2 to 4 μ, between B and A1, and between E and
The distance between A2 and shin also takes a value of about 1.0 to 1.5μ, and therefore the distance between B and E is about 4 to 7μ. The latter is determined by the emitter width, and the smaller the emitter width, the smaller the base resistance rbbI&co becomes, and when a projection aligner is used, it is about 2.5 to 3.0 μm.

Furthermore, it is possible to reduce the emitter width by using a reduced projection exposure apparatus, but this poses some problems in terms of mass production.

Therefore, in conventional transistors, there is a limit to reducing the emitter width, and the base resistance r bb'
There were great difficulties in making it as small as desired.

[Summary of the invention]

The present invention has been made in view of the above points, and an object thereof is to provide a transistor with better high frequency characteristics and a method for manufacturing the same. In this invention, the main focus is on the base resistance rbb', and the base resistance rbbI is set to 1/2 to
The present invention provides a transistor structure that improves the collector junction capacitance CtC and the cutoff frequency f, yIl-(maximum repetition frequency fm0) while reducing 1/4Vc.

[Technical field of invention]

An embodiment of the present invention will be described below with reference to FIGS. 2(A) to 2(H).

In FIG. 2(A), an n+ buried layer 1 is formed on a p-type substrate 11.
2 is formed, an epitaxial layer 13 is formed by epitaxial growth, separated by an oxide film 14, and reaches the n+ buried layer 12 from the surface (n+ type collector drawer ff1
15)? Formed by diffusion.

FIG. 2(B) shows that a putter foot, which is to become the graft base region 16, is formed by an ordinary photolithography process and then formed by ion implantation or the like.

In this invention, as described later, although the effect of reducing the base resistance r bb' itself is small, the main purpose is to reduce the base contact resistance, and depending on the selection of the base resistance value, the contact resistance (In that case, the process in FIG. 2 (B) can be omitted. Also, in this case, the collector junction capacitance CtC is reduced, and the maximum repetition frequency frII,x is good ~・Brings result t.

FIG. 2C shows an active base region 17Y formed by photolithography, ion implantation, etc. in the same way as the graft base region 16, and then the oxide film 14 in the active region is removed.

FIG. 2(D) shows the polysilicon layer below the polycrystalline silicon layer C5)18. Next, after depositing a silicon nitride film 2o, a pattern using a resist 32 is formed only on the regions where the emitter and the flaft contact (Y) are to be formed. This pattern does not have to be formed precisely;
It is better to make it slightly larger than the emitter and collector contacts that will be formed later. Next, phosphorus or silicon arsenic ions are implanted into the pattern to form a polysilicon layer 19 containing n-type impurities.

In FIG. 2(E), after removing the resist 32, a new resist pattern is formed only in the portions that are to become emitter contacts and collector contacts, but this time, contrary to FIG. 2(D), the emitter and collector Make sure that the resist remains only on the contact area. It is clear that this makes it possible to produce particularly small emitter dimensions. Thereafter, the silicon nitride film 20 and the polysilicon layer 19 other than the emitter contact and the collector contact are removed by a technique such as plasma etching or active ion etching (RIE). At this time, it is desirable to remove as much as possible. The reason for this is that the emitter-base junction area can be reduced by removing the emitter sidewall and forming an oxide film as shown in FIG. 2(F).

In FIG. 2(F), a necessary heat treatment is performed to diffuse phosphorus or arsenic in the polysilicon layer 19 into silicon to form an emitter region 21 and a collector contact 22. At the same time, the exposed silicon surface is oxidized to 100%
An oxide film 23Y having a thickness of about 0 to several 100 degrees is formed.

FIG. 2(G) shows that after removing the silicon nitride film 20 on the emitter region 21 and the collector contact 22, a first base contact 24 is formed by photolithography. At that time, it is important to make the distance between the emitter contact and the first base contact 24 close, but with today's mask alignment technology, this distance can be reduced to 1.
5 to 2.0 μm is quite possible. After that, for example, P
Alloy layers 25, 26, 27'r of PT, etc. are formed on the surface of the polysilicon layer 19 on the substrate 2 and on the silicon surface of the first base contact 24.

Next, as shown in FIG. 2 (rH), after depositing an oxide film 28Y of phosphorus glass or the like by CVD, the emitter region 21. Collector contact 22. A window is formed on the first base contact 24, and in this case, the position of the window of the second base contact 29 is set in the emitter region 21.
Form it away from the That is, the distance is the interval G-H of the At wiring 30.31 which is an electrode and the overlap between the window of each contact and each At wiring 30.31 772~0
Question and each distance between H-J! equal to the distance added. After that, it is deposited using AIY vapor deposition or the like to form a pattern and complete the process.

Considering the base resistance y bb I in the above structure, the distance between the pace contact and the emitter F-J is F-
It is divided into Nitoni and J. There is a ptst alloy layer between F~, and the resistance is lowered by i/zo~1150 compared to the sheet resistance of the graft base directly under it, so the base resistance rbb' of this part is lower than the conventional one. can be almost ignored. Therefore, the base resistance rbb' at the distance between the pace contact emitters is determined by the resistance between K and 7, which is almost the same as the conventional sheet resistance, but the distance is 1/2 to 1/2 of the conventional distance. It has been reduced to /4. Next, as for the resistor directly under the emitter, as mentioned above, the dimensions of this resistor are also controlled using the remains of the Lujist, and since it is etched and oxidized from both sides, even with the conventional Aquina, it is 1.0~ The base resistance r bb' can be set to a sufficiently possible dimension of 1.5 μm, and the base resistance r bb' can be substantially the same or lower than that of the conventional structure. Furthermore, by adopting emitter diffusion using polysilicon, the diffusion depth t of the base region and emitter region can be made shallower, and the emitter sidewalls can be made shallower. By covering with an oxide film, fTv is improved.

Furthermore, although the graft base region is also used in the above-mentioned embodiment, it is only used to improve the ohmink property with the PT and ST containing layers, and the base resistance is 01.
Depending on i, ohmic properties can be ignored and the graft base region can be omitted. In that case, in the conventional structure, the base resistance rbb' increases (but
In this invention, the change in base resistance rbb' is negligibly small. Therefore, the collector junction capacitance CTC can also be reduced to the same level or by eliminating it on a graft basis compared to the conventional one.

〔Effect of the invention〕

As explained in detail above, the semiconductor device of the present invention has
a first base contact is provided on a portion of the base region;
Since the metal silicon alloy layer is provided on this and the second base contact is provided on this metal silicon alloy layer, the base contact resistance can be reduced, and thus the base resistance can be reduced. In addition, the side surfaces of the emitter are covered with an oxide film and the emitter-base junction area is small, so the maximum repetition frequency f KIII
Cutoff frequency f that governs LX? +flexor junction capacitance C
'? e Of the manufactured base resistance rbb', f? , C
, c'&rbb' y]l while being the same or improving
-Can be reduced to 1/2 to 1/4. The manufacturing method of the present invention has the advantage that semiconductor devices can be manufactured without impairing conventional mass productivity.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing a conventional transistor, Figure 2 is a cross-sectional view of a conventional transistor;
) to (H) are cross-sectional views of a transistor in required steps showing an embodiment of the manufacturing method of the present invention. In the figure, 11 is a p-type substrate, and 12 is ? A buried layer, 13 is an epitaxial layer, 14 is an oxide layer, 15 is an n+ collector extraction layer, 16 is a graft base region, 17 is an active base region, 18 is a polysilicon layer, and 19 contains an n+ type impurity. Polysilicon layer, 20 is a silicon nitride film, 21 is an emitter region, 22 is a collector contact, 23 is an oxide film, 24 is a first base contact, 25.26.27
is Pt5t alloy, 28 is oxide film such as phosphorus glass, 29 is
is the second base contact, 30 and 31 are At wirings, 3
2 is a resist. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 (A) (B) (B) Figure 2 OuJ - Figure 2 FGKHJ Procedural amendment (voluntary) 1. Indication of the case Patent Application No. 1988-2121388 2 , Title of the invention Semiconductor device and its manufacturing method 3, Representative Hitoshi Katayama of the person making the amendment, Department 4, Agent 5, Claims column 1 of the specification to be amended, Detailed description of the invention column 9
Brief Description of Drawings, Drawing 6, Contents of Amendment (1) The claims of the specification will be amended as shown in the attached sheet. (2) Similarly, “Regist 3” on page 8, line 17 and page 9, line 4.
2" are respectively corrected as "registration 33". (3) Similarly, change “rK-T” on page 12, line 1 to rK-J.
Correct it to "between." (4) Also on page 14, lines 16-17, “30°31 is A.
The M wiring 32 is a resist. ”, r30, 31.
32 is an AfL wiring, and 33 is a resist. ” he corrected. (5) Correct the drawing in Figure 2 (D) as shown in the attached sheet. Above 2, Claim (1) - A substrate of a conductive type, an epitaxial layer of an opposite conductive type formed on the substrate, and a buried layer of an opposite conductive type formed at a boundary between the substrate and the epitaxial layer. With a mixed layer,
A separation layer or an oxide film insulating layer of one conductivity type is provided in a shape that reaches and surrounds the substrate from the surface of the epitaxial layer, and a collector region, a base region, and an emitter region are formed in the epitaxial layer. In the semiconductor device, a first base contact is provided on a portion of the base region, a metal silicon alloy layer is provided on the Ml base contact, and a second base contact layer is provided on a portion of the metal silicon alloy layer. a polycrystalline silicon layer containing impurities of the opposite conductivity type in contact with the upper part of the emitter region; A semiconductor device characterized in that a metal silicon alloy layer and a metal silicon alloy layer are sequentially provided. (2) - After providing a buried layer of an opposite conductivity type on a substrate of a conductivity type, an epitaxial layer of an opposite conductivity type is provided on the substrate, and a film of one conductivity type or an oxide film reaching the substrate from the surface of this epitaxial layer. An oxide film on the surface of the epitaxial layer is formed after forming a co1/cota extraction layer of the opposite conductivity type and a base region of the -conductivity type in the epitaxial layer separated by the separation layer. After removing the polycrystalline silicon layer and sequentially depositing a nitride film, and introducing impurities of opposite conductivity type into the portion of the polycrystalline silicon layer whose lower part includes the portions to be the emitter contact and the collector contact, After removing a portion of the nitride film, polycrystalline silicon layer, and surface of the epitaxial layer other than the portions to become the emitter contact and collector contact, the exposed surface of the epitaxial layer and the surface of the epitaxial layer are removed at the same time as the emitter contact and collector contact are formed. After oxidizing the surface of the crystalline silicon layer and then removing the nitride film, a first base contact is formed on the base region, and an oxide film of the polycrystalline silicon layer is formed on the first base contact and in the emitter region. A metal-silicon alloy layer is formed on the removed surface,
1. A method of manufacturing a semiconductor device, characterized in that a required wiring is then provided on the entire surface.

Claims (1)

[Claims] (11-A substrate of a conductivity type, an epitaxial layer of an opposite conductivity type formed on the substrate, and a buried layer of an opposite conductivity type formed at a boundary between the substrate and the epitaxial layer. and,
A separation layer or an oxide film insulating layer of one conductivity type is provided in a shape that reaches and surrounds the substrate from the surface of the epitaxial layer, and a collector region, a base region, and an emitter region are formed in the epitaxial layer. In the semiconductor device, a first base contact is provided on a portion of the base region, a metal silicon alloy layer is provided on the first base contact, and a second base contact is provided on a portion of the metal silicon alloy layer. , the emitter region is formed to be of an opposite conductivity type surrounded by a part or the entire side surface of an oxide film insulating layer, and a polycrystalline silicon film containing impurities of an opposite conductivity type is formed in contact with the upper part of the emitter region. A semiconductor device characterized in that a layer and a metal silicon alloy layer are sequentially provided. (2) - A diameter in which a buried layer of an opposite conductivity type is provided on a substrate of a conductivity type, an epitaxial layer of an opposite conductivity type is provided on the substrate, and an oxide film of one conductivity type or oxide film reaches the substrate from the surface of this epitaxial layer. After forming a collector extraction layer of an opposite conductivity type and a base region of a -conductivity type by diffusion in the epitaxial layer separated by this separation layer, the oxide film on the surface of the epitaxial layer is removed. After sequentially depositing a polycrystalline silicon layer and a nitride film V, and introducing impurities of opposite conductivity type into a portion of the polycrystalline silicon layer whose lower portion includes portions to become an emitter contact and a collector contact, the emitter contact is formed. After removing the nitride film, the polycrystalline silicon oxide film, and a part of the epitaxial layer surface other than the portion to be used as the collector contact, the epitaxial layer surface and the polycrystalline layer exposed at the same time as the emitter contact and the collector contact are formed. After oxidizing the surface of the silicon layer and then removing the nitride film, a first base contact is formed on the base region, and an oxide film of the polycrystalline silicon layer on the first base contact and in the emitter region is formed. After forming a metal silicon alloy layer on the removed surface and then oxidizing the entire surface,
A method for manufacturing a semiconductor device, characterized by providing required wiring.