JPS62183178A - Manufacture of bipolar transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides bipolar transistors characterized by shallow junctions for high switching speeds and capable of increasing packing density by LSI or VLSI. relating to manufacturing.

PRIOR ART AND PROBLEMS There is a strong desire to form bipolar transistors in VLSI processes that can provide high packing density and high speed switching. One process that has been proposed to achieve these goals is called polysilicon self-alignment or PSA. However,
The PSA process uses complex etch steps and double polysilicon sequences, which makes the overall flow difficult to manufacture and reduces the achievable yield. Another way to achieve high speed circuits is through sidewall-based contact structures. This 19th structure is also difficult to manufacture due to the large number of photolithographic levels and processing complexity. Other methods utilize the basic bipolar transistor profile with additions such as trench isolation rather than oxide isolation.

However, such devices were unable to achieve maximum speed.

111ell-117) lltFfF dish Therefore, it is an object of the present invention to provide a bipolar transistor cell formed by ■LSI process, which improves the switching speed and allows high packing density. .

The present invention provides a method for making bipolar transistors in an LSI or VLSI process.

This method uses a buried region (DUF) with a first conductivity type.
forming a collector, growing an epitaxial layer having a first conductivity type over the DLJF collector, and forming isolation means around the transistor region. The transistor region includes a trench that at least partially surrounds the transistor region and extends into the DUF collector. The epitaxial layers each have a first and a second 1! Emitter and base regions having electrical types are formed. A collector contact region having a first conductivity type is formed in the epitaxial layer and extends to the buried DUF collector.

Preferably, the trench surrounds the transistor region. Coat the sidewalls of the trench with oxide and then fill with polysilicon. By using only a thin oxide coating and polysilicon, problems inherent to oxide trenches due to the different expansion coefficients of oxide and silicon are avoided. A channel stop of a second conductivity type is implanted below the trench before filling it with undoped polysilicon. An oxide layer is grown over the epitaxial layer and then the resistor and base are implanted through the oxide into the epitaxial region. The collector region is deeply implanted directly into the epitaxial region. Heating the device anneals the implant damage. Doped polysilicon emitter and collector contacts are then formed. An emitter region is then formed in the base by heating the device to drive impurities in the polysilicon into the base and collector regions. Metal contacts and interconnects are then formed.

The first conductivity type impurity is N type, and the second conductivity type is P.
It is preferable that it is a shape. More specifically, the slow-diffusing impurity is antimony, and the fast-diffusing impurity is phosphorus. By using a thin oxide of i,ooo to 1°500, lower implant energies can be used to form the base, resulting in minimal dropout and a shallow base area. . By using boron as the impurity and implant energies of 5 Q keV or less, base depths of less than 5,000 are achieved.

By increasing the doping of the base impurity, the resistance value of the base can be reduced and the delay of the base can be reduced. By achieving a shallow junction, the epitaxial layer can be narrowed to 1.0 to 1.4 microns, thus lowering the collector resistance.

By forming trenches approximately 2 microns wide, devices can be integrated on a chip approximately an order of magnitude -m more densely than conventional bipolar devices.

Utilizing a deep collector implant avoids the long anneal times associated with standard deep collectors, thereby avoiding perturbing the boron diffusion profile.

The choice of antimony as the dopant for the DLJF region minimizes updiffusion from the buried collector, thus helping to achieve narrow epitaxial layers.

While the novel features considered characteristic of the invention are set forth in the claims, the invention itself, as well as other features and advantages, will be best understood from the following detailed description of the drawings.

Tomo-Yutaka-1 Figures 23 and 24 show one of many bipolar transistors formed on each of a number of silicon bars. formed from par or silicon slices. In a preferred embodiment of the invention, each transistor is constructed from a P-type single crystal silicon substrate 1o with an N-type antimony implanted DLJF region 12 extending into the slice to a thickness of 3 to 3.5 microns. ing.

An N-type epitaxial layer 14 is deposited over DUF region 12 to a thickness of 1.0 to 1.4 microns.

Trenches 18 filled with polysilicon divide substrate 10 and epitaxial layer 14 into multiple regions in which bipolar transistors are formed. Each transistor has a highly doped shallow base region 48 extending downward by only 3,000 to 4,000 nm, which is a highly doped P-domain region in the form of a rectangular strip with a rectangular volume in the center of the epitaxial region 14. The surface is in contact with 58. A metal contact 78 contacts both the P+ dec region 58 and the epitaxial region 14 to form a clamping Schottky diode between the P+ dec region 58 epitaxial region 14.

Platinum silicide 72 is used between metal contact 78 and silicon 14, polysilicon emitter 64 and collector contact 66 to provide good ohmic contact. The unclamped device is identical to FIG. 23, except that the P-cross region 58 extends completely below the base contact.

Shallow emitter 49 approximately 1,000 to 2,000 people deep
is formed in base region 48 by diffusion from phosphorous doped polysilicon emitter 64. deep N
A decagonal collector contact 62 is formed within the epitaxial region 14 and includes a DIJF region [1] that acts as a buried collector.
Contact with 2.

A metal contact 78 is formed over the surface and thermally grown oxide 20
a and the overlying nitride 152 insulate it from the epitaxial region 14, reducing the capacitance of the conductor. Optionally, a chemical vapor grown oxide film 80 may be used to further reduce capacitance. This coating provides a planarizing effect on the first rubel interconnect. 1 and 2, a P-type silicon substrate 10 is shown with a depth of 3 to 3.5 microns after annealing.
It is then subjected to a one-sided implant of antimony such that the final sheet resistance is 15-20 ohms/square. Antimony diffuses much more slowly into silicon than other types of donor impurities, such as phosphorous or arsenic.
Updiffusion into the overlying epitaxial layer is much less. Next, as seen in FIG. 3, an N-type epitaxial layer 14 is deposited under reduced pressure over the antimony implanted DUF region 12 to a thickness of 1.0 to 1.4 microns. , its resistivity is related to the application of the circuit. This thickness of epitaxial layer 14 is approximately 0% less than the epitaxial layer thickness used in conventional technology and requires shallow emitter and base regions.

Silicon dioxide 116 is then deposited to a thickness of approximately 1.0 to 1.5 microns. A layer of photoresist (not shown in the drawings) is then deposited over the silicon dioxide, exposed to ultraviolet light through a mask, and the exposed portions are removed to open a number of spaced trench regions. First deposit a 7-otoresist (not shown in the drawings), define its pattern, and etch the deposited oxide.
By etching the exposed silicon,
Trench region 18 is etched so that a deep trench having a width of 1.5 to 2.0 microns extends below DUF region 12.

As shown in FIG. 4, sidewall oxide 2o is grown on the walls of trench 18 by placing the cell in a vapor atmosphere at a temperature of about i,00° C. for about 15 minutes. Next, 4
A channel stop boron implant is directed into trenches 18 with an energy of 0 to 60 keV and a concentration of approximately 1×10 a/α2, and each trench 1 is
A P-shaped channel stopper region 19 is formed below 8 to prevent formation of an inversion layer around trench oxide sidewalls 20. As shown in Figure 5, by etching,
The silicon dioxide layer 16 on the surface of the N-type epitaxial layer 14 and the silicon dioxide layer on the trench sidewalls are removed. A new sidewall oxide layer is grown as shown in FIG.

The trench 18 is then filled with a polysilicon deposit 22, and a planar photoresist layer 24 is deposited over this layer, as shown in FIG.

Photoresist 24 is chosen to have approximately the same etch rate as the underlying polysilicon. Therefore, when the photoresist and polysilicon are etched down to the oxide surface, a flat oxide surface 2 as seen in FIG. 8 is obtained. By using the trenches as isolation regions, oxide encroachment into the active device areas, as occurs in devices using conventional oxide isolation, is avoided and packing densities can be significantly increased. For oxide isolation, current design rules require 8 to 10 microns of separation between transistors to achieve acceptable tank-to-tank breakdown voltages, whereas for polysilicon-filled trenches, the trench A width of 1.5 to 2 microns is the limit for separation.

Referring to FIG. 9, silicon nitride WJ 30 is formed on the oxide surface by low pressure chemical vapor deposition. As seen in FIG. 10, a photoresist layer 32 is deposited over the nitride 30 and then patterned and the exposed isolation regions 34 are etched to remove the nitride 30 and oxide 20. After this, the whole slice should be about 90
Exposure to a high pressure oxidizing atmosphere at 0° C. for approximately 2 hours. During this oxidation, silicon is consumed, thereby forming a relatively thick oxide isolation region 36, as seen in FIG.

The nitride is then etched away along with the oxide layer 20, as seen in FIG. Thereafter, a more complete and more uniform oxide layer 20a is thermally grown. 13th
A photoresist layer 38 is used to pattern the openings for the resistor/base implants as shown. The implant is performed at an energy of 40 to 60 keV and at a concentration appropriate to obtain the sheet resistance required by the application of the device. Resistor implants (not shown) are performed in different discrete areas separated by different pairs of trenches. Using conventional processing, an a-opening 40.42 forming an elongated P-shaped implanted resistor body and P-shaped implant regions at each end thereof is defined by the photoresist layer 38 and is shown in FIG. has been done. A layer of photoresist is then deposited over the first resist and exposed through a mask that allows the resist to cover the resistor body (not shown). After removing the exposed 7 photoresist, the surface is implanted with boron for the intrinsic base. Apply another layer of hood resist 44;
Configuring the features with photoresist level 38 opens areas 42, 46 as seen in FIG. The extrinsic base boron implant results in a P-shaped region 58 as shown in FIG. It extends approximately 4,000 to 5,000 nm below the silicon surface and has a sheet resistance of 80 to 100 ohms/square.

The P-shadow region 48 obtained by the extrinsic implant extends approximately 3,000 to 4,000 degrees below the surface of the silicon. Base region 48 is heavily doped to the point where its sheet resistance is 600-800 ohms/square. This high level of base doping reduces the base resistance and thus reduces gate delay and switching time. All junction depths and sheet resistances mentioned above are the final values of the process.

Strip the photoresist 38, resistor block (not shown in the drawing) and photoresist 44 and apply surface passivation nitridation over the surface using low pressure chemical vapor deposition (LPGVD) as shown in FIG. A material layer 52 is formed. Thermal oxide 2o and LPGVD nitride 52 help minimize the capacitance of the conductor to ground. Another photoresist layer 54 is deposited over the nitride 52 and oxide 20a and patterned and etched to open a region 56 for the collector and a region 60 for the emitter. Photoresist 42 is used as an implant stop layer over the emitter and patterned by conventional means. 5
A deep phosphorus implant is performed at an energy of 100 to 120 keV with a concentration in the range of ×1015 to 3×10 atoms/α2.

As shown in FIG. 17, except for the photoresist layer 42,
Emitter contact area 6o is opened. A short base anneal is performed to drive the collector and anneal any implant damage. Polysilicon is then deposited into the holes 56,60 and over the nitride surface 52. A phosphorus implant is performed in polysilicon at an energy in the range of 80-100 keV and a concentration of 5.times.10.sup.15 to 2.times.10.sup.16 atoms/.alpha.2. A polysilicon pattern is then defined and etched to form emitter 64 and collector contacts 66, as shown in FIG. A 900° C. emitter anneal is performed to drive the phosphorus downward from the emitter polysilicon into the emitter region 48.

This anneal also drives phosphorus from the collector polysilicon 66 into the collector region 62. Due to the highly doped shallow base region 48, it is necessary to use an efficient polysilicon diffused emitter 64. In devices with shallow emitters, surface recombination at the metal contact surfaces reduces the current gain (for small changes in emitter junction lumpiness, the base current increases significantly, but the collector current remains flat). ). The reason for such a small gain is that there are large fluctuations in the crystal properties at the interface.)
, because the depth of the emitter junction is shallower than the diffusion length of the holes in the emitter, which leads to severe recombination in the area of the emitter contact. Implant only polysilicon,
Because it is used as a diffusion source for the monocrystalline portion of the emitter, the polysilicon does not incur unwanted implant damage to the monocrystalline silicon substrate. For this reason, almost ideal small current performance is obtained with forward injection, and the dielectric breakdown characteristics are improved due to the phosphorus emitter distribution. Therefore, over the normal operating range of bipolar transistors, current gain is nearly independent of current level.

Another deposit of photoresist 68 and opening areas 6 as shown in FIG. 19 for forming contacts and leads.
Patterning and etching is required to form 9. Next, open area 69, polysilicon contact 64 .
A platinum layer 70 is sputtered over the surfaces of 66 and nitride layer 52. By sintering platinum, Figure 20 and Figure 2
As seen in FIG. 1, platinum silicide 72 is formed wherever platinum and silicon are in contact, and the unsintered platinum is removed. A metal layer 76 is deposited on the surface, patterned and etched using photoresist, leaving the structure shown in FIG. The platinum silicide reduces the resistance of the ohmic contact between the silicon and the corresponding metal contact.

The rest of the process is standard metal fabrication.

Optionally, as shown in FIG. 23, a 10,000 thick conformal silicon dioxide layer 80 can be deposited by a low temperature chemical vapor deposition method. The thickness of layer 80 causes it to be relatively planar. This silicon dioxide layer is etched back by about 2,000 times over the polysilicon by a resist etchback method, so that the upper surface thereof is made into a flat surface. Contacts for the emitter, base and collector are made and metal 78 is deposited and patterned as shown. The necessary improved alignment to the first metal level is achieved, as well as reduced interconnect capacitance and better reliability and planarization.

The trench structure seen in the base area of FIG. 24 has both outer 84 and inner 86 walls angled at 45 degrees on each side to maintain a constant width at the corners and to keep the trench width constant. This avoids creating voids in the polysilicon used to fill the As shown in FIG. 25, when two bipolar transistors 88, 90 are placed adjacent to each other, trenches 18 are patterned with cutouts 92.

By using shallow junctions, thin epitaxial layers can be used without significantly increasing collector-base capacitance. The thin epitaxial deposit lowers the collector resistance and reduces charge storage beneath the active base. By using a short base anneal after a deep collector implant, to the extent possible by conventional means using phosphorus-oxychloride diffusion.
A method is provided for reducing the collector resistance and providing better control over the diffusion distribution. By using antimony, which diffuses into silicon much more slowly than other impurities such as phosphorous, it is possible to create a buried collector, or DUF.
The extent of up-diffusion of region 14 is limited, thus allowing for a thinner epitaxial layer 12. For conventional oxide separations, the current standard is 8 microns for breakdown voltage requirements. By using narrow 2 micron wide trenches filled with polysilicon, the present invention can increase packing density by an order of magnitude over that possible with conventional oxide isolation.

The use of highly efficient polysilicon diffused emitters allows for enhanced doping of the active base. Highly doping the base makes the base resistance lower and hence the gate delay (or switching i).
(between) is made even smaller.

Improved packing density reduces spacing between metals,
As a result, the fringe capacitance between the edge of the conductor and the underlying ground plane increases, as well as the capacitance due to coupling between adjacent lines. The use of a low temperature, undoped, non-conducting, low dielectric constant oxide in combination with a silicon nitride layer between the metal and ground minimizes this capacitance.

Although the invention has been described in terms of embodiments, this description should not be construed as limiting the invention. From the above explanation,
Various modifications of this embodiment, as well as other embodiments of the invention, will readily occur to those skilled in the art. It is therefore intended that the appended claims cover all such modifications that fall within the scope of the invention.

In connection with the above description, the following sections are further disclosed.

(1) LS I or G; tVLs In a method of making a bipolar transistor with a 17D process, a buried DU having a first conductivity type is embedded in a semiconductor substrate having a second conductivity type.
forming a DUF collector, growing an epitaxial layer having a first conductivity type over the DtJF collector, and forming a trench at least partially surrounding the transistor and passing through the DUF collector; forming a separation means around the epitaxial layer, forming an intrinsic base region having the second conductivity type in the epitaxial layer; forming an emitter in the intrinsic base region adjacent to the extrinsic base region having the first conductivity type extending to the buried DUF collector in the epitaxial layer; A method comprising forming a collector contact region.

(2) In the method described in item (1), the trench surrounds the transistor region.

(3) In the method described in item (2), forming a polysilicon contact implanted with fast-diffusing impurities on the emitter and collector contact regions in the epitaxial layer,
The polysilicon contact is heated to drive the fast-diffusing impurity into the epitaxial layer to form an emitter of the first conductivity type and to drive the fast-diffusing impurity into the collector contact (1[ A method that includes pushing the

(4) In the method described in paragraph (2), first deposit and pattern seven photoresist layers on the epitaxial layer to form a base region and deposit a second conductivity type in the base region. depositing a second 7-photoresist layer and defining a pattern of the second layer, the second 7-photoresist layer having an opening defined by the first photoresist layer; defining one edge of the smaller opening, with the first seven photoresist layers defining the remainder of the smaller opening;
said base is formed by implanting an impurity having a second conductivity type to form an extrinsic base;
How the rest of the implant area constitutes the extrinsic base.

(5) The method described in paragraph (3), which includes heating the substrate to anneal the w1 implant flaws before depositing the polysilicon.

(6) The method described in item (3), including performing deep collector implantation of a fast-diffusing impurity having a first conductivity type into the collector contact region prior to the heating step. Method.

(7) In the method described in paragraph (2), growing a thin oxide on the epitaxial layer and performing intrinsic and extrinsic based implants through the oxide to eliminate any dropouts. A method that involves achieving a shallow drive that is almost non-existent.

(8) In the method described in paragraph (6), the DU
A method in which the impurity implanted into the F collector is of a type that diffuses slowly.

(9) In the method described in paragraph (2), the method described in the first
The second conductivity type impurity is N-type, and the second conductivity type impurity is P-type.

(10) In the method described in item (8), the slow-diffusing impurity is antimony and the fast-diffusing impurity is phosphorus.

(11) The method described in item (8), wherein the sheet resistance value of the extrinsic base after implantation is 600 to 800 ohms/square.

(12) The method of paragraph (4), wherein the width of the trench is less than about 2.5 microns.

(13) The method of paragraph (7), wherein the extrinsic base has a depth of less than about 5,000 microns and the epitaxial layer has a thickness of less than about 1.5 microns.

(14) In the method described in paragraph (4), the DUF
A method in which the zone depth is less than about 3.5 microns and the sheet resistance is less than or equal to about 25 ohms/square.

(15) In the method described in item (4), the sheet resistance of the extrinsic base region in the epitaxial layer is about 10
A method that is 0 ohms/square.

(16) The method described in item (7), wherein the thickness of the oxide is within the range of 1.000 to 1.500 mm.

(17) The method of paragraph (4) comprising depositing a passivation layer over the thin oxide.

(18) The method described in item (6), wherein the collector implant energy is within a range of 100 to 120 keV.

(19) The method described in item (7), wherein the base is implanted with boron.

(20) In the method described in item (17) II, the surface passivation layer is silicon nitride.

(21) In the method described in paragraph (7), depositing a high temperature metal on the emitter and collector of the polysilicon and on a base contact region overlying the extrinsic base region, A method comprising sintering to form a silicide wherever the metal contacts silicon and removing the metal elsewhere.

(22) The method described in item (21), wherein the high temperature metal is platinum.

(23) In the method described in paragraph (4), after the deposition, doping and patterning of the polysilicon, a thick oxide having a relatively planar top surface is formed by isomorphic low pressure chemical vapor deposition. depositing a resist layer by a spin deposition method to create a planar top surface, and etching back the resist and oxide top surface using an etchant that etches both the resist and oxide at approximately the same rate. exposing emitter, collector and base contacts of the polysilicon.

(24) The method of paragraph (7), wherein the extrinsic base is adjacent to the N-type epitaxial silicon, and a base contact region is located between a portion of the extrinsic base and the N-type epitaxial silicon. A method that includes both parts of epitaxial silicon.

(25) In the method described in item (9), the step of forming the isolation means includes etching a deep trench pattern passing through the epitaxial layer and the buried DUF collector, and etching the bottom of the etched opening. A method comprising implanting and diffusing a P-doped impurity into a channel stopper region located in a channel stop region, growing a thin oxide layer over the sidewalls and bottom of the trench, and filling the trench with polysilicon.

(2G) In a method of making a bipolar transistor using an LSI or VLSI process, an embedded DUF having a first conductivity type is placed on the surface of a semiconductor substrate having a second conductivity type.
forming a collector, growing an epitaxial silicon layer of a first conductivity type on top of the DUF collector, forming isolation means around the transistor region, first depositing a layer of polysilicon on the emitter and collector contacts m 1ffl; depositing a silicon contact, doping and patterning it with a fast-diffusing impurity having said first conductivity type, and heating the mock polysilicon and epitaxial layer to drive the fast-diffusing impurity into the emitter and collector contact regions; By this,
the first layer in the epitaxial layer of the transistor region;
forming emitter and collector contact regions having a conductivity type of the first a-conductivity type, and forming a collector contact region having the first a-conductivity type in an epitaxial layer of the transistor region up to the buried DUF collector.

(27) The method described in item (2G), wherein the isolation means includes a trench surrounding the transistor region and entering the DUF collector region.

(28) In the method described in paragraph (26), the base is formed by first depositing and patterning a photoresist layer on the epitaxial layer to open a base region and forming a photoresist layer in the base region. implanting an impurity having a conductivity type of 2 and depositing a second photoresist layer, the second photoresist layer covering one edge of the opening that is smaller than the width defined by the first photoresist layer; patterning the second layer and implanting an impurity of the second conductivity type to form an extrinsic base such that the first photoresist layer defines the remainder of the smaller opening; and the remainder of the first implant region forming an intrinsic base.

(29) In the method described in item (27), the substrate is heated to anneal implant damage before depositing the polysilicon.

(30) In the method described in item (26), before depositing the polysilicon, deep collector implantation of a fast-diffusing impurity having a first conductivity type is performed in the collector contact region. A method that involves annealing the material.

(31) In the method described in item (26), an oxide is grown on the epitaxial layer, and a base is implanted through the oxide to perform a shallow implant with almost no failure. How to achieve.

(32) In the method described in paragraph (26), the DU
A method in which the impurity implanted into the F collector is of a slow whl type.

(33) The method of paragraph (26), including heating the substrate to anneal implant damage prior to depositing the polysilicon.

(34) The method described in item (33), including performing deep collector implantation of a fast-diffusing impurity having a first conductivity type into the collector contact region before the heating step. .

(35) In the method described in paragraph (26), growing a thin oxide on the epitaxial layer and performing intrinsic and extrinsic base implants through the oxide, A method including achieving a shallow drive with no dropouts.

(36) In the method described in paragraph (26), the DU
A method in which the impurity implanted into the F collector is of a type that diffuses slowly.

(37) In the method described in paragraph (26), the first
The second conductivity type impurity is N-type, and the second conductivity type impurity is P-type.

(38) The method described in item (36), wherein the slow-diffusing impurity is antimony and the fast-diffusing impurity is antimony.

(39) The method described in item (35), wherein the sheet resistance of the intrinsic base after implantation is within the range of 600 to 800 ohms/square.

(40) The method of item (35), wherein the depth of the intrinsic base is less than about 1.5 microns.

(41) In the method described in paragraph (36), the DU
A method in which the depth of the F region is less than about 3.5 microns and the sheet resistance is less than or equal to about 25 ohms/square.

(42) In the method described in item (35), the sheet resistance of the extrinsic base region of the epitaxial layer is about 10
A method that is 0 ohms/square.

(43) The method described in item (35), wherein the thickness of the oxide is within the range of 1.000 to 1,500.

(44) The method of paragraph (26) comprising depositing a passivation layer over the thin oxide.

(45) The method described in item (38), wherein the collector implant energy is within a range of 100 to 120 keV.

(46) The method described in item (35), wherein the base is implanted with boron.

(47) The method described in item (44), wherein the surface passivation layer is silicon nitride.

(48) In the method of paragraph (35), depositing a high temperature metal over the emitter and collector of the polysilicon and over the base contact region overlying the extrinsic base region; sintering the hot metal to form a silicide where it comes into contact with the metal and removing the metal elsewhere.

(49) The method described in item (48), wherein the high temperature metal is platinum.

(50) In the method described in paragraph (26), after deposition, doping, and buttering of the polysilicon, a low-pressure chemical reaction vapor phase is performed to conformally form a thick oxide having a relatively planar upper surface. depositing by growth, etching back the top surface, and etching the oxide;
A method comprising exposing emitter, collector and base contacts of the polysilicon.

(51) The method of paragraph (35), wherein the extrinsic base is adjacent to N-type epitaxial silicon, and the base contact region is located between a portion of the extrinsic base and a portion of the epitaxial region. contains both,
A method of forming a Schottky diode between the collector and the base.

(52) In the method described in item (26), the step of forming the trench includes determining and etching a pattern of a deep trench opening that penetrates into the epitaxial layer and the buried DLJF; A method comprising implanting and diffusing a channel stopper region at the bottom, growing a thin oxide layer on the walls of the trench, and depositing polysilicon into the trench to fill the trench.

(53) In a bipolar transistor cell formed on a semiconductor substrate having a second conductivity type, a buried DUF collector having a first conductivity type in the substrate;
an epitaxial layer having a first conductivity type overlapping the F collector; isolation means surrounding a transistor region and including a trench at least partially surrounding the transistor region and into the DtJF collector; A bipolar transistor having emitter and base regions having first and second 81M types and a collector contact region having the first conductivity type within the epitaxial layer and extending down to the buried DLJF collector. cell.

(54) In the bipolar transistor cell described in item (53), the first conductivity type impurity is N- type and the second conductivity type impurity is P- type.・Transistor cell.

(55) The bipolar transistor cell according to item (53), wherein the trench surrounds the transistor region.

(56) The bipolar transistor cell according to item (55), wherein the sidewalls and bottom of the trench have a thin oxide layer.

(57) In the bipolar transistor cell described in item (55), the trench has a width of 1.5 to 2.
Bipolar transistors in the 0 micron range
cell.

(58) In the bipolar transistor cell described in item (531), the emitter is formed by diffusing the first impurity having one electric type into the P-type intrinsic base. transistor cell.

(59) The bipolar transistor cell according to item (53), comprising an oxide layer overlapping the epitaxial layer and a surface passivation layer overlapping the oxide layer.

(60) The bipolar transistor cell described in item (53), wherein the buried DUF is formed by diffusing antimony as an impurity into the substrate.

(61) In the bipolar transistor cell of paragraph (60), the collector contact is formed by diffusing into the epitaxial layer a deep phosphorus implant extending from the surface to the DUF region. bipolar transistor cell.

(62) In the bipolar transistor cell described in item (60), the thickness of the DUF region is 3 to 3.
Within the range of 5 microns and sheet resistance of 15 to 2
Bipolar transistor cell in the range of 5 ohms/square.

(63) The bipolar transistor cell of paragraph (59), wherein the oxide layer overlying the epitaxial layer is within the range of about i,ooo to 1.500.

(64) In the bipolar transistor cell described in paragraph (53), the thickness of the intrinsic base is approximately 3.00 mm.
A bipolar transistor cell having a sheet resistance in the range of 0 to 4,000 ohms and less than about 1,000 ohms/sware.

(65) The bipolar transistor cell described in paragraph (53), wherein the thickness of the P-decade extrinsic base region is within the range of approximately 4,000 to 5,000 nm. cell.

(66) The bipolar transistor cell of paragraph (60), wherein the intrinsic base implant is boron.

(67) In the bipolar transistor cell according to paragraph (53), the emitter and collector contact regions absorb phosphorus from a phosphorous-doped polysilicon layer into the intrinsic base and collector contact regions, respectively. bipolar transistor cell formed by diffusion into

(68) The bipolar transistor cell described in item (55), wherein the trench is filled with polysilicon.

(69) The bipolar transistor cell described in item (56), wherein the trench is filled with polysilicon.

(70) A transistor cell formed within a transistor region of a semiconductor substrate, including a trench that at least partially surrounds the transistor region.

(71) The transistor cell according to item (70), wherein the trench surrounds a transistor region.

(72) The transistor cell of paragraph (71), wherein the trench has a thin oxide coating on its walls and is filled with polysilicon.

(73) The transistor cell described in item (12), which has a channel stopper region formed below the trench.

(74) The transistor cell described in item (70), in which the corners of the trench are angled so that the trench has a substantially uniform width.

[Brief explanation of drawings]

1-22 are greatly enlarged side cross-sectional views of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, illustrating the device structure at each stage of manufacture. FIG. 23 is a side cross-sectional view of one cell of the chip of FIGS. 1-21 during the final manufacturing step using a thick conformal deposit of silicon dioxide; FIGS.
FIG. 3 is a plan view of the cell shown in the figure.

Claims (1)

[Claims] (1) In a method of manufacturing a bipolar transistor using an LSI or VLSI process, a buried collector having a first conductivity type is formed in a semiconductor substrate having a second conductivity type, and a second conductivity type is placed on the buried collector. forming an isolation means around the transistor region including growing an epitaxial layer having a conductivity type of 1 and forming a trench at least partially surrounding the transistor and passing through the buried collector; forming an intrinsic base region having the second conductivity type within the intrinsic base region, forming an extrinsic base region having the second conductivity type self-aligned with an edge of the intrinsic base; forming an emitter in the intrinsic base region adjacent to the intrinsic base region, and forming a collector contact region with the first conductivity type in the epitaxial layer extending to the buried collector.