JPH08102469A - Bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high-speed switching by growing an epitaxial layer having a first conductivity type on the embedded-region collector provided with the first conductivity type, and forming a separating means around a transistor region. SOLUTION: A shallow emitter 49 is formed in a base region 48 by diffusion from a phosphorus-doped polysilicon emitter 64. A deep N<+> -type collector contact 62 is formed in an epitaxial region 14 and brought into contact with a DUF region 12, acting as an embedded collector. A metallic contact 78 is formed on the surface and insulated from the epitaxial region 14 by a thermally grown oxide 20a and a nitride layer overlapped thereon. Thus, the electrostatic capacity of a conductor is decreased. In this way, the filling density can be enhanced, and doping of an active base can be strengthened. Therefore, the delay (or switching time) of the gate can be made further smaller.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fabrication of bipolar transistors by LSI or VLSI technology which feature shallow junctions for high switching speeds and which allow high packing densities.

[0002]

2. Description of the Related Art There is a strong demand for forming a bipolar transistor in a VLSI process capable of increasing packing density and switching at high speed. 1 proposed to achieve these goals
Two processes are polysilicon self-alignment or PS
It is called A. However, the PSA process uses complex etching steps and double polysilicon sequences, which makes the overall flow difficult to manufacture and achievable yields are low. Another way to achieve high speed circuits is through sidewall-based contact structures. Again, the structure is difficult to manufacture due to the large number of photomechanical levels and the complexity of the process. This other method utilizes the basic bipolar transistor contour with the addition of trench isolation rather than oxide isolation. However, such a device could not achieve the maximum speed.

[0003]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a bipolar transistor cell formed by a VLSI process which has improved switching speed and high packing density. Is to provide.

The present invention provides a method of making bipolar transistors in an LSI or VLSI process. This method forms a buried region (DUF) collector having a first conductivity type, growing an epitaxial layer having a first conductivity type on the DUF collector, and forming isolation means around the transistor region. Including that. The transistor region includes a trench that at least partially surrounds the transistor region and extends into the DUF collector. Emitters and base regions having first and second conductivity types are formed in the epitaxial layer. A collector contact region having a first conductivity type is formed in the epitaxial layer and extends to the buried DUF collector.

A trench preferably surrounds the transistor region. Coat the sidewalls of the trench with oxide,
After that, it is filled with polysilicon. By using only a thin oxide coating and polysilicon, the problems inherent in oxide trenches due to the different expansion coefficients of oxide and silicon are avoided. A channel stopper having a second conductivity type is implanted below the trench before it is filled with undoped polysilicon. An oxide layer is grown on the epitaxial layer and then a resistor and base are implanted through the oxide into the epitaxial region. The collector region is directly driven deep into the epitaxial region. By heating the device, the implant damage is annealed. Thereafter, doped polysilicon emitter and collector contacts are formed. The device is then heated to drive the impurities in the polysilicon into the base and collector regions to form emitter regions in the base. Next, metal contacts and interconnects are formed.

The impurity of the first conductivity type is N-type, and the impurity of the second
It is preferable that the conductivity type of P is P-type. More specifically, the slow-diffusing impurity is antimony, and the fast-diffusing impurity is phosphorus. By using a thin oxide of 1,000 to 1,500Å, low implantation energies can be used to form the base, resulting in minimal degradation and a shallow base region. By using boron as an impurity and an implant energy of 60 keV or less, a base depth of less than 5,000Å is achieved.

By strengthening the doping of the base impurities, it is possible to reduce the resistance value of the base and the delay of the base. By achieving a shallow junction, the epitaxial layer can be narrowed to 1.0 to 1.4 microns, thus lowering the collector resistance.

By forming trenches about 2 microns wide, the device can be integrated on the chip about an order of magnitude more densely than conventional bipolar devices. By utilizing the deep collector implant, the long anneal times associated with standard deep collectors are avoided, and consequently the boron diffusion distribution is disturbed.

By choosing antimony as the dopant for the DUF region, updiffusion from the buried collector is minimized, which helps to achieve a narrow epitaxial layer. While the novel features believed characteristic of the invention are set forth in the appended claims, the invention itself as well as other features and advantages will be best understood from the following detailed description of the drawings.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIGS. 23 and 24 show one of many bipolar transistors formed on each of a number of silicon bars. Formed from bars or silicon slices. In the preferred embodiment of the present invention, each transistor is comprised of a P-type single crystal silicon substrate 10 and has an N-type antimony implanted DUF region 12 therein.
Extend into the slice to a thickness of 3 to 3.5 microns. N-type epitaxial layer 14 is 1.0 to 1.4
Deposited on the DUF region 12 to a micron thickness. Trench 18 filled with polysilicon is substrate 1
0 and the epitaxial layer 14 are divided into a number of regions where bipolar transistors are formed. Each transistor has a heavily doped shallow base region 48 extending downwardly by only 3,000 to 4,000 Å, which is a heavily doped P + region 58 in the form of a rectangular strip having a rectangular volume in the center of the epitaxial region 14.
Is in contact with the surface. A metal contact 78 contacts both the P + type region and the epitaxial region 14 to provide a P + type region 58.
A clamping Schottky diode is formed between the epitaxial region 14 and the epitaxial region 14. The platinum silicide 72 is connected to the metal contact 78, the silicon 14, and the polysilicon emitter 64.
And between the collector contact 66 to improve ohmic contact. Non-clamping device has P + shaped area 58
Aside from extending completely below the base contact,
It is the same as FIG.

A shallow emitter 49, about 1,000 to 2,000 Å deep, is formed in the base region 48 by diffusion from a phosphorus-doped polysilicon emitter 64. A deep N + type collector contact 62 is formed in the epitaxial region 14 and acts as a buried collector D.
Contact the UF area 12. A metal contact 78 is formed on the surface and is insulated from the epitaxial region 14 by the thermally grown oxide 20a and the overlying nitride layer 52,
The capacitance of the conductor is reduced. Optionally, a chemical reaction vapor deposition oxide coating 80 may be used to further reduce capacitance. This coating provides a planarization effect for the first level interconnect. 1 and 2
The P-type silicon substrate 10 has an annealed depth of 3 to 3.5 microns and a final sheet resistance of 1.
Antimony can be single-sided so as to be 5 to 20 ohms / square. Since antimony diffuses much slower into silicon than other types of donor impurities such as phosphorus or arsenic, it has much less updiffusion into the overlying epitaxial layer. Next, as shown in FIG. 3, an N-type epitaxial layer 14 is applied to the antimony-implanted DUF region 12 under reduced pressure by 1.0 to 1.4.
Although deposited to a micron thickness, its resistivity is relevant for circuit applications. Epitaxial layer 14 of this thickness
Requires approximately 20% less than the thickness of the epitaxial layer used in conventional technology and requires shallow emitter and base regions.

Next, silicon dioxide layer 16 is deposited to a thickness of about 1.0 to 1.5 microns. A layer of photoresist (not shown) is then deposited over the silicon dioxide, exposed to UV light through a mask, and the exposed portions are removed, leaving a number of spaced trench regions.
Etch the trench region 18 by first depositing photoresist (not shown), defining its pattern, etching the deposited oxide, and then etching the exposed silicon to form 1.5 to A deep trench with a width of 2.0 microns extends below the DUF region 12.

As shown in FIG. 4, sidewall oxide 20 is grown on the walls of trench 18 by placing the cell in an atmosphere of steam at a temperature of about 1,000 ° C. for about 15 minutes. Then, at a concentration of energy and about 1 × 10 ¹⁴ atoms / cm ² of 40 to 60 keV, the directing implantation of boron for channel stopper against the trench 18, P + form channels below each trench 18 Forming a stopper region 19 so that no inversion layer is formed around the trench oxide sidewall 20. As shown in FIG. 5, etching removes the silicon dioxide layer 16 on the surface of the N− type epitaxial layer 14 and the silicon dioxide layer on the trench sidewalls. A new sidewall oxide layer is grown as shown in FIG.

The trench 18 is then filled with a polysilicon deposit 22 and a planar photoresist layer 24 is deposited over this layer, as shown in FIG. The photoresist 24 is chosen to have approximately the same etch rate as the underlying polysilicon. Therefore, when the photoresist and polysilicon are etched down to the oxide surface, a flat oxide surface 20 as seen in FIG. 8 is obtained. By using this trench as an isolation region, oxide ingress into the active device region, which would occur with conventional oxide isolation devices, is avoided and packing density can be significantly increased. In oxide isolation, current design rules require that in order to achieve an acceptable breakdown voltage between isolated regions,
It is necessary to have a 8 to 10 micron separation between the transistors, but in a trench filled with polysilicon, the width of the trench is limited to 1.5 to 2 microns.

Referring to FIG. 9, a silicon nitride layer 30 is formed on the oxide surface by low pressure chemical vapor deposition. As seen in FIG. 10, a photoresist layer 32 is deposited over the nitride 30, then patterned and the exposed isolation regions 34 are etched to remove the nitride 3
0 and oxide 20 are removed. After this, the entire slice is exposed to a high pressure oxidizing atmosphere at about 900 ° C. for about 2 hours. During this oxidation, silicon is consumed, thus forming a relatively thick oxide isolation region 36, as seen in FIG.

Next, as seen in FIG. 12, oxide layer 20.
Together with it, the nitride is removed by etching. Then, a more uniform and more uniform oxide layer 20a is thermally grown. Using a photoresist layer 38 as shown in FIG.
Define a pattern of openings for resistor / base implants. This implantation is performed at an energy of 40 to 60 keV and at a concentration suitable for obtaining the sheet resistance value required by the application of the device. Resistor implants (not shown) are made in different discrete regions bounded by different pairs of trenches. Conventional processing is used to form the elongated P-shaped implanted resistor body and the P + shaped implanted regions at its ends. The openings 40, 42 are defined by the photoresist layer 38 and are shown in FIG. A photoresist layer is then deposited over the first resist and exposed through a mask that allows the resist to cover the resistor body (not shown). After removing the exposed photoresist, the surface is bombarded with boron for an intrinsic base. Once again the photoresist layer 44
To form regions with the photoresist level 38, the regions 42, 4 as seen in FIG.
Open 6 The implantation of boron for the extrinsic base results in the P + type region 58 shown in FIG. This extends about 4,000 to 5,000 liters below the surface of the silicon,
It has a sheet resistance of 80 to 100 ohms / square. P-shaped region 48 obtained by exogenous implantation
But about 3,000 to 4,000 Å from the surface of silicon
It extends downward. The base region 48 has a sheet resistance of 6
Dope strongly to the point of 00 to 800 ohms / square. This high level of doping of the base reduces the resistance of the base and thus reduces gate delay and switching time. All junction depths and sheet resistances mentioned above are final values of the process.

Strip photoresist 38, resistor block (not shown) and photoresist 44 and use low pressure chemical vapor deposition (LPCVD) to surface inactivate over the surface as shown in FIG. The nitrided nitride layer 52 is formed. Thermal oxide 20 and LPCVD nitride 52 help minimize the conductor's capacitance to ground.
Another photoresist layer 54 is added to the nitride 52 and oxide 20.
Deposit on top of a and pattern and etch to expose region 56 for collector and region 60 for emitter. The photoresist 42 is used as an implant blocking layer over the emitter and is patterned by conventional means. Deep phosphorus implantation is performed at a concentration in the range of 5 × 10 ^{15 to} 3 × 10 ¹⁶ atoms / cm ² with an energy of 100 to 120 keV.

As shown in FIG. 17, a photoresist layer 42
Except for the emitter contact region 60. A short base anneal is performed to drive the collector and anneal the implant damage. Then polysilicon 5
Deposit in 6, 60 and on nitride surface 52. Energy in the range of 80 to 100 keV and 5 ×
Phosphorus is implanted into polysilicon at a concentration of 10 ^{15 to} 2 × 10 ¹⁶ atoms / cm ² . Thereafter, a polysilicon pattern is defined and etched to form emitter 64 and collector contact 66, as shown in FIG. Annealing of the emitter at 900 ° C. is performed to drive the phosphorous downward from the emitter polysilicon to the emitter region 48. This anneal also drives phosphorus from the collector polysilicon 66 into the collector region 62. Due to the heavily doped shallow base region 48, it is necessary to use an efficient polysilicon diffused emitter 64. In devices with shallow emitters, surface recombination at the metal contact surface reduces current gain (base current increases significantly for small changes in emitter junction depth,
The collector current remains flat). This small gain is due to the large variation in crystal properties at the interface and the depth of the emitter junction, which is shallower than the diffusion length of holes in the emitter, in the area of the emitter contact. This is because the recombination becomes very serious. Since only the polysilicon is implanted and it is used as a diffusion source for the monocrystalline portion of the emitter, the polysilicon does not result in unwanted implant damage to the monocrystalline silicon substrate. Therefore, in the forward implantation, almost ideal small current performance is obtained, and the insulation breakdown characteristic is improved by the emitter distribution of phosphorus. Therefore, in the normal operating range of bipolar transistors,
The current gain is almost independent of the current level.

Another deposit of photoresist 68 is required to form contacts and leads, and patterning and etching to form open areas 69 as shown in FIG. Next, a platinum layer 70 is formed on the surface of the opening region 69, the polysilicon contacts 64 and 66, and the nitride layer 52.
Is sputtered. Platinum is sintered to form platinum silicide 72 wherever platinum and silicon are in contact, as shown in FIGS. 20 and 21, to remove unsintered platinum. Metal layer 7 on the surface
6 is deposited and patterned using photoresist to etch, leaving the structure shown in FIG. The platinum silicide lowers the ohmic contact resistance between the silicon and the corresponding metal contact. The rest of the process is standard metal manufacturing.

Optionally, as shown in FIG. 23, a low temperature chemical vapor deposition method can deposit a 10,000 Å thick silicon dioxide isomorphic layer 80. The thickness of layer 80 results in a relatively planar surface. This silicon dioxide layer is etched back above the polysilicon to about 2,000 Å by the resist etch back method, making its top surface even planar. Contacts are made to the emitter, base and collector and metal 78 is deposited as shown to define the pattern. While achieving the required improved alignment for the initial metal level,
The capacitance of the interconnect is reduced, improving reliability and planarization. The trench structure seen in the base region of FIG. 24 has walls on both the outer 84 and inner 86, 4 on each side.
It is angled at 5 ° to keep the width at the corners constant and to avoid creating voids in the polysilicon used to fill the trench. As shown in FIG. 25, 2
If two bipolar transistors 88, 90 are to be placed next to each other, the trench 18 is patterned with notches 92.

By using a shallow junction, a thin epitaxial layer can be used without noticeably increasing the collector-base capacitance. The thin epitaxial deposit lowers the resistance of the collector and reduces charge storage under the active base. The use of a deep base implant followed by a short base anneal reduces the collector resistance to the extent possible by the usual means of phosphorus-oxychloride diffusion, yet gives better control over the diffusion profile. A method is obtained. By using antimony, which diffuses much more slowly into silicon than other impurities such as phosphorus, the buried collector,
That is, the degree of upward diffusion of the DUF region 14 is limited, thus allowing a thinner epitaxial layer 12. For conventional oxide isolation, current design rules are 8 microns due to breakdown voltage requirements. In the present invention, 2
By filling the narrow micron-wide trench with polysilicon, the packing density can be increased by an order of magnitude more than is possible with normal oxidation isolation.

Utilizing a highly efficient polysilicon diffused emitter allows for enhanced active base doping. Heavy doping of the base results in a lower resistance of the base and thus a lower gate delay (or switching time).

The improved packing density results in shorter metal-to-metal spacing, resulting in fringe capacitance between the conductor edges and the underlying ground plane, as well as static due to coupling between adjacent lines. The electric capacity increases. This capacitance is minimized by using an undoped, non-conductive, low dielectric constant, low temperature processed oxide in combination with a silicon nitride layer between the metal and ground.

Although the present invention has been described in terms of embodiments, this description should not be construed as limiting the invention. From the above description, those skilled in the art can easily think of various modifications of the present embodiment and other embodiments of the present invention. Therefore, it is to be understood that the appended claims are intended to cover all such modifications as fall within the scope of the invention. The following section is further disclosed in connection with the above description.

(1) In a method of manufacturing a bipolar transistor by an LSI or VLSI process, an embedded D having a first conductivity type is embedded in a semiconductor substrate having a second conductivity type.
Forming a UF collector, growing an epitaxial layer having a first conductivity type on the DUF collector, at least partially surrounding the transistor and forming a trench through the DUF collector; Isolation means around the second conductive layer, an intrinsic base region having the second conductivity type is formed in the epitaxial layer, and an edge of the intrinsic base and the second conductive layer that is a self-alignment line in the intrinsic base region. Forming an extrinsic base region having a type, forming an emitter in the intrinsic base region adjacent to the extrinsic base region, and having the first conductivity type extending in the epitaxial layer to the buried DUF collector. A method comprising forming a collector contact region.

(2) The method described in the item (1), wherein the trench surrounds the transistor region.

(3) In the method described in the item (2), a polysilicon contact in which an impurity having a high diffusion rate is implanted is formed on the emitter and collector contact regions in the epitaxial layer, and the polysilicon contact is formed. Heating the contact to drive the rapidly diffusing impurities into the epitaxial layer to form an emitter having the first conductivity type and to drive the first conductivity type impurity into the collector contact region. How to include.

(4) In the method described in paragraph (2), a photoresist layer is first deposited on the epitaxial layer to define a pattern, a base region is opened, and a second region is formed in the base region. Of an impurity having a conductivity type of 2 to deposit a second photoresist layer to define a pattern of the second photoresist layer, the second photoresist layer being defined by an opening defined by the first photoresist layer. Defining one edge of the smaller opening and allowing the first photoresist layer to define the remainder of the smaller opening, implanting impurities of the second conductivity type to implant the extrinsic base. Forming to form the base and the remainder of the first implant region constitutes an extrinsic base.

(5) The method described in paragraph (3), which comprises heating the substrate to anneal the implant damage prior to depositing the polysilicon.

(6) In the method described in the item (3), prior to the heating step, deep collector implantation of a fast-diffusing impurity having the first conductivity type is performed on the collector contact region. A method that includes that.

(7) In the method described in the paragraph (2), a thin oxide is grown on the epitaxial layer, and intrinsic and extrinsic bases are implanted through the oxide to cause a defect. A method that includes achieving a shallow implant with little to do.

(8) The method described in the item (6), wherein the impurities implanted into the DUF collector are of a type in which diffusion is slow.

(9) The method according to item (2), wherein the first conductivity type impurity is N-type and the second conductivity type impurity is P-type.

(10) The method described in the item (8), wherein the slow-diffusing impurity is antimony and the fast-diffusing impurity is phosphorus.

(11) In the method described in (8), the sheet resistance value of the extrinsic base after implantation is 60.
The method is from 0 to 800 ohms / square.

(12) The method described in paragraph (4), wherein the trench width is less than about 2.5 microns.

(13) In the method described in paragraph (7), the depth of the extrinsic base is less than about 5,000Å and the thickness of the epitaxial layer is less than about 1.5 microns. Method.

(14) The method described in paragraph (4), wherein the depth of the DUF region is less than about 3.5 microns and the sheet resistance is about 25 ohms / square or less.

(15) The method described in paragraph (4), wherein the sheet resistance of the extrinsic base region in the epitaxial layer is about 100 ohms / square.

(16) The method according to the item (7), wherein the thickness of the oxide is in the range of 1,000 to 1,500Å.

(17) The method described in paragraph (4), which comprises depositing a passivation layer over the thin oxide.

(18) In the method described in the item (6), the energy for implanting the collector is 100 to 120 k.
A method within the range of eV.

(19) The method described in (7), wherein the base is implanted with boron.

(20) The method described in (17) above, wherein the surface passivation layer is silicon nitride.

(21) In the method described in paragraph (7), a high temperature metal is deposited on the polysilicon emitter and collector and on the base contact region overlapping the extrinsic base region, and A method comprising sintering a hot metal to form a silicide wherever the metal contacts silicon and removing the metal elsewhere.

(22) The method described in the paragraph (21), wherein the high temperature metal is platinum.

(23) In the method described in the paragraph (4), after depositing, doping and patterning the polysilicon, a thick oxide having a relatively flat upper surface is subjected to an isomorphic low pressure chemical reaction. The top surface of the resist and oxide is deposited by vapor deposition, the resist layer is deposited by spin deposition to create a planar top surface, and an etchant that etches both the resist and oxide at about the same rate. Etching back to expose the polysilicon emitter, collector and base contacts.

(24) In the method described in paragraph (7), the extrinsic base is adjacent to the N-type epitaxial silicon and the base contact region is a portion of the extrinsic base and the N-type epitaxial silicon. A method including both a portion of -type epitaxial silicon.

(25) In the method described in paragraph (9), the step of forming the isolation means defines and etches a pattern of deep trenches passing through the epitaxial layer and the buried DUF collector. Implanting and diffusing P + type impurities into a channel stopper region located at the bottom of the opening, growing a thin oxide layer on the sidewalls and bottom of the trench, and filling the trench with polysilicon. .

(26) In a method of manufacturing a bipolar transistor by an LSI or VLSI process, a buried DUF collector having a first conductivity type is formed on a surface of a semiconductor substrate having a second conductivity type, and the DUF collector is formed. First on
Growing an epitaxial silicon layer having a conductivity type of, forming isolation means around the transistor region, first depositing a polysilicon contact over the emitter and collector contact regions, and having the first conductivity type. By doping with fast-diffusing impurities to define a pattern, then heating the polysilicon and the epitaxial layer to drive the fast-diffusing impurities into the emitter and collector contact regions,
In the epitaxial layer of the transistor region, the first
Forming an emitter and collector contact region having a conductivity type of, and forming a collector contact region having the first conductivity type in the epitaxial layer of the transistor region, the collector contact region reaching the buried DUF collector.

(27) The method described in paragraph (26), wherein the isolation means includes a trench that surrounds the transistor region and extends into the DUF collector region.

(28) In the method described in paragraph (26), the base is formed by first depositing a photoresist layer on the epitaxial layer to define a pattern to open a base region, and to form the base region. An impurity having a second conductivity type into the first photoresist layer and depositing a second photoresist layer, the second photoresist layer having a smaller opening than the opening defined by the first photoresist layer. When defining the edge and defining the remainder of the smaller opening by the first photoresist layer, a pattern of the second layer is defined and an impurity having the second conductivity type is implanted to cause extrinsicity. The method wherein the base is formed and the remainder of the first implant region constitutes the intrinsic base.

(29) The method described in the paragraph (27), wherein the substrate is heated to anneal damage due to implantation before depositing the polysilicon.

(30) In the method described in paragraph (26), a deep collector implantation of a fast-diffusing impurity having the first conductivity type is performed in the collector contact region before depositing the polysilicon. And annealing the implant damage.

(31) In the method described in the paragraph (26), an oxide is grown on the epitaxial layer,
A method of implanting a base through the oxide to achieve a nearly imperceptible shallow implant.

(32) The method described in the paragraph (26), wherein the impurities implanted into the DUF collector have a slow diffusion rate.

(33) The method described in paragraph (26), which comprises heating the substrate to anneal the implant damage prior to depositing the polysilicon.

(34) In the method described in (33), prior to the heating step, deep collector implantation of a fast-diffusing impurity having the first conductivity type is performed in the collector contact region. Including the method.

(35) In the method described in the paragraph (26), a thin oxide is grown on the epitaxial layer, and intrinsic and extrinsic base implantation is performed through the oxide. A method that includes achieving a shallow implant with almost no compromise.

(36) The method described in the paragraph (26), wherein the impurities implanted into the DUF collector have a slow diffusion rate.

(37) The method described in (26), wherein the first conductivity type impurity is N-type and the second conductivity type impurity is P-type.

(38) The method described in (36), wherein the slow-diffusing impurity is antimony and the fast-diffusing impurity is phosphorus.

(39) In the method described in (35), the sheet resistance of the intrinsic base after implantation is 600.
To 800 ohms / square.

(40) The method of paragraph (35), wherein the intrinsic base has a depth of less than about 1.5 microns.

(41) The method described in paragraph (36), wherein the depth of the DUF region is less than about 3.5 microns and the sheet resistance is about 25 ohms / square or less.

(42) The method described in paragraph (35), wherein the sheet resistance of the extrinsic base region of the epitaxial layer is about 100 ohms / square.

(43) In the method described in the paragraph (35), the oxide has a thickness of 1,000 to 1,500Å
Method that is within the range of.

(44) The method described in paragraph (26), comprising depositing a passivation layer over the thin oxide.

(45) In the method described in the item (38), the collector implantation energy is 100 to 120.
A method that is within keV.

(46) The method described in (35), wherein the base is implanted with boron.

(47) The method described in (44), wherein the surface passivation layer is silicon nitride.

(48) In the method described in paragraph (35), above the polysilicon emitter and collector,
And depositing a high temperature metal over the base contact region overlying the extrinsic base region, where the metal is in contact with silicon, sintering the high temperature metal to form a silicide, and the metal elsewhere. Including removing.

(49) The method described in (48), wherein the high temperature metal is platinum.

(50) In the method described in paragraph (26), after depositing, doping and patterning the polysilicon, a thick oxide having a relatively flat upper surface is conformally formed by low pressure chemical. A method comprising depositing by reactive vapor deposition, etching back the top surface, and etching the oxide to expose the polysilicon emitter, collector and base contacts.

(51) In the method described in paragraph (35), the extrinsic base is adjacent to the N-type epitaxial silicon, and the base contact region is a portion of the extrinsic base and the epitaxial region. And forming a Schottky diode between the collector and the base.

(52) In the method described in paragraph (26), the step of forming the trench defines and etches a pattern of deep trench openings that penetrate into the epitaxial layer and the buried DUF, Implanting and diffusing a channel stopper region at the bottom of the trench opening to grow a thin oxide layer on the walls of the trench,
Depositing polysilicon in the trench to fill the trench.

(53) In a bipolar transistor cell formed on a semiconductor substrate having a second conductivity type, a buried DUF collector having a first conductivity type in the substrate and a DUF collector Surrounding the transistor region with an overlapping epitaxial layer having a first conductivity type,
Isolation means including a trench at least partially surrounding the transistor region and extending into the DUF collector; emitter and base regions having first and second conductivity types, respectively, in the epitaxial layer; and in the epitaxial layer. A collector contact region having the first conductivity type extending down to the buried DUF collector.

(54) In the bipolar transistor cell described in the paragraph (53), the first conductivity type impurity is N-type, and the second conductivity type impurity is P-type.
-Type bipolar transistor cell.

(55) The bipolar transistor cell as described in the paragraph (53), wherein the trench surrounds the transistor region.

(56) The bipolar transistor cell as described in paragraph (55), wherein the sidewall and bottom of the trench have a thin oxide layer.

(57) In the bipolar transistor cell described in (55), the width of the trench is in the range of 1.5 to 2.0 microns.
Transistor cell.

(58) In the bipolar transistor cell described in the paragraph (53), the emitter is formed by diffusing the impurity having the first conductivity type into the P-type intrinsic base. Bipolar transistor cell.

(59) The bipolar transistor cell according to item (53), which has an oxide layer overlapping the epitaxial layer and a surface passivation layer overlapping the oxide layer. ·cell.

(60) In the bipolar transistor cell described in (53), the embedded DUF is used.
A bipolar transistor cell formed by diffusing antimony as an impurity into the substrate.

(61) In the bipolar transistor cell described in the paragraph (60), the collector contact diffuses into the epitaxial layer a deep phosphorus implant portion extending from the surface to the DUF region. Formed by a bipolar transistor cell.

(62) In the bipolar transistor cell described in the paragraph (60), the thickness of the DUF region is in the range of 3 to 3.5 μm, and the sheet resistance is 15 to 25 ohms. / Bipolar transistor cell within square.

(63) The bipolar transistor cell according to item (59), wherein the oxide layer overlapping the epitaxial layer is in the range of about 1,000 to 1,500Å. .

(64) In the bipolar transistor cell described in (53), the thickness of the intrinsic base is in the range of about 3,000 to 4,000Å.
A bipolar transistor cell having a sheet resistance of less than about 1,000 ohms / square.

(65) The bipolar transistor cell according to the item (53), wherein the thickness of the P + type extrinsic base region is in the range of about 4,000 to 5,000 Å. ·cell.

(66) The bipolar transistor cell as described in the paragraph (60), wherein the intrinsic base is implanted by boron.

(67) In a bipolar transistor cell as described in paragraph (53), the emitter and collector contact regions contain phosphorus from a polysilicon layer doped with phosphorus, the intrinsic base and the collector, respectively. A bipolar transistor cell formed by diffusing into the contact area.

(68) In the bipolar transistor cell described in the paragraph (55), the trench is filled with polysilicon.
cell.

(69) The bipolar transistor cell described in the paragraph (56), wherein the trench is filled with polysilicon.
cell.

(70) A transistor cell formed in a transistor region of a semiconductor substrate, including a trench that at least partially surrounds the transistor region.

(71) The transistor cell according to the item (70), wherein the trench surrounds the transistor region.

(72) The transistor cell according to paragraph (71), wherein the trench has a thin oxide coating on its walls and is filled with polysilicon.

(73) The transistor cell according to the item (72), which has a channel stopper region formed below the trench.

(74) The transistor cell according to the item (70), wherein the corners of the trench are angled so as to have a substantially uniform trench width.

(75) This bipolar transistor has a buried collector region having a first conductivity type buried in a substrate, an epitaxial layer having a first conductivity type provided on the buried collector region, and an epitaxial layer. And a transistor region isolation means including a trench extending through the buried collector region, an emitter and base region doped with impurities having first and second conductivity types, a collector contact region having the first conductivity type, on the epitaxial layer. An insulating layer provided and an isolation surface passivation layer provided on the insulating layer, and further having polysilicon contacts to the emitter and collector contact regions doped with the same impurities as the emitter region. , This polysilicon contact extends through the insulating layer and the passivation layer, and the corresponding limit of the passivation layer. A thickened insulating layer and a metal conductor.

[Brief description of drawings]

FIG. 1 is a side elevational view of a single cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention in greatly enlarged scale,
The device structure in each manufacturing stage is shown.

FIG. 2 is a side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention in a significantly enlarged manner,
The device structure in each manufacturing stage is shown.

FIG. 3 is a side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention in a significantly enlarged manner;
The device structure in each manufacturing stage is shown.

FIG. 4 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention,
The device structure in each manufacturing stage is shown.

FIG. 5 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention,
The device structure in each manufacturing stage is shown.

FIG. 6 is a side view of a single cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention in a significantly enlarged view,
The device structure in each manufacturing stage is shown.

FIG. 7 is a significantly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention,
The device structure in each manufacturing stage is shown.

FIG. 8 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention,
The device structure in each manufacturing stage is shown.

FIG. 9 is a side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention in a significantly enlarged manner,
The device structure in each manufacturing stage is shown.

FIG. 10 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each manufacturing stage.

FIG. 11 is a significantly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each stage of manufacture.

FIG. 12 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each manufacturing stage.

FIG. 13 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each manufacturing stage.

FIG. 14 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each stage of manufacture.

FIG. 15 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each manufacturing stage.

FIG. 16 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each manufacturing stage.

FIG. 17 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each stage of manufacture.

FIG. 18 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each stage of manufacture.

FIG. 19 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each manufacturing stage.

FIG. 20 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each manufacturing stage.

FIG. 21 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each manufacturing stage.

FIG. 22 is a greatly enlarged side cross-sectional view of one cell of a semiconductor chip made in accordance with a preferred embodiment of the present invention, showing the device structure at each manufacturing stage.

FIG. 23 is a side cross-sectional view of one cell of the chip of FIGS. 1-21 at the last fabrication stage using a thick isomorphic deposit of silicon dioxide.

FIG. 24 is a plan view of the cell shown in FIG. 23.

25 is a plan view of the cell shown in FIG. 23. FIG.

[Explanation of symbols]

 10 substrate 12 DUF region 14 epitaxial layer 18 trench 22 isolation means 30 nitride 36 isolation region 48 P-type region 52 nitride layer 66 collector contact 70 platinum layer 72 platinum silicide 88 bipolar transistor 90 bipolar transistor

[Procedure amendment]

[Submission date] August 23, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

[Title of Invention] Bipolar transistor

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Steve Thomson Bittersweet, Litchimond, Texas, USA 1130 (72) Inventor Harry F. Pang Curtain Lane 1019 (72), Hyuseton, Texas, USA Inventor Douglas P. Beretto 13807 Baytry Drive, Scheugerland, Texas, United States

Claims (1)

[Claims] 1. A bipolar transistor formed on a semiconductor substrate having a second conductivity type, comprising a buried collector region having a first conductivity type embedded in the substrate, wherein the buried A transistor region isolation means having a first conductivity type epitaxial layer overlying the collector region and at least partially surrounding the transistor region and including a trench extending through the epitaxial layer and the buried collector region. , The transistor region includes an emitter and a base region doped with impurities having first and second conductivity types, respectively, in the epitaxial layer, and further extends through the epitaxial layer to the buried collector region and is provided in the transistor region. Has a collector contact region having a first conductivity type and is provided on the epitaxial layer. A polysilicon contact to the emitter and collector contact regions, which is doped with the same impurities as the emitter region, and which has an isolated insulating layer and an isolation surface passivation layer provided on the insulating layer. A polysilicon contact has an enlarged area contact portion that extends through the insulating layer and the passivation layer and over a correspondingly limited area of the passivation layer, and further provided on the surface passivation layer. A separated thicker insulating layer having a substantially flat surface, contacting the enlarged region contact portion of the polysilicon contact, the flat surface and a portion extending through the thickness of the thick insulating layer. The above bipolar transistor having a metal conductor extending through only.