JPH04290273A - Manufacture of silicon nitride capacitor - Google Patents

Abstract

PURPOSE: To provide a method for manufacturing silicon nitride metal-insulator capacitor that can control the thickness of a silicon nitride layer and prevent the under-cut of silicon nitride that may occur during treatment. CONSTITUTION: Pad oxides 13a and 13b are eliminated, regardless of the formation of a semiconductor integrated circuit. That is, before a silicon nitride layer that becomes a capacitor is deposited, the pad oxides are eliminated, and the silicon nitride layer is covered with a half-sacrifice layer of polysilicon for preventing the silicon nitride after deposition from being attacked during a series of treatment processes.

Description

[Detailed description of the invention]

0001

FIELD OF THE INVENTION This invention relates to the field of integrated circuit semiconductor processing, and more particularly to methods and apparatus for forming metal-insulator semiconductor capacitors.

0002

BACKGROUND OF THE INVENTION One typical conventional method of manufacturing metal-insulator semiconductor capacitors is to use two dielectric layers. According to this method, a pad oxide layer is used in conjunction with a silicon nitride layer for the well-known LOCOS (local oxidation of silicon) process in the first part of the process. Thereafter, the silicon nitride layer is stripped and a second silicon nitride layer is deposited. This second silicon nitride layer is used in conjunction with the initial pad oxide layer to form the insulator portion of the metal-insulator semiconductor capacitor. A disadvantage of this method is that both the oxide and nitride layers may be subject to erosion during wafer fabrication. Specifically, the pad oxide is attacked during the initial wet etch of the silicon nitride layer. If the composition of the etching solution is not carefully adjusted,
Undesirable etching of the pad oxide layer will occur. Additionally, the second silicon nitride layer is attacked during the sputter etch prior to platinum deposition.

[0003] In the prior art, additional complications can occur during the removal of pad oxide from areas of an integrated circuit that are not part of a silicon nitride capacitor. Dry etching is not desirable unless a special dry etching process is developed that has very high selectivity for silicon oxide compared to silicon nitride and silicon. A less selective dry etching process can attack the nitride that forms the capacitor. When a wet etch is attempted to remove the pad oxide, the wet etch creates an undercut in the capacitor nitride, resulting in coverage problems for the metallization process.

0004

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for manufacturing metal-insulator semiconductor capacitors without being subject to erosion of the insulator layer.

Another object of the present invention is to fabricate metal-insulator semiconductor capacitors without creating metallization process coverage problems that can occur due to undercut formation of the insulator layer during wet etching of the pad oxide. The purpose is to provide a method. Yet another object of the present invention is to provide a method for manufacturing a metal-insulator semiconductor capacitor with improved reproducibility of the thickness of the insulating layer.

Yet another object of the present invention is to introduce a process modification that does not require reorganization of other parts of the integrated circuit manufacturing process unrelated to the manufacture of metal-insulator semiconductor capacitors. An object of the present invention is to provide a method for manufacturing a semiconductor capacitor.

[0007]

SUMMARY OF THE INVENTION A method of manufacturing a silicon nitride capacitor is disclosed. The process requires removing the pad oxide layer in portions using etching techniques. In conventional techniques, removal of this pad oxide layer is process sensitive.

The present invention allows pad oxide removal to be process independent. As a result, the controllability of the capacitor value is improved. In the present invention, the pad oxide layer is removed prior to depositing the silicon nitride layer that will become the capacitor. The silicon nitride layer is then covered with a semi-sacrificial layer of polysilicon to prevent erosion of the silicon nitride during subsequent processing steps. The polysilicon layer further eliminates the need to wet etch pad oxide areas in parts of the integrated circuit not covered by silicon nitride, thereby eliminating possible metallization process coverage problems due to wet etch of the oxide. This prevents the formation of undercuts in the silicon nitride.

[0009]

EXAMPLE A method of forming a silicon nitride capacitor will be described. In the following description, numerous specific details are set forth, such as conductivity types, dopant types, etc., in order to more fully describe the invention; however, the invention may be practiced without such specific details. It will be obvious to those skilled in the art that In other instances, well-known features may not be described in detail so as not to obscure the present invention.

FIG. 1 is a cross-sectional view of a silicon substrate 10 illustrating the initial processing steps utilized in the present invention. The structure of the present invention is formed on a P-type silicon substrate. The following description shows the formation of a capacitor and collector of an NPN transistor. First, an N+ buried layer 11 is formed in the P-type substrate layer 10. N+ buried layer 11 is typically formed using ion implantation techniques, which may utilize any suitable dopants such as arsenic or antimony. The N+ buried layer 11 forms a "well" that reduces the base-collector resistance.

Although the present invention shows a silicon nitride capacitor formed in combination with an NPN transistor, this is just one example. The present invention is also applicable to forming silicon nitride capacitors without associated transistors. After forming the N+ buried layer 11, an N-type epitaxial layer is deposited over the entire substrate. A thin silicon dioxide layer (approximately 400 angstroms) is formed over the epitaxial layer. This oxide layer is hereinafter referred to as a pad oxide layer. A silicon nitride layer (approximately 1000 angstroms) is then deposited over the silicon dioxide layer. Thereafter, the silicon nitride layer, the silicon dioxide layer, and a portion of the epitaxial layer are etched according to the pattern using photolithography. Next, the localized field oxide 13 (LOCOS) is formed by a thermal oxidation process.
) to form. This field oxide is formed only in areas not covered by silicon nitride. Pad oxide regions 16A and 16B prevent the formation of stress-induced defects during this thermal oxidation. Usually the area around 12A is used to use capacitors,
The area around 12B is used to form a contact to the semiconductor electrode of the capacitor. Second LOCOS
Oxidation leaves regions of nitride only where contacts are to be made to the respective device. Silicon nitride layers 14A and 14B are left in place during the second LOCOS. Photoresist layer 1 on the surface of the field oxide
5, pattern it, and implant N+ phosphorus layers 16A and 16B into the exposed regions of epitaxial layers 12A and 12B. The N+ layer is implanted through the nitride layer and pad oxide layer, forming the N+ capacitor and NPN
Used to form the collector of a transistor.

FIG. 2 illustrates the effects of subsequent conventional processing steps used to form silicon nitride capacitors. Photoresist layer 15 is removed. A diffusion process is then performed to diffuse the implanted phosphorus regions 16A and 16B into the epitaxial layers 12A and 12B to form deep N+ regions 17A and 17B. Region 17A is the bottom electrode of the capacitor, and the surface of region 17B ultimately becomes the contact that electrically connects this electrode to the surface metallization layer. Areas similar to 17B are also N
Functions as a collector for the PN transistor.

Next, when silicon nitride layers 14A and 14B are peeled off, N+ regions 17A and 17 are formed as shown in FIG.
Pad oxide layers 13A and 13B remain on top of B. Next, a new silicon nitride layer 18 is deposited on the surface of substrate 10. The silicon nitride layer is then etched in a pattern such that this thin silicon nitride layer remains only over the capacitor pad oxide region 13A.

Next, as shown in FIG. 5, pad oxide layer 13B is removed from transistor N+ region 17B. Next, referring to FIG. 6, the deep N+ region 17B
A "self-aligned" platinum silicide layer 19 is formed thereon. Thereafter, as shown in FIG. 7, metallized layers 20A and 2
0B is formed and removed according to the pattern. Metallization layer 20A is the metal electrode of the silicon nitride capacitor, and metalization layer 20B forms the contact to the N+ silicon electrode of the capacitor.

A disadvantage of conventional methods of forming metal-insulator semiconductor capacitors is that careful process control must be performed on two different dielectric layers: pad oxide layer 13A and silicon nitride layer 18. It is. When stripping silicon nitride layers 14A and 14B, the pad oxide may be eroded. If a sputter etching step is performed before the deposition of the platinum silicide layer 19,
The silicon nitride layer 18 will be eroded.

Another disadvantage of conventional methods of forming metal-insulator semiconductor capacitors arises from the requirement to remove pad oxide from the emitter and base regions (not shown) of the NPN transistor. This is typically performed after depositing and patterning the thin silicon nitride layer 18 and before depositing the metallization layers 20A and 20B. If a dry etch process is employed to remove this pad oxide, the dry etch process must be performed with very high selectivity in etching silicon dioxide much faster than either silicon nitride or silicon. . Selectivity to silicon nitride is required to prevent erosion of the thin silicon nitride layer 18 for capacitors. High selectivity with respect to silicon is required to prevent excessive erosion of the emitter and base contacts after pad oxide removal. In practice, it is difficult to obtain the required degree of selectivity.

Much higher selectivity can easily be obtained by wet etching the pad oxide. However, wet etching is performed in areas 21A and 21 in FIG.
This results in the formation of an undercut 21 in the thin silicon nitride layer as seen in FIG. This undercut is 21
Areas like A may cause problems with the effective range in the metallization process.

The initial processing steps of the present invention are shown in FIG.
The process is almost the same as that described with reference to FIG. Referring now to FIG. 8, silicon nitride layers 14A and 14B have been stripped from the capacitor and collector contacts, respectively. Pad oxide layers 13A and 13B
is removed by wet etching to expose the underlying implanted silicon contact area as shown in FIG.

Remove photoresist 15 and implant N+
Regions 16A and 16B are diffused to form deep N+ regions as shown in FIG. The resulting deep N
+ Regions 17A and 17B are used as capacitor electrodes and/or collectors. At this point during fabrication, processing of the emitter and base regions of the bipolar transistor begins.

Next, referring to FIG. 11, after stripping off the silicon nitride from all areas of the wafer surface that were covered with the photoresist in FIG. evaporate on top. In the preferred process, since the pad oxide layer has already been removed, the silicon nitride layer 2 of the present invention is removed to obtain the specified capacitance per unit area.
1 is thicker than conventional layer 18. Stripping and redepositing the silicon nitride is necessary because the two layers serve two distinct functions. The original silicon nitride layers 14A and 14B are used as mask layers in the LOCOS oxidation and therefore must be deposited over the pad oxide. A second silicon nitride layer 21 is used as a dielectric in the capacitor, so it is deposited directly above the N+ silicon electrode. Furthermore, FIG. 11 shows that the polysilicon layer 2
2 (~500 angstroms) is shown to prevent erosion of silicon nitride layer 21 during subsequent processing.

Next, according to FIG. 12, polysilicon layer 2
The layers 2 and silicon nitride layer 21 are removed by dry etching according to the pattern so that they remain only in the capacitor region. Next, dry etching is performed to
Remove pad oxide overlying other areas of the PN transistor and other devices (not shown). Here, dry etching is used to prevent undercutting of the silicon nitride of the capacitor. This is to avoid problems with the effective range of the metallization step in subsequent processing steps. Polysilicon layer 22 prevents erosion of capacitor nitride 21 during the pad oxide dry etch. Since a dry etch is used to remove the pad oxide, the undercut problems associated with wet etching are avoided.

Next, a p-type or n-type dopant such as boron, phosphorus, or arsenic is implanted into the polysilicon layer 21, and the dopant is activated by heat treatment to make the polysilicon conductive. The required implantation dose of this dopant must be large enough so that the polysilicon layer has high conductivity and good ohmic contact with the platinum silicide that is subsequently formed. Next, metallization layers 20A and 20B are formed over the capacitor and left in the pattern. that's all,
A method of forming a silicon nitride capacitor has been described.

[Brief explanation of the drawing]

[Figure 1] ~

FIG. 7 is a cross-sectional view of a semiconductor substrate showing conventional processing steps in forming a silicon nitride capacitor.

[Figure 8] ~

FIG. 12 is a cross-sectional view of a substrate illustrating the processing steps of the present invention in forming a silicon nitride capacitor.

[Explanation of symbols]

10 Silicon substrate 11 N+ Buried layers 12A, 12B N-type epitaxial layers 13A, 13
B Pad oxide layer 14A, 14B Silicon nitride layer 15 Photoresist layer 16A, 16B Implanted N+ region 17A, 17B Deep N+ region 19B Self-aligned platinum silicide layer 20A, 20B Metallization layer 21 Silicon nitride layer 22 Polysilicon layer

Claims (4)

[Claims] 1. A method of forming a silicon nitride capacitor as part of a silicon semiconductor wafer manufacturing process, comprising: (a) preparing a P-type silicon substrate; (b)
) forming a localized N-type buried layer on the surface of the silicon substrate; (c) forming an N-type EPI layer covering the surface;
(d) forming a recessed oxide LOCOS isolation portion having at least two openings over the designated localized buried layer region; (e) said recessed oxide LOCOS over the designated localized buried layer region; forming a second LOCOS oxide having regions of nitride and pad oxide where contacts to the semiconductor device are to be formed, including at least a portion of each of the two openings in the isolation portion; (
f) photomasking techniques to prevent implantation into other device contacts through the silicon nitride and pad oxide of the two openings and the silicon nitride and pad oxide of the contact to the semiconductor device; implanting N dopants using; (g
) stripping the remaining silicon nitride from the contact that provided a path for implanting the N dopant and retaining the photoresist to prevent removal of silicon nitride from unimplanted areas; (h (i) removing the photoresist; (j) directing the implanted N dopant through the EPI layer; (k) forming an emitter region, a base region, and other semiconductor devices; (l) peeling off the remaining silicon nitride and removing the remaining silicon nitride. leaving the underlying pad oxide; (m
) depositing a layer of silicon nitride as the silicon nitride capacitor; (n) depositing a polysilicon layer or an amorphous silicon layer on the silicon nitride; (o) depositing the polysilicon layer or the amorphous silicon layer. , patterning and etching the silicon nitride layer as a capacitor using photolithographic techniques to leave silicon nitride in one of the two openings in the oxide;
stripping the silicon nitride from the other opening in the oxide; (p) stripping the polysilicon layer without affecting controllability of the capacitor or forming an undercut in the silicon nitride as a capacitor; Alternatively, a method for manufacturing a silicon nitride capacitor, comprising a dry etching step and a sputter etching step so that a portion of the amorphous silicon layer is removed. 2. A method of forming a silicon nitride capacitor, the method comprising: providing a partially processed wafer having an oxide on its surface that includes at least two openings leading to a common P-type region or a common N-type region; depositing a layer of silicon nitride as the silicon nitride capacitor; depositing a polysilicon layer or an amorphous silicon layer on the silicon nitride; and depositing the polysilicon layer or the amorphous silicon layer and silicon nitride as the capacitor. and etching using photolithographic techniques to leave silicon nitride in one of the two openings in the oxide and stripping the silicon nitride from the other opening in the oxide. a dry etching process and a sputtering process such that a portion of the polysilicon layer or amorphous silicon layer is removed without affecting the controllability of the capacitor or forming an undercut in the silicon nitride as a capacitor; A method for manufacturing a silicon nitride capacitor, comprising the steps of completing a wafer manufacturing process by a conventional silicon semiconductor wafer manufacturing process including an etching process. 3. A method of forming a silicon nitride capacitor, comprising: providing a first buried layer of a second conductivity type on a silicon substrate of a first conductivity type; forming a first oxide layer on the epitaxial layer; forming a first silicon nitride layer on the first oxide layer; forming a pattern of a plurality of openings in a first silicon nitride layer, the first oxide layer, and a part of the epitaxial layer, and removing the opening portions by etching; forming a recess in the opening; Oxide LOC
forming an OS oxide; forming a second LOCOS oxide; and forming the first silicon nitride layer and the first LOCOS oxide.
implanting a dopant into the epitaxial layer through the oxide layer; removing the first silicon nitride layer; removing the first oxide layer;
diffusing the implanted dopant into the epitaxial layer; forming a second layer of silicon nitride thinner than the first silicon nitride layer over the epitaxial layer; forming a polysilicon layer on the silicon nitride layer; etching the polysilicon layer and the second silicon nitride layer; forming a platinum silicide layer as the polysilicon layer; A method for manufacturing a silicon nitride capacitor, comprising the step of forming a conductive layer on a platinum silicide layer. 4. A method of forming a silicon nitride capacitor, comprising: providing a first buried layer of n-type in a P-type silicon substrate; forming an epitaxial layer of n-type on the surface using ion implantation; forming a first oxide layer on the epitaxial layer;
forming a first silicon nitride layer over the oxide layer; implanting an n-type dopant into the epitaxial layer through the first silicon nitride layer and the first oxide layer; removing the first silicon nitride layer; removing the first oxide layer; diffusing the implanted dopant into the epitaxial layer; forming a second silicon nitride layer thinner than the first silicon nitride layer; forming a polysilicon layer on the second silicon nitride layer; The method is characterized by comprising the steps of etching the second silicon nitride layer; forming a platinum silicide layer as the polysilicon layer; and forming a conductive layer on the platinum silicide layer. Method of manufacturing silicon nitride capacitors.