GB2250378A - Method of forming silicon nitride capacitors - Google Patents

Method of forming silicon nitride capacitors Download PDF

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GB2250378A
GB2250378A GB9119888A GB9119888A GB2250378A GB 2250378 A GB2250378 A GB 2250378A GB 9119888 A GB9119888 A GB 9119888A GB 9119888 A GB9119888 A GB 9119888A GB 2250378 A GB2250378 A GB 2250378A
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silicon nitride
silicon
capacitor
pad oxide
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Neal F Gardner
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Silicon Systems Inc
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Silicon Systems Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3211—Nitridation of silicon-containing layers
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

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Abstract

A method for fabricating silicon nitride metal-insulator semiconductor capacitors as part of an integrated circuit fabrication is disclosed. In prior art, the fabrication process requires formation of a silicon nitride layer on a pad oxide layer as part of the metal-insulator semiconductor capacitors. Both the thickness of the silicon nitride layer and the pad oxide layer are difficult to control. With the present invention, the thickness of the silicon nitride layer 21 is much more easily controlled and undercutting the layer is avoided since a layer 22 of polysilicon or amorphous silicon is deposited over the dielectric nitride layer before etching to produce the desired pattern but after processing steps are carried out to produce N-type regions 17A, 17B and oxide isolation 13. The silicon layer 22 is then implanted to render it conductive and metallization 20 is applied. The method can be incorporated into the process steps for fabricating an integrated circuit. <IMAGE>

Description

-'23037d EMOD OF F0T,1ING SILICON NITRIDE CAPACITORS
BACKGROUND OFTHE PRESENT INVENTION
1. FIELD OF THE INVENTION
This invention relates to the field of semiconductor processing of integrated circuits, in particular to a method and apparatus for forming metal- insulator semiconductor capacitors.
2. BACKGROUND ART
In the prior art, one typical method of fabricating a metal-iiisulator semiconductor capacitor is to use two dielectric layers. With this method, in the first part of the process, a pad oxide layer is used in conjunction with a -ilicoii nitride layer for [lie well known LOCOS (localized oxidation of silicon) s process. The silicon nitride layer is subsequently stripped and a second silicon nitride layer is deposited. The second silicon nitride layer is used in conjunction with the original pad oxide layer for the insulator portion of metal-iiisulator semiconductor capacitors. The disadvantage of this system is both the oxide and nitride layers may be subject to erosion during wafer fabrication. Specifically, the pad oxide may be eroded during wet etching of the initial silicon nitride layer. If the composition of the etch is not carefully controlled, unwanted etching of the pad oxide layer can result. Moreover, the second nitride is eroded during the sputter etch prior to platinum disposition.
In the prior art, further complications can result during removal of the pad oxide from regioli of the integrated circuit that are not part of the silicon nitride capacitors. Dry etching is not desirable unless a special dry etch. process with very high selectivity of silicon dioxide over silicon nitride and silicon is developed. A dry etch process with poor selectivity can erode the capacitor nitride. If a wet etch is attempted to remove the pad oxide, the wet etch can 1 undercut the capacitor nitride resulting in metallization step coverage problems.
Therefore, it is an object of the present invention to provide a method for fabricating nietal-insulaLor semiconductor capacitors without experiencing erosion of the insulator layer.
It is another object of the present invention to provide a method of fabricating metal-insulator semiconductor capacitors without experiencing potential melallization step coverage problems due to undercutting of insulator layers during wet etching of the pad oxide.
it is still another object of the present invention to provide a method of fabricating metal-insulator semiconductor capacitors with better repeatability in the thickness of the insulating layers.
it is still another object of this invention to provide a method of fabricating metal-insulation semiconductor capacitors which introduces process modifications that do not require re-engineering of other parts of the integrated circuit fabrication process not related to the fabrication of the inetal-insulator semiconductor capacitors.
i 2 SUMMARY OF THE PRESENT INVENTION
A method for fabricating silicon nitride capacitors is disclosed. The processing requires in part the removal of a pad oxide layer using an etching technique. In the prior art, the removal of this pad oxide layer is processsensitive. The present invention allows removal of the pad oxide ill a manner which is process insensitive. This results in improved control of capacitor values. In the present invention, the pad oxide layer is removed prior to deposition of the capacitor silicon nitride layer. The silicon nitride layer is then protected with a seini-sacrificial layer of polysilicon to prevent erosion of the silicon nitride during subsequent processing steps. The polysilicon layer also obviates the need to wet etch pad oxide regions oil parts of the integrated circuit that are not covered by silicon nitride, thereby preventing potential rnetallization step coverage problems from undercutting [lie silicon nitride during the oxide wet etch.
j 3 BRIEF DESCRIPTION OF THE DRAWINGS
Figures 1-7 provide cross-sectional views of a semiconductor substrat and illustrate prior art processing steps in the forniation'of a silicon nitride 5 capacitor.
Figures 8-12 are a cross-sectional view of a substrate illustrating the processing steps of the present invention in forming a silicon nitride capacitor.
4 t DETAILED DESCRIPTION OF THE PRESENT INVENTION
A method for forming silicon nitride capacitors is described. In the following description, numerous specific details such as conductivity type, dopant species, etc. are set forth ill detail in order to provide a more thorough description of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these -specific details. In other instances, well known features have not been described in detail so as not to obscure the present invention.
Figure 1 is a cross sectional view of a silicon substrate 10 illustrating the initial processing steps utilized in the present invention. The present invention is formed in a P-type silicon substrate. The following description illustrates the formation of a capacitor and a collector of all NPN transistor.
Initially, all N+ buried layer 11 is formed in the P type substrate layer 10. The N+ buried layer 11 is typically formed using ion implantation techniques and may utilize any suitable dopant such as arsenic or antimony. The N+ layer 11 forms a "well" which reduces the base-collector resistance.
Although the present invention illustrates a silicon nitride capacitor formed in conjunction with an NPN transistor, this is by way of example only. The present invention is also directed to the formation of a silicon nitride capacitor without an associated transistor.
After formation of the buried layer 11, an N-type epitaxial layer is deposited on the top of the entire substrate. A thin silicon dioxide layer (approximately 400 angstroms) is formed on the epitaxial layer. This oxide layer is referred to hereafter as the pad oxide layer. A silicon nitride layer (approximately 1000 angstroms) is then deposited on the silicon dioxide layer.
The silicon nitride, silicon dioxide and a portion of the epitaxial layer are then patterned and etched using photolithographic techniques. Then the localized field oxide 13 (LOCOS) is formed by a thermal oxidation process. This field oxide is formed only in re ions not covered by silicon nitride. The pad oxide - M:, 1 - _..
regions 16A and 16B pr!vent formation of stress-induced defects during this thermal oxidation. The region generally about 12A is used to form the capacitor and [lie region about 12B is used to form the contact to the semiconductor electrode of the capacitor.
A second LOCOS oxidation is performed, which leaves behind regions of nitride only where contacts are to be made to the respective devices. Silicon nitride regions 14A and 14B are left intact during the second LOCOS.
Photo resist layer 15 is formed and patterned on the surface of the field oxide and N+ phosphorous layers 16A and 16B are implanted in the exposed areas of the epitaxial regions 12A and 1213. The N+ layers are implanted through the nitride and pad oxide layers and used to form the N+ capacitor and the collector of [lie NPN transistor.
Figure 2 illustrates the effects of subsequent prior art processing steps used to form a silicon nitride capacitor. The photoresist layers 15 are removed. Next, a diffusion process is executed so that the implanted phosphorous regions 16A and 16B are diffused into the epilayer 12A and 12B to form deep N+ regions, 17A and 1713. The region 17A is the bottom electrode of the capacitor and the surface of region 17B ultimately becomes a' contact which electrically connects this electrode to surface metallization.
Regions similar to 17B also function as collectors to NPN transistors.
Next, the silicon nitride layers 14A and 14B are stripped, leaving tile pad oxide layers 13A and 13B over the N+ regions 17A and 17B as illustrated in Figure 3. A new silicon nitride layer 18 is then deposited on the surface of the substrate 10. This thin silicon nitride layer is then patterned and etched so that it rernains only over the pad oxide region 13A of the capacitor.
6 A Next, the pad oxide layer 13B is removed from the transistor N region 17B as illustrated in Figure 5. Referring now to Figure 6, a "self-aligiiett" platinum silicide layer 19 is formed over the deep N+ region 17B. Next, metalization layers 20A and 20B are formed and patterned as illustrated in Figure 7. The metal layer 20A is the metal electrode of the silicon nitride capacitor and the metal layer 20B provides contact to [lie N+ silicon electrode of [lie capacitor.
A disadvantage of the prior art method of forming metal-insulator semiconductor capacitors is [lie need to provide careful process control for two different dielectric layers, that is, the pad oxide layer 13A and the silicon nitride layer 18. When the silicon nitride layers 14A and 14B are stripped, [lie pad oxide may be eroded. A sputter etch process prior to the deposition of the platinum layer 19 erodes silicon nitride layer 18.
A second disadvantage of the prior art method of forming metalinsulator semiconductor capacitors arises from the need to remove the pad oxide from the emitter and base regions of NPN transistors (not shown). This is normally done after depositing and patterning the thin silicon nitride 18 and prior to depositing metallization 20A and 20B. If a dry etch process is used to remove this pad oxide, the dry etch process must be very selective in etching silicon dioxide much faster than either silicon ritride or silicon. The high selectivity over silicon nitride is required to prevent erosion of the thin silicon nitride 18 for [lie capacitors. The lligh selectivity for silicon is required to prevent excess erosion of emitter and base contacts after removal of the pad oxide. In practice, the required degree of selectivity is difficult to attain.
A much higher degree of selectivity can easily be attained with wet:
etching of the pad oxide. But wet etching gives rise to undercutting 21 of the thin silicon nitride as in regions 91A and 21B of Figure 7. This undercutting can cause nietallization step coverage problems in regions such as 21A.
7 The initial processing steps of the present invention are substantially similar to those shown and described in connection with Figure 1. Referring now to Figure 8, silicon nitride layers 14A and 14B are stripped from the capacitor and collector contacts, respectively. Pad oxide layers 13A and 13B are wet etched to expose the implanted silicon contact regions beneath as shown in Figure 9.
The photoresist 15 is removed and the implanted N-1- regions 16A and 16B are diffused to form deep N+ regions as illustrated in Figure 10. The resulting deep N+ regions 17A and 17B will serve as a capacitor electrode and/or a collector. At this point during fabrication, processing of the einitter and base regions of the bipolar transistors begins.
Referring now to Figure 11, after stripping the silicon nitride from regions that were covered with pholoresist in Figure 8 from all regions of [lie wafer surface, a new layer of silicon nitride 21 is deposited over the wafer. For a specified capacitance per unit area, the silicon nitride layer 21 is thicker in the present invention than the prior art layer 18, since in the preferred process, the pad oxide layer has been removed. The stripping and redepositing of silicon nitride is a necessary feature because the two layers carry out two distinct functions. The original silicon nitride layers 14A and 14B are used as a masking layer for LOCOS oxidation and therefore, must be deposited on a pad oxide. The second silicon nitride layer 21 is used as the dielectric in a capacitor and thus is deposited directly on the N+ silicon electrode. Figure 11 also illustrates the deposition of a polysilicon layer 22 (-500 angstroms) which will prevent erosion of the silicon nitride layer 21 during subsequent processing.
Referrhig now to Figure 12, the polysilicon 22 and silicon nitride layers 21 are patterned and dry etched so that they remain only over the capacitor 8 z !:z regions. A dry etch is then performed to remove pad oxide on other regions of NPN transistors and oilier devices (not shown). A dry etch is used here to prevent undercutting of the silicon nitride of the capacitor. This prevents nietalization step coverage problems in subsequent processing steps. The polysilicon 22 prevents erosion of the capacitor nitride 21 during the dry etch of the pad oxide. Since a dry etch is used to remove the pad oxide, the undercutting problem associated with wet etclihig is avoided.
Next, the polysilicon layer 21 is implanted with a p or n type dopant, such as boroii, phosphorous or arseiiic, and the dopant is activated with a heat treatment to make the polysilicon conducting. The required implant dose of this dopant must be high enough to ensure that the polysilicon is highly conductive and makes a good olimic contact to the subsequently formed platinum silicide. Metallization layers 20A and 20B are then fornied and patterned over the capacitor.
Thus, a method of fori-nhig silicon nitride capacitors has been described.
9 1 1 CIADIS 1. A method of forming a silicon nitride capacitor as part of a silicon semiconductor wafer fabrication process comprising the steps of.
(a) providing a P-type silicon substrate; (b) forming localized N-type buried layers on a surface of said substrate; (c) forming all N-type EPI layer over said surface; (d) forming recessed oxide LOCOS isolation with at least two lo openings ill the oxide over a specified localized buried layer region; (e) forming a second LOCOS oxide, having regions of nitride and pad oxide where contacts are to be made to semiconductor devices including at least portions of each of said two openings ill said recessed oxide isolation over said specifed localized buried layer region; (f) implanting N dopant through said silicon nitride and pad oxide of said two openings and through said silicon nitride and pad oxide of said contacts to said semiconductor devices, using photomasking techniques to prevent implantation into other device contacts; (g) stripping residual silicon nitride from said contacts through which said N depant is implanted, retaining said photoresist to prevent renloval of silicon nitride from unimplanted regions; (11) stripping residual pad oxide from contacts through which said N dopant is implanted; (1) removing said photoresist; (j) diffusing said implanted N dopant through said EPI layer to said N-type buried layers; (k) forming ernitter and base regions and other semiconductor devices; (1) stripping said remaining silicon nitride, leaving pad oxide under the remaining silicon nitride; 1 (111) depositing a layer of silicon nitride for said silicon nitride capacitor; (11) depositing a polysilicon layer or amorphous silicon layer on said silicon nitride; (0) patterning and etching said polysilicon or amorphous silicon and said capacitor silicon nitride using photolithographic techniques, leaving silicon nitride in one of said two openings in said oxide, and stripping said silicon nitride from [lie oilier opening in said oxide; (p) completing the wafer fabrication process with conventional silicon semiconductor wafer fabrication processing including dry etching and sputter etching steps wherein a portion of said poly silicon or amorphous silicon is removed without affecting the controllability of the capacitors or undercutting the capacitor silicon nitride.
r_ 2. The method of claim 1 further including the steps of:
implanting said polysilicon or amorphous silicon layer with N or P dopants; processing.
activating said implanted dopant through high temperature 3. A method of forming silicon nitride capacitors comprising the' steps of: providing a partially processed wafer having an oxide on the surface with at least two openings in said oxide to a common 11-type or N-Lype region; depositing a layer of silicon nitride for said silicon nitride capacitor; depositing a polysilicon layer or amorphous silicon layer on said silicon nitride; patterning and etching said polysilicon or amorphous silicon and said capacitor silicon nitride using photolithographic techniques, leaving silicon nitride in one of said two openings in said oxide, and stripping said silicon nitride from the other opening in said oxide; 11 completing the wafer fabrication process With conventional silicon semiconductor wafer fabrication processing including dry eLching and sputter etclihig steps wherein a portion of said poly silicon or amorphous silicon is removed without affecting the controllability of the capacitors or undercutting the capacitor silicon nitride.
4. The method of claim 3 further including the steps of: iinplanting said polysilicon or amorphous silicon layer with N or P dopants; activating said implanted dopant through high temperature processing.
steps of:
5. A method of forming a silicon nitride capacitor comprising the providing in a first conductivity type silicon substrate a first buried layer of a second conductivity type; forming an epitaxial. layer of said second conductivity type over entire surface; forming a first fficide layer over said epitaxial layer; forming a first silicon nitride layer over said first oxide layer; patterning and etching away openings in said first silicon nitride, first oxide and portion of said epitaxial layer, forming a recessed oxide LOCOS oxidation in said openings; forming a second LOCOS oxidation; implanting a dopant through said nitride layer and said first oxide layer into said epitaxial layer; removing said first silicon nitride layer; removing said first oxide layer; diffusing said implanted dopant into said epitaxial layer, 12 1 t forming a second layer of silicon nitride over said epitaxial layer, said second layer of silicon nitride having a thickness less than the thickness of said first nitride layer; forming a polysilicon layer over said second nitride layer; etching said polysilicon layer and said second nitride layer; forming a platinum silicide layer as said polysilicon layer; and forming a conductive layer over said platinum silicide layer.
6. The method of claim 5 wherein said first silicon nitride layer is used as a masking layer for field oxide oxidation and said second silicon nitride layer is used as [lie dialectric in the capacitor.
7. The method of claim 5 wherein said etching step is a dry etch.
8. The method of claim 7 wherein [lie remaining said polysilicon layer is implanted with either said first or second conductivity type to ensure an ohinic contact with said conductive layer.
9. The method of claim 8 wherein said first conductivity type is P- type.
10. steps of:
A method of forming a silicon nitride capacitor comprising the providing in a p-type silicon substrate a first buried layer of ii-type; forming an epitaxial layer of n-type using ion implantation over the surface forming a first oxide layer over said epitaxial- layer; forming a first silicon nitride layer over said first oxide layer; implanting a dopant of n-type through said nitride layer and said second oxide layer into said epitaxial layer, removing said silicon nitride layer; removing said second oxide layer; 13 diffusing said implanted dopant into said epitaxial layer; forming a second layer of silicon nitride over said epitaxial layer, said second layer of silicon nitride having a thickness less than the thickness of said first nitride layer; forming a polysilicon layer over said second nitride layer; etching said polysilicon layer and said second nitride layer; forming a platinum silicide layer as said polysilicon layer; forming a conductive layer over said platinum silicide layer; t 11. The method of claim 10 wherein said first silicon nitride layer is used as a masking layer for field oxide oxidation and said second silicon nitride layer is used as [lie dielectric in the capacitor.
12. The niethod of claim 11 wherein said etching step is a dry etch.
13. The method of claim 12 wherein the remaining said polysilicon layer is implanted with either said first or second conductivity type to ensure an olimic contact with said conductive layer.
14. A method of forming a silicon nitride capacitor as part of a silicon semiconductor wafer fabrication process substantially as hereinbefore described with reference to the accompanying drawings.
c 14
GB9119888A 1990-11-27 1991-09-18 Method of forming silicon nitride capacitors Withdrawn GB2250378A (en)

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EP1560269A1 (en) * 2004-01-30 2005-08-03 Alcatel MOS capacitor in an integrated semiconductor circuit
US8076728B2 (en) 2004-02-10 2011-12-13 Infineon Technologies Ag Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production

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US8076728B2 (en) 2004-02-10 2011-12-13 Infineon Technologies Ag Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production

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GB9119888D0 (en) 1991-10-30
JPH04290273A (en) 1992-10-14
KR920010970A (en) 1992-06-27
DE4137081A1 (en) 1992-06-17

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