JPS61234564A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having excellent frequency characteristics, by forming an emitter region in a base region by a self-aligning method, and lowering the resistance of the base and the capacity between the base and a collector. CONSTITUTION:A silicon film, which has impurity diffusing source for forming an emitter region, is formed on a semiconductor substrate region, which is to become an emitter region 7. A base region 6 is formed by implanting ions partially through the silicon film. Then, by using the silicon film, the emitter region 7 is formed in the base region 6 by a self-aligning method. An insulating film is formed between the silicon film and a base-electrode taking-out region on the emitter region 7 by the self-alignment. The part between the base electrode and the emitter electrode is insulated. A base-electrode taking-out region is formed by the self-alignment. The interval between the emitter and the base is the thicknesses of an oxide film 107 on the side wall of a silicon film 603 and a nitride film 203. The base resistance becomes small. An emitter region 70 and the active base region 6 are simultaneously formed through the silicon film 603. Therefore, the region 70 and the region 6 are in approximately parallel. The width of the base is constant. The area of the base is reduced to a large extent. The capacity between the base and collector is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming an electrode extension portion of a base in a bipolar semiconductor integrated circuit device.

[Prior Art] Generally, transistors in a bipolar semiconductor integrated circuit device are formed in electrically independent islands by pn junction isolation, oxide film isolation using selective oxidation technology, triple diffusion, or the like.

Here, a method for forming an npn transistor using an oxide film separation method will be described. Of course, when using the above-mentioned various separation methods other than this, it can also be applied to pnp transistors.

FIGS. 58 to 5E are cross-sectional structural views of a semiconductor device at major process steps according to a conventional manufacturing method. The conventional manufacturing method will be briefly described below with reference to FIGS. 5A to 5E.

In FIG. 5A, a p-type (+)-type) silicon substrate 1 with a low impurity concentration and a high impurity concentration n
A type (n+ type) layer 2 is selectively formed. Next, an n''' type epitaxial layer 3 is formed on the silicon substrate 1 and the n'' type layer 2.

In FIG. 5B, an underlying oxide film 101 and a nitride film 20
1 is formed in a predetermined area on the nth layer 3. Nitride film 20
1 as a mask, a p-type layer 4 for channel cutting is formed, and then, simultaneously with annealing of the p-type layer 4, a nitride film 201 is formed.
A thick isolation oxide film 102 is formed by selective oxidation using as a mask.

In FIG. 5C, first, the nitride film 201 used as a second layer for selective oxidation is removed together with the underlying oxide film 101. Next, an oxide film 103 for protecting ion implantation is formed again, and a photoresist film (the photoresist film at this stage is not shown) is used as a mask to form the external base layer.
A + type layer 5 is formed. Roughly, the photoresist film 301 is removed, a photoresist film 301 is formed again in a predetermined shape, and using this as a mask, a p-type layer 6 that will become an active base layer is formed by ion implantation.

In FIG. 5D, photoresist film 301 is removed and then passivation film 401, typically phosphorus glass (PSG), is deposited. Base ion implantation layer 5.6
By performing a heat treatment that also serves as annealing and baking of the PSG film 4.1, an intermediate external base layer 51 and an active base layer 61 are formed. Next, an emitter electrode contact hole 7o is formed in a predetermined area of the PSGl 1401.
A contact hole 8o for collector electrode is formed, and an n+ type layer 7 to become an emitter layer and an n'' type layer 8 to become a collector electrode extraction layer are formed by ion implantation through this contact hole 70.80. .

In FIG. 5E, each ion implantation layer is annealed to complete external base 152 and active base layer 62, and to form emitter layer 71 and collector electrode extraction layer 81. All-island silicide L to prevent electrode penetration into each opening 50, 70 and 80 (for example, to prevent reaction between Hemi and 3i)! ! 501 is formed. For this metal silicide film 501, platinum silicide (Pt-8i), palladium silicide (Pd-8i), or the like is used. Aluminum (,11
) is used to form a base electrode wiring 9°, an emitter electrode wiring 10, and a collector electrode wiring 11.

[Problems to be Solved by the Invention] Incidentally, the frequency characteristics of a transistor depend on base-collector capacitance, base resistance, and the like.

Therefore, in order to improve the frequency characteristics of the transistor, it is necessary to reduce these. The p+ type external base layer 52 in the conventional structure described above is provided to reduce base resistance.

However, this external base layer 52 has the disadvantage of increasing base-collector capacitance.

FIG. 6 is a plan pattern diagram of a transistor manufactured by a conventional method. The base resistance depends on the distance between the emitter layer 71 and the base electrode extraction opening 50 shown in FIG. In the conventional device, the total distance is the distance between the base electrode wiring 9 and the emitter electrode wiring 10 and the protrusion of the electrode wiring 9.10 from the respective openings 50.70. Therefore, even if the precision of photoetching is improved and the spacing between the electrode wirings is reduced, the above-mentioned protrusion will inevitably remain. Further, the base region between the emitter layer 71 and the isolation oxide film boundary A shown in FIG. 6 is an inactive region, increasing the base-collector capacitance. In order to eliminate this inactive region, there is a method of forming a walled emitter structure in which the emitter layer 71 is in contact with the isolation oxide film.

However, this method also has various drawbacks.

78 to 7C are views showing a part of the cross section taken along the line XX in FIG. 6. Hereinafter, problems with the conventional wold emitter structure will be explained with reference to FIGS. 7A to 7C.

FIG. 7A shows 7 otresist 1130 for base formation.
1 as a mask, the state in which boron, which is a p-type impurity, is implanted is shown. Next, it is necessary to remove the oxide film 103 on the emitter region 7 to form a contact hole. However, in this walled emitter structure,
As shown in FIG. 7B, the boundary A of the isolation oxide film 102
When the oxide film is removed, the emitter region is overetched and the emitter region becomes deeper as shown at 8 in FIG. 7C. As a result,
There is a great risk that the controllability of the current amplification factor will deteriorate, and that a short circuit will occur between the emitter and the collector at the portion B shown in FIG. 7C.

Generally speaking, as a method of reducing base resistance, a double base structure as shown in FIG. 8 is often used. However, the conventional method has the disadvantage that the base area increases due to extraction of the base electrode, which results in an increase in base-collector capacitance.

Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the above-mentioned drawbacks, reduce base resistance and base-collector capacitance, and obtain a semiconductor device with good frequency characteristics. .

[Means for Solving the Problems] In the method of manufacturing a semiconductor device according to the present invention, a polysilicon film having an impurity diffusion source for forming an emitter region is formed on a semiconductor substrate region that will become an emitter region, and a base region is uniformly formed. This polysilicon film is then used to form an emitter region within the base region in a self-aligned manner. Furthermore, an insulating film is formed in a self-aligned manner between the polysilicon film on the emitter region and the base electrode lead-out region to insulate the base-emitter electrode, and furthermore, the base electrode lead-out region is formed in a self-aligned manner.

[Operation] Since the emitter region is formed in the base region in a self-aligned manner, the emitter polysilicon film is formed in a self-aligned manner by the patterning mask of the polysilicon film that serves as an emitter region diffusion source and is connected to the metal electrode. A minimum base electrode extraction area is formed at the periphery.

Further, since only an insulating film is interposed between the silicon film on the emitter region and the metal wiring on the base region, the emitter-base distance becomes small due to the thickness of this insulating film.

Furthermore, since the emitter region is formed by diffusing impurities from the polysilicon film, which serves as an impurity diffusion source, into the region that is to become the emitter region, there is no need to form a contact hole for ion implantation when forming the emitter region. . Therefore, there is no need to remove the oxide film on the emitter region, and no over-etching occurs at the boundary of the isolation oxide film, so that the emitter region and base region contact the isolation region in a substantially parallel state.

[Embodiment of the Invention] FIGS. 18 to 1J are cross-sectional views at main process steps of a method for manufacturing a semiconductor device according to an embodiment of the invention. Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 18 to 1J.

See Figure 1A. An n+ type collector buried layer 2. is formed in a predetermined region of the p- type silicon substrate 1. n-type epitaxial layer 3. P-type layer 4 for channel cut, isolation oxide film 102
．． An n+ diffusion layer 8 which becomes a collector electrode extraction region is formed. The formation of each region is performed using a method similar to the conventional method shown in FIGS. 5A and 5B. Next, the fifth
Underlying oxide 11101 and nitride film 201 shown in Figure B
After the polysilicon film 600. is removed, the polysilicon film 600. nitriding v142
02 and oxide film 104 are formed in this order on the surface of semiconductor substrate 1. Next, using the resist film 303 having a predetermined pattern shape as a mask, the polysilicon film 600. Nitride film 202 and oxide Il! A multilayer film consisting of 104 layers is etched.

By this patterning, the oxide film 104 and the nitride film 104 are formed only in the regions that will later become the collector electrode extraction layer and the emitter layer.
! 202. A polysilicon layer 600 remains.

See Figure 1B. Using the resist film 303 used for patterning the multilayer film in the above-described process as a mask, only the side walls of the oxidized 1!104 included in the multilayer film are side etched. As a result, the oxide film 104 is replaced by the polysilicon film 6.
00 and retreats inward from the nitride film 202.

In FIG. 1C, selective oxidation is performed using nitride 1202 as a mask to form an oxide film 105 in a predetermined region on the surface of the semiconductor substrate.

In FIG. 1D, the nitride film 202 is buttered by etching using the oxide M104 as a mask. At this time, a portion of the polysilicon layer 600 underlying the nitride film 202 is etched to a certain thickness, and the portion protruding from the nitride film 202 is thinned.

This is to make it possible to easily oxidize this portion (thin polysilicon layer) to form an oxide film when forming an oxide film in the next step.

See Figure 1E. After the oxide film 104 is removed, the oxide film 10 is removed by selective oxidation using the nitride film 202 as a mask.
6 is formed on the surface of the semiconductor substrate between polysilicon film 600 and oxide film 105.

At this time, the selective oxidation is performed on the thin (thinned) polysilicon film 60.
This is done to the extent that not only the oxidation layer 0 but also the n-type semiconductor region 3 below it is slightly oxidized. The oxide film 106 is polysilicon m
Covers 600 side walls.

In FIG. 1F, the nitride film 202 is first removed. Next, a polysilicon layer 600 is formed using the oxide film 106 as a mask.
Introducing n+ type impurities into impurity-containing polysilicon! 1
1601 is formed. As a result, the polysilicon film 6
01 serves as an impurity diffusion source for forming an emitter region.

In FIG. 1G, after the oxide film 106 is removed, p-type impurities are ion-implanted, and the ion-implanted layers 52', 51
, 52.53 are formed. At this time, the n-type semiconductor region from which the oxide film 106 has been removed becomes an external base layer. On the other hand, oxide film 105 is left to separate the base region and collector region. Therefore, the oxide film 105 is as thick as 1 μ- in the selective oxidation shown in FIG. 1C, and the oxide film 106 is as thick as 2 μ- in the selective oxidation in FIG.
It is formed as thin as 0 to 300 n-. Additionally, 0 layers 52' and 5 are formed by ion implantation into the collector electrode extraction region.
2 is an almost negligible amount of impurity due to the n1 diffusion layer 8 for taking out the collector electrode, and has almost no effect on the diffusion layer 8 for taking out the collector electrode. Furthermore, the ion-implanted region below the polysilicon film 602, which should become the active base layer, is formed shallower than the region 53, which should become the external base layer, because the p-type impurity is ion-implanted through the polysilicon layer 602. Ru.

In FIG. 1H, annealing of the p-type impurity ion-implanted layer and diffusion of the n+-type impurity from the polysilicon film 602 into the silicon substrate 3 are performed simultaneously. As a result, the emitter region 7 is formed in a self-aligned manner, and
External base region 54 is formed to be slightly deeper and lower in resistance than active base region 6. Next is low 21! (800℃～9
A thick oxide film 107 is formed on the n+ type polysilicon film 603, 604, and a thin oxide film 108 is formed on the p+ type silicon substrate 54.

This utilizes the well-known fact that enhanced oxidation occurs at low temperatures in silicon and polysilicon containing a high concentration of n-type impurities such as phosphorus or arsenic.

In FIG. 1, oxide films 107 and 108 formed on polysilicon films 603 and 604 are anisotropically etched.
The thin oxide film 108 on the extrinsic base region 54 is removed by RIE. Here, as a method for preventing short circuits of the base electrode to the emitter layer 7, a nitride film 203 is deposited on the entire surface shown in FIG. 1H, and only the side walls of the polysilicon film 603 are nitrided by anisotropic etching. After leaving the film 203, the oxide film 1 is formed again using the RIE method.
08 is removed and an oxide film is formed on the side wall of the polysilicon film 603.
There is a method of leaving the nitride film, and this state is shown in FIG.

In FIG. 1J, first, the thick oxide film 108 on the collector electrode extraction region 8 is removed. Next, selective etching is performed in a predetermined region to form an emitter electrode contact hole 70 (not shown in FIG. 1J) and a collector electrode contact hole 80. Then, for example, A
Base electrode wiring using low resistance metal such as fL9. Emitter electrode wiring 10 (not shown in FIG. 1J) and collector electrode wiring 11 are formed, respectively. As seen from FIG. 1J, the emitter-base spacing is approximately the thickness of the oxide film 107 and nitride film 203 on the sidewalls of the polysilicon film 603, and the base resistance is extremely small.

FIG. 2 is a plane pattern diagram of a transistor manufactured in one embodiment of the above-described invention, and corresponds to the plane pattern diagram of a conventional transistor shown in FIG. As shown in FIG. 2, emitter electrode wiring 10
Since the polysilicon film 603 connected to the polysilicon film 603 serves as a diffusion source for the emitter region 7, the emitter region 7 comes into contact with the isolation oxide film 102 at point A in the figure. Also,
Conventional method and development shown in FIG. 7, emitter region 7
is formed in a self-aligned manner by impurity diffusion from the polysilicon film 603, so that the base region is isolated and oxidized 1!10
It will not become narrow due to overetching in the vicinity of 2. That is, as shown in FIG.
Since active base region 6 and active base region 6 are formed at the same time via polysilicon film 603, they are substantially parallel and the base width is constant. Therefore, the base area is significantly reduced due to the elimination of the protruding area between the emitter and base electrodes, and the fact that the base electrode extraction area is formed with the minimum area in a self-aligned manner, and the base-collector capacitance is reduced. reduced. Furthermore, as seen in FIG. 2, since the base electrode wiring 9 is formed around the three sides of the emitter region 7, a double base structure is automatically formed, without causing an increase in the base tIA area. , the base resistance is significantly reduced.

As another example, instead of performing the n-type impurity diffusion for forming the collector electrode extraction region as shown in FIG. 4, in the step shown in FIG. After removing the oxide 11106 in the region, p-type impurity is selectively implanted and annealing is performed.

As a result, the polysilicon 116 implanted with n-type impurities
An n-type impurity can be diffused from 04 to form an electrode extraction layer.

Needless to say, the present invention can also be applied to the manufacture of pnp transistors.

[Effects of the Invention] As described above, according to the present invention, since only an insulating film is interposed between the silicon film on the emitter region and the metal electrode film on the base region, the emitter-base spacing can be effectively reduced. As a result, the base resistance is reduced and the frequency characteristics of the semiconductor device are improved.

In addition, the emitter region is formed by diffusing impurities for forming the emitter region into the region that is to become the emitter slope using the polysilicon film as a diffusion source, and at the same time, the impurities for forming the base region are roughly diffused into the semiconductor substrate. Since the base region is completed using the same method, the boundary of the isolation region is not over-etched, and the emitter region and the base region can be brought into contact with the isolation oxidized m region in a substantially parallel state.

Furthermore, since the base electrode lead-out region is formed with the minimum area in self-alignment with the pattern for forming the emitter region, the inactive base region is significantly reduced.

Furthermore, the pattern size of the polysilicon 11603 forming the emitter layer is reduced to 1/3 or less from the pattern size of the resist film 303 shown in FIG. Micron wide emitter regions can be realized. In the manner described above, it is possible to manufacture a semiconductor integrated circuit device with improved frequency characteristics.

[Brief explanation of drawings]

FIGS. 18 to 11J are diagrams showing cross-sectional structures at main process steps of a manufacturing method according to an embodiment of the present invention. FIG. 2 is a plan pattern diagram of a transistor manufactured by the method of the present invention. FIG. 3 is a schematic cross-sectional view of the semiconductor device in the present invention near the isolation oxide film boundary. Fourth
The figure is a cross-sectional structural diagram of a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIGS. 58 to 5E are cross-sectional views showing the state of a semiconductor device at main process steps of a conventional manufacturing method. FIG. 6 is a plan pattern diagram of a transistor manufactured by a conventional method. FIGS. 78 to 7C are schematic cross-sectional views of the vicinity of the isolation oxide film when the emitter layer is formed in contact with the isolation oxide film by the conventional method. FIG. 8 is a plan pattern diagram of a transistor with a double base structure manufactured by a conventional method. In the figure, 1 is a p-type silicon substrate, 2 is an n-type collector buried layer, 3 is an n-type epitaxial layer, 5 is a region to be an external base layer, 52 and 54 are external base regions,
6.62 is the active base region, 7.71 is the emitter region,
8 and 81 are collector electrode extraction areas, 9 is a base electrode wiring, 10 is an emitter electrode wiring, 11 is a collector electrode wiring,
5o is a contact hole for the base electrode, 70 is a contact hole for the emitter electrode, 80 is a contact hole for the flutter electrode,
102 is a tIIW1 film, 103, 104, 105.
106,107.108! *Oxide film, 2o1°202.
203 is a nitrided layer, 303.304 is a photoresist film,
401 is a passivation film, 600.601, 602
, 603 and 604 are polysilicon films. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa 1st AI2] Fig. 10 Takashi 1D Fig. 1E Group 1G Fig. 1HUfU Fig. 1j tt: Kore 7P+, &1itJtL tp
) text; vl is also 1sho

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device formed on a semiconductor substrate of a first conductivity type and comprising an emitter region, a collector region, and a base region, wherein the semiconductor device is electrically connected to an adjacent semiconductor device by a separation region. a first step of forming a multilayer film which is insulated and is made up of a polysilicon film, a nitride film, and an oxide film deposited in this order on a predetermined region on the surface of the semiconductor substrate; a second step of side-etching only the oxide film to be retreated inward from the nitride film and the silicon film; and performing selective oxidation using the nitride film as a mask to form a oxide film in a predetermined region on the semiconductor substrate. a fourth step of selectively etching and removing the nitride film and the polysilicon film using the side-etched oxide film as a mask; a fifth step of performing selective oxidation using a nitride film as a mask to form a second oxide film on the surface of the semiconductor substrate between the polysilicon film and the first oxide film; a sixth step of introducing impurities of the first conductivity type into the polysilicon film using an oxide film as a mask; and a seventh step of removing the second oxide film on a region of the base region that will become an electrode extraction portion. an eighth step of introducing a second conductivity type impurity into the region to become the base region; and heating the semiconductor substrate to remove the first conductivity type impurity from the polysilicon film. a ninth step of diffusing the semiconductor substrate into a region to become the emitter region to form the emitter region and simultaneously completing the base region; a tenth step of forming a third oxide film on the sidewalls and top surface of the polysilicon film; and an opening penetrating the third oxide film formed in a predetermined region on the polysilicon film. an eleventh step of forming an emitter electrode through the semiconductor substrate, and providing electrode wires serving as a base electrode and a collector electrode on predetermined regions on the semiconductor substrate. (2) between the tenth step and the eleventh step, further comprising the step of forming a nitride film on the sidewall of the third oxide film formed on the polysilicon film connected to the emitter region; , a method for manufacturing a semiconductor device according to claim 1.