JPS622657A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the frequency characteristics of a semiconductor device only by providing an insulating film between a silicon film on an emitter region and a metal electrode film on a base region, thereby effectively reducing the interval between the emitter and the base, and reducing the resistance of the base. CONSTITUTION:In order to prevent a short circuit between a base electrode and an emitter layer 7, a nitride film 203 is deposited on the entire surface. The nitride film 203 is made to remain only on the side wall of a polysilicon film 603 by anisotropic etching. Then, an oxide film 108 is removed by using an RIE method again. The oxide film and the nitride film are made to remain on the side wall of the polysilicon film 603. Thus, the interval between the emitter and the base becomes approximately equal to the thickness of the oxide film 107 and the nitride film 203 on the side wall of the polysilicon film 603. Therefore, the resistance of the base becomes very low.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor iW, and more particularly to an improvement in a method for forming a III lead portion of a base in a bipolar semiconductor integrated circuit device.

[Prior Art] Generally, transistors in a bipolar semiconductor integrated circuit device are formed in electrically independent islands by a method such as pn junction isolation, selective oxidation technology, or triple diffusion.

Here, a method for forming an npn transistor using an oxide film separation method will be described. Of course, when using the above-mentioned various separation methods other than this, p+1p l
- It can also be applied to transistors.

FIGS. 58 to 5E are diagrams showing the cross-sectional structure of a semiconductor device at major process steps according to a conventional manufacturing method. Hereinafter, a conventional manufacturing method will be briefly described with reference to FIGS. 5A to 5E.

In FIG. 5A, a p-type (p-type) silicon substrate 1 with a low impurity concentration and a high impurity concentration n
A type (n+ type) layer 2 is selectively formed. Next, an n − type epitaxial layer 3 is formed on the silicon substrate 1 and the n + type layer 2 .

In FIG. 5B, the underlying oxide film 101 and the nitrided film 1!2
01 is formed in a predetermined region on n-lIa. At the same time as annealing the p-type layer 14 for channel cut using the nitride 11201 as a mask, a thick isolation oxide film 102 is formed by selective oxidation using the nitride 11201 as a mask.

In FIG. 5C, first, the nitride film 201 used as a mask for selective oxidation is removed together with the underlying oxidation 11101. Next, the oxide film 103 for protecting ion implantation is
is formed, and using photoresist II (the photoresist film at this stage is not shown) as a mask, a p+ type 115 that will become an external base layer is formed. Furthermore, the above photoresist film is removed and a photoresist 11130 is added again.
1 is formed into a predetermined shape, and using this as a mask, a p-type layer 6 that will become an active base layer is formed by ion implantation.

In FIG. 5D, the photoresist film 301 is removed and then a passivation layer 401, typically phosphor glass (PSG), is deposited. A heat treatment is performed that combines the annealing of the base ion-implanted layer 5.6 and the baking of the PSGI 11401 to form an intermediate external base layer 51 and an active base layer 61. Next, PSGl1401
The contact hole 70 for the emitter electrode and the collector 1! An elm contact hole 80 is formed, and an n+ type layer 717 to become an emitter layer and an n+ type layer 8 to become a collector electrode extraction device are formed by ion implantation through this contact hole 70.80.

In FIG. 5E, each ion implantation g is annealed, the external base 152 and active base 1162 are completed, and the emitter layer 71 and collector electrode are taken out! 181 is formed. Metal silicide l11501 is formed in each of the openings 50, 70 and 80 to prevent electrical equipment from being damaged (for example, to prevent reactions between Am and Si). This metal silicide 11501 includes platinum silicide (Pt-8i)
, palladium silicide (pd-s+>, etc.) are used.A base electrode wiring 9, an emitter electrode wiring 10, and a collector electrode wiring 11 are formed on the metal silicide film 501 using a low resistance metal such as aluminum Ai.

[Problems to be Solved by the Invention] By the way, the frequency characteristics of a transistor depend on its collector capacitance, base resistance, and the like.

Therefore, in order to improve the frequency characteristics of the transistor, it is necessary to reduce these. The p+ type external base layer 52 in the conventional structure described above is provided to reduce base resistance.

However, this external base layer 52 has the disadvantage of increasing base-collector capacitance.

FIG. 6 is a plan pattern diagram of a transistor manufactured by a conventional method. The base resistance depends on the distance between the emitter layer 71 and the base electrode extraction opening 50 shown in FIG. In conventional devices, the base electrode arrangement 1iii
9 and the emitter electrode wiring 10. What is the spacing between the m-pole wiring 9,
This is the total distance including the protrusion from each of the 10 openings 50.70. Therefore, even if the precision of photoetching is improved and the distance between the 'R' wires is reduced, the above-mentioned protrusion will inevitably remain. Furthermore, the emitter M71 shown in FIG. Introduced! The base fIJ area between IWWA is inactive amr, increasing base-collector capacitance. In order to eliminate this non-active region, there is a method in which the emitter H71 is formed into a walled emitter F331 in contact with the wiring. However, this method also has various drawbacks.

78 to 7C are views showing a part of the cross section taken along the line XX in FIG. 6. Below, go to Figure i17 7C
Problems with the conventional walled emitter structure will be explained with reference to the drawings.

The seventh AIZ is a photoresist film 30 for base formation.
1 as a mask, the state in which boron, which is a p-type impurity, is implanted is shown. Next, it is necessary to remove the oxide w1103 on the emitter region 7 to form the contact hole. However, in this walled emitter structure, as shown in FIG. 7B, the boundary A of the isolation oxide film 102 is overetched when the oxide film is removed, and the emitter region becomes deeper as shown by B in FIG. 7C. . As a result, '2! There is a great risk that the controllability of the current amplification factor will deteriorate, and that a short circuit will occur between the emitter and the collector at the portion B shown in FIG. 7C.

Furthermore, as a method of reducing base resistance, a double base structure as shown in FIG. 8 is often used. However, the conventional method has the disadvantage that the base area increases due to the extraction of the base electrode, which leads to an increase in base-collector capacitance.

Further, in the conventional manufacturing method, the emitter base junction is made deeper than the surface of the external base region, which has the disadvantage that the current amplification factor becomes highly dependent on current. That is, in the very low current fIi region, there is a problem that current is absorbed by recombination or the like at the interface (emitter external base region, etc.), and the controllability of the current amplification factor deteriorates.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, reduce the base resistance and base-flefter capacitance, reduce the current dependence of the current amplification factor in the low current region, and furthermore provide a semiconductor device with good frequency characteristics. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be obtained.

[Means for Solving the Problems] A semiconductor manufacturing method according to the present invention includes a silicon film (single crystal) having an impurity diffusion source for forming an emitter region on a semiconductor substrate region that becomes an emitter region.

either amorphous or polycrystalline), and a base region is formed by partially implanting ions through this silicon film,
Next, using this silicon film, an emitter region is formed in the base region in a self-aligned manner.

Roughly, an insulating film is formed between the polysilicon film on the emitter region and the base electrode extraction region in a self-aligned manner to insulate the base-emitter electrode, and further the base electrode extraction region is formed in a self-aligned manner. . At this time, the emitter base junction is made shallower than the surface of the external base region and is formed at the same depth as the base electrode extraction portion.

[Function] Since the emitter region is formed in the base region in a self-aligned manner, it serves as a diffusion source for the emitter region and is connected to the metal electrode using a patterning mask such as a polysilicon film that forms the emitter region around the emitter silicon film in a self-aligned manner. A region with the minimum number of base electrodes is formed.

In addition, since only an insulating film is interposed between the silicon film on the emitter region and the metal wiring on the base region, the emitter base [1] is approximately the thickness of this insulating film and becomes small.

Furthermore, since the emitter region is formed by diffusing impurities from the polysilicon film, which serves as an impurity diffusion source, into the region that should become the emitter region, there is no need to form a contact hole for ion implantation when forming the emitter region. . Therefore, there is no need to remove the oxide film on the emitter region, and
Since over-etching does not occur at the 111t oxide film boundary, the emitter region and base region come into contact with the isolation region in a substantially parallel state.

In general, the emitter base junction is shallower than the surface of the external base region, so there is no current absorption due to recombination, and the current dependence of the current amplification factor in the low current region is small.

[Embodiments of the Invention] FIGS. 18 to 1J are cross-sectional views at main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 18 to 1J.

Referring to FIG. 1A, an n++ collector buried layer 2. n-type epitaxial layer 3. P-type layer 40 separation oxidation 111 for channel cut
02. An n+ type scattered layer 8 is formed which becomes the collector electrode area. The formation of each region is shown in FIGS. 5A and 5B.
This is done using a method similar to the conventional method shown in the figure. Next, underlay oxidation 11101 and nitridation 1 shown in FIG. 5B
After removing the silicon film 600.m201, a silicon film, preferably a polysilicon film 600. A nitride film 202 and a graphic film 104 are formed in this order on the surface of semiconductor substrate 1. Next, using the resist film 303 having a predetermined pattern shape as a mask, polysilicon [1600, i-1!20
2. t5. A multilayer film consisting of a 1o4 oxidized film is etched. By this patterning, the oxide film 104 is formed only in the m region, which will later become the collector electrode extraction layer and the emitter layer.
．． The nitrided WJ 202 and polysilicon film 600 remain.

See Figure 1B. Using the resist film 303 used for patterning the multilayer film in the above process as a mask, only the side walls of the oxide 11104 included in the multilayer film are side etched. As a result, the oxide film 104 is
600 and nitride 110202.

In FIG. 1C, selective oxidation is performed using the nitride 11202 as a mask to form an oxide film 105 in a predetermined region on the surface of the semiconductor substrate.

In FIG. 1D, etching is performed using the oxide film 104 as a mask to form a nitride film 202Ll15 and a nitride film 202.
The underlying polysilicon film 600 is buttered, and the silicon substrate (n'' layer 3) is etched to a predetermined thickness to make the base electrode thinner. This is to reduce the current dependence of the current amplification factor by forming the active base region-emitter region junction at the same depth as the base electrode extraction layer.In other words, the current dependence of the current amplification factor is reduced.
To eliminate current Φ absorption and to reliably control current amplification factor even in a low current region.

See Figure 1E. After the W oxide film 104 is removed, oxidation 1 is removed by selective oxidation using the nitride 111202 as a mask.
1106 is oxidized with polysilicon 11600! 11105
formed on the surface of the semiconductor substrate between the

At this time, selective oxidation is performed on the thinned polysilicon film 600.
This is done to such an extent that not only the n-type semiconductor region 3 thereunder is also slightly oxidized. Oxide film 106 is polysilicon 11
Covers the side wall of 11600.

In FIG. 1F, the nitride film 202 is first removed. Next, using the oxide 11106 as a mask, polysilicon 116 is
An n+ type impurity is introduced into 00 to form impurity-containing polysilicon m601. This allows polysilicon III
Reference numeral 601 serves as an impurity diffusion source for forming an emitter region.

In FIG. 1G, after the oxide film 106 is removed, p-type impurities are ion-implanted into ion-implanted layers 52'', 51.
52.53 are formed. At this time, the n-type semiconductor region from which the oxide film 106 has been removed becomes an external base layer.

On the other hand, the oxide film 105 is left to separate the base region and collector region. For this reason, oxide III 05
is formed as thick as 1μ in the selective oxidation shown in FIG. 1C, and as thin as 200 to 300 nil in the selective oxidation shown in FIG. 1E. In addition, the 0 layer 5 formed by ion implantation into the collector electrode extraction region
2-. 52 is an almost negligible amount of impurity due to the n+ diffusion layer 8 for taking out the collector electrode, and has almost no effect on the diffusion layer 8 for taking out the collector electrode. In addition, the ion-implanted region to become the active base layer under the polysilicon film 602 (polysilicon m601 implanted with p-type impurities) is exposed to external It is formed shallower than the region 53 that is to become the base layer.

In FIG. 1H, annealing of the p-type impurity ion implantation and diffusion of the n+-type impurity from the polysilicon film 602 into the silicon substrate 3 are performed simultaneously. As a result, the emitter region 7 is formed in a self-aligned manner, and
External base region 54 is formed slightly deeper and with lower resistance than active base region 6. Next, low m (800℃~900℃
'C8 degrees) oxidation is performed to form n+ type polysilicon II.
! ! A thick oxide 11107 is formed on 603° and 604, and a thin oxide 1108 is formed on the p+ type silicon substrate 54, respectively.

This utilizes the well-known fact that enhanced oxidation occurs at low temperatures in silicon and polysilicon containing high concentrations of n-type impurities such as phosphorus or arsenic.

In FIG. 11, an anisotropic etch (RIE) is performed on the oxide 11107.108 formed on the polysilicon 1603.604 to remove the thin oxide layer 108 on the extrinsic base region 54. Here, as a method for preventing short circuits of the base electrode to the emitter layer 7, a nitride film 203 is deposited on the entire surface shown in FIG. 1H, and only the side walls of the polysilicon film 603 are nitrided by anisotropic etching. After leaving the membrane 203, RIE (ReacN
There is a method of removing the oxide 11108 using a vel onbeam etching method and leaving an oxide film-nitride film on the sidewall of the polysilicon 91603, and this state is shown in FIG.

In FIG. 1J, first, the thick oxide film 108 on the collector electrode extraction region 8 is removed. Next, selective etching is performed in a predetermined region to form an emitter electrode contact hole 70 (not shown in FIG. 1J) and a collector electrode contact hole 80. Next, for example 1
Base electrode arrangement using a low resistance metal such as i19. Emitter electrode wiring 10 (not shown in FIG. 1J) and collector electrode wiring 11 are formed, respectively. As can be seen from FIG. 1J, the distance between the emitter and base is approximately between the oxide film 197 on the side of the polysilicon 11603 and the nitride ff12.
03, the base resistance is extremely small.

FIG. 2 is a plan pattern diagram of a transistor manufactured in one embodiment of the above-described invention, and corresponds to the plan pattern diagram of a conventional transistor shown in FIG. As shown in FIG. 2, emitter electrode arrangement 4111
The polysilicon 11603 connected to 0 serves as a diffusion source for the emitter region 7, so there is an emitter at A in the figure! Ti27 comes into contact with isolation oxide film 102. Furthermore, unlike the conventional method shown in FIG. 7, the emitter region 7 is formed in a self-aligned manner by impurity diffusion from the polysilicon film 603, so the base region is overetched and narrowed near the isolation oxide 11102. Never. That is, as shown in FIG. 3, the emitter region 70 and the active base region 6 are made of polysilicon l1.
Since they are formed simultaneously via the II 603, they are substantially parallel and the base width is constant. Therefore, the base area is significantly reduced due to the elimination of the protruding area between the emitter base IK poles and the fact that the protruding area of the base electrode is formed with the minimum area in a self-aligned manner, reducing the base-collector capacitance. be done. Furthermore, as seen in FIG. 2, since the base electrode arrangement ta9 is formed around the emitter region 7 on three sides, it automatically has a double base structure, which increases the base region. The base resistance is significantly reduced without any problems.

In addition, since the emitter junction is formed shallower than the surface of the external base end region and at the same depth as the base electrode extraction layer, there is no absorption of current due to recombination at the interface, and the current amplification factor in the low current region Dependency is reduced.

As another example, as shown in FIG. 4, instead of performing the n-type impurity diffusion for forming the collector electrode extraction region, the resist 1I3 is used in the step shown in FIG. 1G.
Using 04 as a mask, p-type impurity is selectively implanted after removing the oxidized portion 51106 of the base region, and annealing is performed. As a result, the n-type impurity is diffused from the polysilicon film 604 into which the n-type impurity has been implanted, and a C1 pole extraction layer can be formed.

Needless to say, is this invention a PNP? - It can also be applied to the manufacture of transistors.

[Efficacy of invention! l! ] As described above, according to the present invention, the silicon film on the emitter region and the metal electrode p! on the base w4 region! Since only an insulating film is interposed in the A section, the emitter-base spacing can be effectively reduced, and as a result, the base resistance is reduced and the frequency characteristics of the semiconductor device are improved.

In addition, impurities for forming an emitter region are diffused into the region to become the emitter region using the polysilicon film as a diffusion source to form the emitter region, and at the same time, impurities for forming the base region are further diffused into the semiconductor substrate. base vA
Since the region is completed, the isolation region boundary is not over-etched, and the emitter region and base IN region can be brought into contact with the isolation oxide film region in a substantially parallel state.

In addition, since the base electrode area is formed with a minimum area in self-alignment with the pattern for forming the emitter area, the inactive base area is significantly reduced.

Roughly speaking, the pattern size of the polysilicon film 603 forming the emitter layer becomes 1/3 or less from the pattern size of the resist 5303 in FIG. Micron wide emitter regions can be realized.

Furthermore, since the emitter junction is formed shallower than the surface of the external base region and has the same depth as the base electrode extraction layer, the current dependence of the current amplification factor is reduced. In the manner described above, it is possible to manufacture a semiconductor integrated circuit device with a frequency characteristic of 11 degrees.

[Brief explanation of drawings]

Figures 18 to 1J are 1 according to an embodiment of the present invention.
This is a factor that shows the cross-sectional structure at the main process steps of the manufacturing method. FIG. 2 is a plan pattern diagram of a transistor manufactured by the method of the present invention. FIG. 3 is a schematic cross-sectional view of the vicinity of the isolation oxide film boundary of the semiconductor device according to the present invention. Fourth
The figure is a cross-sectional structural diagram of a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIGS. 58 to 5E are cross-sectional views showing the state of a semiconductor device during main process steps of a conventional manufacturing method. FIG. 6 is a plan pattern diagram of a transistor manufactured by a conventional method. FIGS. 78 to 7C are schematic cross-sectional views of the vicinity of the isolation oxide film when the emitter layer is formed in contact with the isolation oxide film by the conventional method. FIG. 8 is a plan pattern diagram of a transistor with a double base structure manufactured by a conventional method. In the figure, 1 is a p-type silicon substrate, 2 is an n÷ type collector buried layer, 3 is an n-type epitaxial layer, 5 is a region to be an external base layer, 52°54 is an external base region, and 6.62 is a Active base region, 7.71 is an emitter region, 8.81 is a collector electrode extraction region, 9 is a base electrode wiring, 10 is an emitter electrode wiring, 11 is a collector electrode wiring, 50 is a contact hole for the base electrode, 70 is an emitter Contact hole for electrode, 80 is contact hole for collector electrode, 102 is isolation oxide film, 103, 104. . 105.106, 107.108 are oxide films, 201.2
02.203 is a nitride layer, 303 and 304 are photoresist layers, 401 is a passivation film, 600.601,
602, 603, and 604 are polysilicon films. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. show. Agent Masuo Oiwa 1st A
Figure IE Figure IF Figure 1 J Figure Name 2 Figure q, Base Denshasuke 10: Emi/N Denshi Hiroshi r+: Kore 7ri IJ! h=Japanese list bo3,6o+ :h-noshi'
) Figure 4 Figure 3 Figure SA Figure 58 Figure SD Figure 7
Kore 7 Ridenshi Dip Chen Jun, brother 77o, go: Tsun 77 to milk procedure amendment (
(Voluntary) Mr. Commissioner of the Patent Office, Field 1,
Indication of the case: Japanese Patent Application No. 143206/1982 2, Name of the invention: Method for manufacturing a semiconductor device 3, Person making the amendment 5, Detailed explanation column of the invention in the specification subject to amendment and Figure 1D of the drawings 6, Amendment Contents (1) "Next" on page 17, line 14 of the specification is corrected to "simultaneously." (2) Figure 1D of the drawing is as attached. that's all

Claims (3)

[Claims] (1) A method for manufacturing a semiconductor device formed on a semiconductor substrate of a first conductivity type and comprising an emitter region, a collector region, and a base region, wherein the semiconductor device is electrically connected to an adjacent semiconductor device by a separation region. a first step of forming a multilayer film which is insulated and includes a silicon film, a nitride film, and an oxide film deposited in this order on a predetermined region on the surface of the semiconductor substrate; a second step of side-etching only the oxide film to retreat inward from the nitride film and the silicon film; and selectively oxidizing the nitride film using the nitride film as a mask to form a first layer in a predetermined region on the semiconductor substrate. a third step of forming an oxide film; selectively anisotropically etching regions of the nitride film, the silicon film, and the semiconductor substrate at a predetermined depth using the side-etched oxide film as a mask; a fourth step of performing selective oxidation using the selectively etched nitride film as a mask to remove the silicon film on the surface of the semiconductor substrate between the silicon film and the first oxide film; a fifth step of forming a second oxide film; a sixth step of introducing impurities of the first conductivity type into the silicon film using the second oxide film as a mask; and taking out an electrode from the base region. a seventh step of removing the second oxide film on the region to become the base region; an eighth step of introducing impurities of a second conductivity type into the region to become the base region; and heating the semiconductor substrate. a ninth step of performing a process to diffuse the impurity of the first conductivity type from the silicon film into the region to become the emitter region to form the emitter region and simultaneously complete the base region; The substrate is subjected to low-temperature oxidation treatment to form a third layer on the sidewalls and top surface of the silicon film connected to the emitter region.
a tenth step of forming an oxide film on the semiconductor substrate; forming an emitter electrode through an opening penetrating the third oxide film formed in a predetermined region on the silicon film; A method for manufacturing a semiconductor device, comprising: an eleventh step of providing electrode wirings serving as a base electrode and a collector electrode on predetermined regions. (2) between the tenth step and the eleventh step, further comprising the step of forming a nitride film on the sidewall of the third oxide film formed on the silicon film connected to the emitter region; A method for manufacturing a semiconductor device according to claim 1. (3) In the fourth step, the predetermined depth of the semiconductor substrate that is selectively removed is a depth such that the emitter base junction is shallower than the surface of the external base region. A method for manufacturing a semiconductor device according to claim 1 or 2.