JP2567867B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device including a bipolar transistor.

[Conventional technology]

A technique described in Japanese Patent Publication No. 55-27469 is known as a highly integrated technique for a semiconductor integrated circuit device having a bipolar transistor. In this technique, a base region is formed in an island region protruding from a substrate, and a base lead electrode is formed in a side wall of the island region or a base region of a shoulder portion.
This technique is characterized in that the area occupied by the bipolar transistor can be reduced because the connection area between the base region and the base extraction electrode and the mask alignment margin area in the manufacturing process are not present in the planar direction.

The manufacturing method of the bipolar transistor to which the above technique is applied is as follows.

First, an island region protruding from the substrate is formed, and an insulating film is formed on the surface of the substrate and the surface of the island region. The substrate is formed by stacking an epitaxial layer on the surface of a semiconductor substrate (single crystal silicon substrate). The insulating film is a silicon oxide film formed by oxidizing the substrate surface, and the insulating film on the substrate surface is thicker than the island region because it is used as an element isolation insulating film.

Next, the insulating film on the sidewall or shoulder of the island region is selectively removed to form a connection hole.

Next, a base lead electrode is formed on the surface of the insulating film on the substrate so as to contact the surface of the epitaxial layer in the island region through the connection hole. The electrode for extracting the base is npn
In the case of the type bipolar transistor, it is formed of a polycrystalline silicon film into which a p-type impurity (B) is introduced. On the surface of the epitaxial layer where the electrode for extracting the base is connected,
The p-type impurities introduced into the electrode for extracting the base are diffused,
A part of the base region is formed.

Next, the surface of the electrode for extracting the base is oxidized to form a silicon oxide film on the surface of the electrode for extracting the base. The silicon oxide film is formed to define the emitter region and electrically separate the base extraction electrode and the emitter extraction electrode.

Next, a p-type impurity is introduced into the upper surface portion of the island region defined by the silicon oxide film on the surface of the base extraction electrode to form a base region.

Next, similarly, an emitter extraction electrode is formed on the upper surface of the island region defined by the silicon oxide film on the surface of the base extraction electrode. After that, n is formed on the main surface of the base region of the surface of the island region through the emitter extraction electrode.
A type impurity is introduced to form an emitter region.

In the bipolar transistor thus formed, the emitter region and the emitter extraction electrode can be formed in self alignment with the silicon oxide film on the surface of the base extraction electrode. That is, since the occupied area of the bipolar transistor can be reduced, the semiconductor integrated circuit device is characterized in that it can be highly integrated.

[Problems to be solved by the invention]

The present inventor has discovered the fact that short-circuits between the emitter and the collector frequently occur during the development of the aforementioned bipolar transistor. As a result of analysis by the present inventor, in the step of forming a silicon oxide film on the surface of the base extraction electrode, oxygen is passed through the insulating film (element isolation insulating film) exposed from the base extraction electrode to the substrate surface and the base. Since it was supplied to the lower surface of the extraction electrode, it was found that that portion was oxidized and stress was generated. This stress is generated on the substrate (single crystal silicon)
Cause crystal defects (dislocations) in the crystal, and the crystal defects induce the above-mentioned short circuit. This crystal defect frequently causes a short circuit between the emitter and the collector, but also causes a short circuit between the emitter and the base, between the base and the collector, and between the base and the substrate.
Therefore, there arises a problem that the electrical reliability of the semiconductor integrated circuit device including the bipolar transistor is lowered.

It is an object of the present invention to provide a technique capable of improving the electrical reliability of a semiconductor integrated circuit device including a bipolar transistor.

Another object of the present invention is a technique capable of reducing the occurrence of stress on the substrate due to the step of forming a silicon oxide film on the surface of a base extraction electrode in a semiconductor integrated circuit device including a bipolar transistor. To provide.

Another object of the present invention is to provide, in a semiconductor integrated circuit device including the bipolar transistor, a technique capable of reducing the occurrence of stress in the target substrate and preventing a short circuit between regions of the bipolar transistor. To do.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical invention disclosed in the present application is briefly described as follows.

An insulating film is formed on the surface of the substrate and the surface of the protruding island region of the substrate, and a base lead electrode is connected to the side wall of the island region or a shoulder thereof, and a silicon oxide film is formed on the surface of the base lead electrode. In a semiconductor integrated circuit device including a bipolar transistor for forming a substrate, on the surface of the insulating film (mainly an element isolation insulating film) exposed from the base lead electrode before or after the step of forming the base lead electrode. An oxidation resistant film is formed on.

The oxidation resistant film is formed so as to overlap the base extraction electrode.

[Action]

According to the above-mentioned means, in the step of forming the silicon oxide film on the surface of the base extraction electrode, it is possible to block the supply of oxygen to the substrate surface through the insulating film exposed from the base extraction electrode. Therefore, it is possible to reduce the occurrence of crystal defects due to stress on the substrate and prevent short circuits between the regions of the bipolar transistor. As a result, the electrical reliability of the semiconductor integrated circuit device including the bipolar transistor can be improved.

Further, in the step of forming a silicon oxide film on the surface of the base extraction electrode, it is possible to block the supply of oxygen from the end of the base extraction electrode to the substrate surface through the insulating film. It is possible to reduce the occurrence of crystal defects due to stress on the substrate and prevent short circuits between the regions of the bipolar transistor.

Hereinafter, the structure of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device including a bipolar transistor.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

Example of Invention

(Example I) A semiconductor integrated circuit device including a bipolar transistor according to Example I of the present invention is shown in FIG. 1 (a cross-sectional view of a main part).

As shown in FIG. 1, the bipolar transistor is formed on a surface portion of a substrate composed of a p ⁻ type semiconductor substrate 1 made of single crystal silicon and an n ⁻ type epitaxial layer 2 laminated on the surface thereof. ing. Bipolar transistor
Mainly, it is electrically isolated from other elements by the semiconductor substrate 1 and the element isolation insulating film (field insulating film) 5A. The element isolation insulating film 5A is formed on the surface of the substrate, substantially on the surface of the semiconductor substrate 1. The element isolation insulating film 5A is composed of a silicon oxide film formed by selectively oxidizing the surface of the semiconductor substrate 1.

The bipolar transistor has an n-type collector region,
It is of npn type composed of a P-type base region and an n-type emitter region.

The n-type collector region is mainly the n ⁺ -type buried semiconductor region (NB
L) 3, n ⁻ type epitaxial layer 2 and n ⁺ type potential raising semiconductor region 12. The buried semiconductor region 3 is a semiconductor substrate 1 in the bipolar transistor formation region.
It is provided at the interface between the epitaxial layer 2 and the epitaxial layer 2.
Buried semiconductor region 3 is configured to reduce the resistance value of the collector region. The potential raising semiconductor region 12 is an island-shaped epitaxial layer 2 formed by projecting a substrate.
It is provided on the main surface of (island region). The bottom of the potential raising semiconductor region 12 is configured to be connected to the embedded semiconductor region 3. The island regions are constructed by selectively etching the epitaxial layer 2 from the surface of the epitaxial layer 2 of the substrate to the surface of the semiconductor substrate 1. Insulating film on the sidewall of the island area
5B is provided. The insulating film 5B is composed of a silicon oxide film formed by selectively oxidizing the surface of the substrate, substantially the surface of the epitaxial layer 2.

In the n-type collector region, the collector wiring 19 is connected to the potential raising semiconductor region 12. The collector wiring 19 is connected to the potential raising semiconductor region 12 through a connection hole 18 formed in the interlayer insulating film 17 and a connection hole 11 formed in each of the insulating films 4 and 9A. The collector wiring 19 is formed of, for example, an aluminum film or an aluminum film containing a predetermined additive (Cu or Si). This collector wiring 19 is the first
It is formed by the layer wiring forming process.

The p-type base region is composed of a p ⁺ -type semiconductor region 8 and a p-type semiconductor region 13. The p-type base region is provided on the main surface portion of the epitaxial layer 2 in the island region. The semiconductor region 8 is formed with a high impurity concentration in order to reduce the contact resistance value with the base extraction electrode 7.

The p-type base region connects the base lead electrode 7 to the semiconductor region 8. The base extraction electrode 7 is connected to the semiconductor region 8 through a connection hole 6 formed in the insulating films 4 and 5B. The connection hole 6 is formed in the side wall or shoulder of the island region, and the base lead-out electrode 7 is drawn out in the plane direction (lateral direction) from the side wall or shoulder of the island region. The base extraction electrode 7 configured in this manner can eliminate the connection area in the plane direction with the p-type base region and the mask alignment margin area in the manufacturing process, so that the area occupied by the bipolar transistor can be reduced. There are features. The base lead-out electrode 7 is formed of, for example, a polycrystalline silicon film capable of forming a silicon oxide film (10) on its surface. A p-type impurity (B) for reducing the resistance value is introduced (or diffused) into the polycrystalline silicon film. The base extraction electrode 7 is formed in the first-layer gate wiring forming step. A base wiring 19 is connected to the base drawing wiring 7.

The n-type emitter region is composed of the n ⁺ -type semiconductor region 16. The n-type emitter region is provided on the main surface portion of the p-type base region formed in the island region. The n-type emitter region is formed in a region defined by the silicon oxide film 10 formed by oxidizing the surface of the base extraction electrode 7.
That is, the n-type emitter region is configured to be self-aligned with the base extraction electrode 7.

An emitter extraction electrode 15 is connected to the semiconductor region 16 which is an n-type emitter region. Emitter extraction electrode 15
Are connected to the semiconductor region 16 through the connection holes 14 formed by the silicon oxide film 10 and the insulating film 4. The emitter extraction electrode 15 is composed of a polycrystalline silicon film into which an n-type impurity (As or P) that reduces the resistance value is introduced. Since the emitter extraction electrode 15 is self-aligned with the silicon oxide film 10 on the surface of the base extraction electrode 7,
It is configured to be self-aligned with the base extraction electrode 7. The emitter extraction electrode 15 is formed in the second layer gate wiring forming step. An emitter wiring 19 is connected to the emitter extraction electrode 15.

Next, a method of manufacturing the bipolar transistor configured as described above will be briefly described with reference to FIGS. 2 to 14 (cross-sectional views of a main part shown in each manufacturing step).

First, n-type impurities are selectively introduced (or diffused) into the main surface portion of the bipolar transistor formation region of the p ⁻ type semiconductor substrate 1.

Next, as shown in FIG. 2, on the main surface of the semiconductor substrate 1,
The n ⁻ type epitaxial layer 2 is laminated to form a substrate. By forming this epitaxial layer 2, an n ⁺ type buried semiconductor region 3 is formed at the interface between the semiconductor substrate 1 and the epitaxial layer 2.

Next, the insulating film 4, the insulating film 20, and the insulating film 21 are sequentially stacked on the main surface of the epitaxial layer 2 to form the island region. The insulating film 4 is, for example, a silicon oxide film formed by oxidizing the main surface of the epitaxial layer 2, and is formed with a film thickness of about 500 [Å]. The insulating film 20 is, for example, a silicon nitride film formed by CVD or sputtering, and is formed with a film thickness of about 1000 [Å]. The insulating film 21 is, for example, a silicon oxide film formed by CVD or sputtering, and is formed with a film thickness of about 7000 to 8000 [Å].

Next, as shown in FIG. 3, the insulating films 21 and 20 are sequentially patterned so that the portions forming the island regions remain, thereby forming an etching mask. The patterning is performed by anisotropic etching such as RIE.

Next, the insulating film 22 as an etching mask is formed on the sidewalls of the insulating films 20 and 21. The insulating film 22 can be formed, for example, by subjecting a silicon nitride film formed on the entire surface of the substrate by CVD or sputtering to anisotropic etching such as RIE. The insulating film 22 is formed in self-alignment with the insulating films 21 and 20.

By the anisotropic etching, the insulating film 4 is also selectively removed, and the surface of the epitaxial layer 2 is selectively exposed.

Next, using the insulating films 21 and 22 as etching masks, the exposed epitaxial layer 2 is etched to form island regions, as shown in FIG. The etching is performed by using anisotropic etching such as RIE, for example, from the surface of the epitaxial layer 2 to the surface of the semiconductor substrate 1. The island region on the right side of FIG. 4 forms a potential raising semiconductor region of the collector region, and the island region on the left side forms a base region and an emitter region. After this, the insulating film 22
Is selectively removed, and thereafter, an insulating film 5B is formed on the main surface of the sidewall of the epitaxial layer 2 in the island region and on the surface of the semiconductor substrate 1. As the insulating film 5B, a silicon oxide film formed by oxidizing the main surfaces of the semiconductor substrate 1 and the epitaxial layer 2 is used.

The insulating film 5B is formed with a film thickness of, for example, about 500 to 1000 [Å].

Next, as shown in FIG. 5, an insulating film 23 as an oxidation resistant mask is formed on the sidewalls of the insulating films 21 and 20 and the sidewall of the epitaxial layer 2 which is an island region. Insulation film 23
Can be formed, for example, by performing anisotropic etching such as RIE on a silicon nitride film formed by CVD or sputtering.

Next, the insulating film 23 is mainly used as an oxidation resistant mask to form an element isolation insulating film 5A on the main surface of the semiconductor substrate 1. As the element isolation insulating film 5A, a silicon oxide film formed by oxidizing the main surface of the semiconductor substrate 1 is used. Element isolation insulating film 5A
Is formed with a film thickness of, for example, about 4000 to 6000 [Å]. After that, the insulating film 23 is selectively removed.

After that, using the insulating films 21 and 4 as an etching mask, the insulating film 20 is side-etched as shown in FIG. The side etching is, for example, isotropic etching. The side etching is performed on the epitaxial layer 2 at the connecting portion between the base region and the base extraction electrode.
The area where the main surface of the epitaxial layer is oxidized is reduced, and the epitaxial layer 2
This is performed to prevent crystal defects from occurring. In addition, the side etching is configured to reduce the connection resistance value between the base region and the base extraction electrode. Next, the insulating film 4 on the sidewall or shoulder of the island area on the left side of the figure and
5B is selectively removed to form a contact hole 6 exposing the surface of the epitaxial layer 2. The connection hole 6 is formed to connect the base lead electrode to the base region. The connection hole 6 is formed by etching using the etching mask made of a photoresist film and the film thickness difference between the element isolation insulating film 5A and the insulating films 4 and 5B.

Next, as shown in FIG. 7, a base lead-out electrode forming film 7A is formed on the entire surface of the substrate. Base extraction electrode formation layer 7A
Are formed so as to contact the surface of the epitaxial layer 2 through the connection holes 6. Base extraction electrode formation layer 7A
Is formed of a polycrystalline silicon film formed by CVD. A p-type impurity (B) that reduces the resistance value is introduced (or diffused) into this polycrystalline silicon film. The base lead-out electrode forming layer 7A is formed with a film thickness of, for example, about 500 to 1000 [Å]. By the step of forming the base lead-out electrode forming layer 7A, the surface of the epitaxial layer 2 is formed in the connection hole 6 portion.
P-type impurities are diffused from the base extraction electrode forming layer 7A,
A p ⁺ type semiconductor region 8 is formed. The semiconductor region 8 constitutes a part of the base region.

Next, a photoresist film is applied on the surface of the base extraction electrode forming layer 7A on the entire surface of the substrate. Since the photoresist film is formed thick in the concave portions and thin in the convex portions of the base lead-out electrode forming layer 7A, the substrate surface can be apparently flattened.

Next, the entire surface of the substrate is etched, that is, the photoresist film and the base lead-out electrode forming layer 7A are uniformly etched, and then the photoresist film is removed.
The etching is performed by anisotropic etching such as RIE, and is performed until the surface of the insulating film 21 is exposed as shown in FIG.

Next, the exposed insulating film 21 is removed by etching using the base lead-out electrode forming layer 7A as an etching mask.

Next, as shown in FIG. 9, the base lead-out electrode forming layer 7A is subjected to predetermined patterning to form the base lead-out electrode 7. The base extraction electrode 7 is formed by using anisotropic etching such as RIE.

Next, as shown in FIG. 10, an oxidation resistant film 9 is formed on at least the surface of the element isolation insulating film 5A exposed from the base extraction electrode 7. The oxidation resistant film 9 is formed of a composite film of a silicon oxide film 9A and a silicon nitride film 9B provided on the silicon oxide film 9A.
The silicon nitride film 9B is mainly configured to prevent oxygen from being supplied to the surface of the semiconductor substrate 1, the surface of the epitaxial layer 2 or the surface of the buried semiconductor region 3 through the element isolation insulating film 5A in the subsequent oxidation step. . The silicon nitride film 9B is formed by CVD or sputtering and has a film thickness of at least about 500 [Å]. Basically, the oxidation resistant film 9 is the silicon nitride film 9B.
It may be formed as a single layer. The silicon oxide film 9A is a silicon nitride film
It is configured to absorb the stress associated with stacking 9B.
When actually forming a bipolar transistor, it is preferable to use a composite film as the oxidation resistant film 9 in terms of generation of the stress. The silicon oxide film 9A is formed by CVD and is 500 to 2000
It is formed with a film thickness of about [Å].

Further, the oxidation resistant film 9 is formed so as to overlap with the end portion of the base lead-out electrode 7. This superposition oxidizes the surface of the base extraction electrode 7 in a later oxidation step,
When the silicon oxide film (10) is formed on the surface of the base lead-out electrode 7, the element isolation insulation at the end of the base lead-out electrode 7 is made when the silicon oxide film and the element isolation insulation film 5A come into contact with each other. Oxygen is supplied to the surface of the semiconductor substrate 1, the surface of the epitaxial layer 2 or the surface of the buried semiconductor region 3 through the film 5A, so that the supply of oxygen is blocked. Therefore, the oxidation-resistant film 9 and the end of the base extraction electrode 7 have at least a dimension corresponding to the film thickness of the silicon oxide film formed on the surface of the base extraction electrode 7 and a misalignment dimension in the manufacturing process. Add and superimpose.

Next, the oxidation resistant film 9 and the insulating film 20 exposed from the oxidation resistant film 9 are formed.
As a mask for oxidation resistance, a silicon oxide film 10 is formed on the exposed surface of the base extraction electrode 7 as shown in FIG. The silicon oxide film 10 is formed, for example, in an oxygen atmosphere at 900
It is formed at a temperature of [° C.]. Since the silicon oxide film 10 mainly electrically separates the electrode 7 for extracting the base and the electrode (15) for extracting the emitter, the silicon oxide film 10 is formed to have a film thickness of about 2000 to 4000 [Å].

Thus, the element isolation insulating film 5A is formed on the surface of the substrate, and the insulating film 5B is formed on the surface of the protruding island region of the substrate.
In a semiconductor integrated circuit device including a bipolar transistor in which a base extraction electrode 7 is connected to a side wall of the island region or a shoulder thereof, and a silicon oxide film 10 is formed on the surface of the base extraction electrode 7, After the step of forming the electrode 7 for base extraction, the oxidation resistant film 9 is formed on the surface of the inter-element isolation insulating film 5A exposed from the electrode 7 for base extraction, so that the silicon oxide film 10 is formed on the surface of the electrode 7 for base extraction. In the step of forming, it is possible to block the supply of oxygen to the substrate surface through the element isolation insulating film 5A,
It is possible to reduce occurrence of crystal defects due to stress on the substrate. If oxygen is supplied to the substrate,
As shown in Figure 11 with reference numeral 5C, the element isolation insulating film 5A
Grows locally, and stress concentrates on the 5D part indicated by the arrow. The reduction of the occurrence of the crystal defects can prevent a short circuit between the regions of the bipolar transistor, so that the electrical reliability of the semiconductor integrated circuit device can be improved.

Further, the oxidation resistant film 9 is formed so as to be overlapped with the base extraction electrode 7, so that oxygen is supplied to the substrate surface from the end portion of the base extraction electrode 7 through the element isolation insulating film 5A. It can be cut off.

Next, as shown in FIG. 12, the silicon nitride film of the oxidation resistant film 9 is formed.
9B is removed, and the insulating film 20 exposed on the upper part of the island region on the left side of the figure is removed.

Next, the silicon oxide film 9 above the island region on the right side of FIG.
A, the insulating film 20, and the insulating film 4 are sequentially removed selectively to form the connection hole 1
Forming a one. After that, n-type impurities (P) are introduced into the main surface portion of the epitaxial layer 2 through the connection hole 11, and n ⁺
A collector region 12 for raising the mold potential is formed. The n-type impurities are formed by ion implantation or diffusion.

Next, as shown in FIG. 13, a p-type semiconductor region 13 is selectively formed on the main surface portion of the epitaxial layer 2 in the left island region. The semiconductor region 13 is formed by introducing a p-type impurity (B) through the insulating film 4. The introduction of this p-type impurity is defined by the silicon oxide film 10 formed on the surface of the base extraction electrode 7, and is performed in self-alignment with the base extraction electrode 7. The semiconductor region 13 has the connection hole 6
It is connected to the p ⁺ type semiconductor region 8 formed by diffusing the p type impurity of the base extraction electrode 7 through.

Next, the silicon oxide film 10 is mainly used as an etching mask to selectively remove the insulating film 4 exposed above the left island region to form a connection hole 14. The connection hole 14 is formed in self-alignment with the silicon oxide film 10, that is, the base lead-out electrode 7.

Next, an emitter extraction electrode 15 is formed on the silicon oxide film 10 so as to be connected to the semiconductor region 13 which is the base region through the connection hole 14. The emitter extraction electrode 15 is
It is formed by introducing an n-type impurity (P) into the polycrystalline silicon film formed by CVD.

Next, as shown in FIG. 14, an n ⁺ type semiconductor region 16 which is an emitter region is formed in the main surface portion of the semiconductor region 13 where the emitter extraction electrode 15 is connected. Semiconductor area 16
Is formed by introducing an n-type impurity through the emitter extraction electrode 15. As a result, the n-type impurities are formed in self-alignment with the silicon oxide film 10, that is, the base extraction electrode 7. As described above, the bipolar transistor includes a p-type base region (semiconductor regions 8 and 13) for the base extraction electrode 7, and an emitter extraction electrode 15 and an n-type emitter region (semiconductor region 16) for the base extraction electrode 7. 2) can be formed by self-alignment, the mask alignment margin area in each manufacturing process can be substantially eliminated. As a result, the occupied area of the bipolar transistor can be reduced and the integration degree of the semiconductor integrated circuit device can be improved.

After the step of forming the semiconductor region 16 shown in FIG. 14, an interlayer insulating film 17 and a connection hole 18 are sequentially formed, and thereafter, as shown in FIG. 1, a collector wiring 19 and a base wiring 19 are formed.
And the emitter wiring 19 is formed. By performing these series of steps, the semiconductor integrated circuit device including the bipolar transistor of this embodiment is completed.

(Example II) Example II is another example of the present invention in which the oxidation resistant film 9 is formed before forming the electrode 7 for drawing out the base in the manufacturing method of the bipolar transistor.

A semiconductor integrated circuit device including a bipolar transistor that is Embodiment II of the present invention is shown in FIG. 15 (a cross-sectional view of a main part in a predetermined manufacturing process).

As shown in FIG. 15, in the bipolar transistor of the present Example II, the oxidation resistant film 9 is formed before the step of forming the base leading electrode 7 shown by the dotted line. That is, the oxidation resistant film 9 is formed after the step of forming the connection hole 6 shown in FIG.

Further, it is possible to form the connection hole 6 together with the step of forming the oxidation resistant film 9.

According to the present Example II, the same effect as that of Example I can be obtained.

Although the invention made by the present inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

For example, the present invention can be applied to a semiconductor integrated circuit device including a pnp type bipolar transistor.

The present invention is also based on a bipolar transistor and a complementary MI.
Semiconductor integrated circuit device (Bi-C) with SFET (CMOS) mixed
MOS) can be applied.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application.

In a semiconductor integrated circuit device including a bipolar transistor, it is possible to prevent a short circuit between regions caused by the step of forming a silicon oxide film on the surface of a base extraction electrode, thus improving electrical reliability. can do.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device including a bipolar transistor according to an embodiment I of the present invention, and FIGS. 2 to 14 are schematic views showing the semiconductor integrated circuit device in each manufacturing process. Partial cross-sectional view, FIG. 15 is a cross-sectional view of essential parts in a predetermined manufacturing process of a semiconductor integrated circuit device including a bipolar transistor that is Embodiment II of the present invention. In the figure, 1 ... Semiconductor substrate, 2 ... Epitaxial layer, 5A
...... Element isolation insulating film, 5B ... Insulating film, 7 ... Base extraction electrode, 3,8,12,13,16 ... Semiconductor region, 9 ... Oxidation resistant film, 9A ... Silicon oxide film, 9B: silicon nitride film, 10: silicon oxide film, 15: emitter extraction electrode, 19: wiring.

Claims (7)

(57) [Claims] 1. An insulating film is formed on a surface of a substrate and a surface of a protruding island region of the substrate, and the insulating film on a side wall of the island region or a shoulder thereof is selectively removed to form a base lead electrode. In a method of manufacturing a semiconductor integrated circuit device having a bipolar transistor for connecting and forming a silicon oxide film on the surface of the base extraction electrode, the base extraction electrode is formed before or after the step of forming the base extraction electrode. A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming an oxidation resistant film on the surface of the insulating film exposed from the base extraction electrode before forming a silicon oxide film on the surface of the. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the base lead-out electrode is formed of a polycrystalline silicon film. 3. The manufacturing of a semiconductor integrated circuit device according to claim 1, wherein the insulating film formed on the surface of the substrate and the surface of the island region is a silicon oxide film. Method. 4. The step of forming the oxidation resistant film is a step of forming a single layer of a silicon nitride film or a composite film in which a silicon nitride film is provided on a silicon oxide film. 5. A method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 3 in the above range. 5. The semiconductor integrated circuit device according to any one of claims 1 to 4, wherein the oxidation resistant film is formed so as to overlap the base extraction electrode. Production method. 6. A silicon oxide film formed on the surface of the base extraction electrode is used to electrically separate the base extraction electrode from the emitter extraction electrode or the collector extraction electrode. The method for manufacturing a semiconductor integrated circuit device according to any one of claims 2 to 5, which is a silicon oxide film formed by oxidizing the surface of the use electrode. 7. The emitter region or collector region of the bipolar transistor, the emitter extraction electrode or the collector extraction electrode is formed in self-alignment with the base extraction electrode. A method of manufacturing a semiconductor integrated circuit device according to claim 6.