JPH03284849A - Semiconductor and manufacture thereof - Google Patents

Abstract

PURPOSE:To decrease the collector-to-base distance for reduction in chip size by providing an insulator in a semiconductor substrate that is in contact with part of conducting films formed on base and collector regions. CONSTITUTION:First polysilicon layers 4 and 13a are formed on a base region 5 and a collector region 10 in a silicon substrate, respectively. These polysilicon layers each are in contact on one end with an insulator 22 having a depth of (d) in the substrate. A second polysilicon layer 7 for an emitter electrode is self-aligned with the first polysilicon layers. The depth (d) of the insulator is preferably 300-700nm. Since the respective polysilicon layers 4 and 13a of base and emitter are self-aligned in contact with the isolation insulator, no positioning allowance is required. Therefore, the space between the base and collector becomes narrow, and thus the total space requirement is reduced.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor device in which a base and an emitter are self-aligned using two-layer polysilicon, and a method for manufacturing the same, which reduces the element size by narrowing the collector-base spacing. The purpose of the present invention is to provide a structure of a semiconductor element that can reduce the chip size and a method for manufacturing the same.In a semiconductor device in which a base electrode and an emitter electrode are formed in a self-aligned manner, a base region and a collector region of a semiconductor substrate are provided. A conductive film is provided thereon, and an end portion of the conductive film is in contact with an insulator that partially protrudes into the semiconductor substrate between the base region and the collector region.

[Field of Industrial Application] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device in which a base and an emitter are self-aligned using two-layer polysilicon, and a method for manufacturing the same. be.

[Prior Art] Conventionally, in the manufacture of high-speed bipolar devices, emitters and bases are formed in self-alignment using two-layer polysilicon. Figure 5 shows the structure of a two-layer polysilicon bipolar transistor (hereinafter referred to as a device). In the figure, 1 is an N+ buried layer, 2 is a LOCOS, 4 is the first polysilicon layer and the base electrode, and 5a is the base. Contact region, 5b is the real base region, 6 is the emitter region, 7 is the second polysilicon layer and emitter electrode, 8 is the 5
10 is a collector contact region, and 11 is an AI2 wiring. In this structure, the base electrode is patterned using the first polysilicon layer, and the emitter window is also formed in a self-aligned manner using this pattern. This structure significantly reduced the base-collector capacitance and achieved high speed.

[Problems to be Solved by the Invention] In conventional elements, the emitter and base are self-aligned, but the base (4) and collector (10, 11) are separated by the LOCOS 2 formed at the beginning of the process. It is necessary to align the first layer of polysilicon with respect to LOCOS 2, and the base-collector interval has been increased to provide a margin for this alignment.

Therefore, in the conventional element, the area occupied by the base electrode and the collector electrode is the same as in a normal element. That is, even with a two-layer polysilicon element, the element area is almost the same as that of a conventional element, and the chip area is also almost the same.

As in the case of current semiconductor devices, as the degree of integration increases, the proportion of wiring that contributes to the performance of the circuit increases. Therefore, by narrowing the collector-base spacing, the present invention
It is an object of the present invention to provide a structure of a semiconductor element and a method for manufacturing the same, which can reduce the element size, shorten the wiring distance, and ultimately reduce the chip size.

[Means for Solving the Problems] The present invention provides a semiconductor device including an element in which a base electrode and an emitter electrode are formed in a self-aligned manner, in which a conductive film is present on a base region and a collector region of a semiconductor substrate, and A semiconductor device is provided, characterized in that the end portion of the conductive film contacts an insulator that partially protrudes into the semiconductor substrate between a base region and a collector region.

The present invention also includes a step of coating a continuous region including a base region and a collector region of a semiconductor substrate with a conductive film, and etching the conductive film and the semiconductor substrate along the base region and the collector region to make the semiconductor substrate conductive. a step of removing the film;
A method of manufacturing a semiconductor device is provided, which includes a step of forming an isolation region made of an insulator in a portion of a semiconductor substrate whose surface has been etched. Although the material of the conductive film may be a conductive material other than polysilicon, in the following description, an example in which the conductive film is made of polysilicon will be described.

[Effect] The principle of the present invention will be explained with reference to FIG.

As schematically shown in FIG. 1, a polysilicon film 4.13a is formed on the base region 5 and collector region 10 of the silicon substrate.
The present invention has a structure in which the polysilicon film 4.13a is in contact with the end portion of the insulator 22, which exists as the first layer of polysilicon and partially protrudes into the silicon substrate at a depth d between the base region and the collector region. provides. In the figure, 7 is a second layer of polysilicon that becomes an emitter electrode, and is formed in self-alignment with the first layer of polysilicon.

The above structure differs from the conventional double polysilicon structure in the following points.

■The structure of the present invention is a walled base structure. That is, the expansion of the base 5 during heat treatment of the emitter 6 is restricted by the isolation insulating film 22. Wal
The LED base structure has the effect of reducing the base area. Note that the depth d of the insulating film is generally 300 to 7
00 nm is preferred.

(2) The ends of the emitter/base polysilicon 4.13a are in contact with the isolation insulating film 22. On the other hand, in the conventional structure (see Fig. 2), the base polysilicon 4 (the fifth
) is raised and extends on the insulating film of LOGO32 at the boundary with the collector, so polysilicon 4 and L
It is necessary to provide a margin for alignment with the OGOS pattern. In the structure of the present invention, since the emitter/base polysilicon 4.13a is formed in a self-aligned manner with its end in contact with the isolation insulating film 22, alignment margin is not required and the base/collector distance is narrowed. It will be done. Due to the above-mentioned structural differences, the device area can be significantly reduced compared to a normal device. This will be explained with reference to FIG. 2, which shows the pattern of a normal element, and FIG. 3, which shows the pattern of the element of the present invention. In the figure, the dotted line is the first layer polysilicon pattern, the solid line is the LOGOSO pattern,
- The dotted chain line is the emitter window pattern. In conventional elements, a spacing of A was required considering the alignment margin between the spacing between two polysilicon patterns and the spacing between two LOGOS patterns, but according to the present invention, the spacing between two polysilicon patterns is Since Ao is required considering only the spacing between the silicon patterns, and A'<A, it is possible to significantly reduce the device size.

[Example] Hereinafter, the present invention will be described in detail with reference to FIGS. 4(A) to 4(0).

(A) P-silicon substrate 1 and N-epitaxial layer 3 (
An oxide (SiO□) film 24 with a thickness of 30 to 1100 nm is formed by thermal oxidation on the surface of the substrate on which a N buried layer 2 is provided in the middle of the N buried layer 2 (with a thickness of approximately 1.5 μm).
A nitride (SiN) film 25 with a thickness of about 1 μm is formed by CVD, and a PSG film 26 is grown on it to a thickness of about 1 μm (
(See Figure 4(A)).

(B) Cover the resist 27, and window 27° in the resist 27.
After that, the PSG film 26, nitride film 25 and oxide film 24 are etched using the resist 27 as a mask (see FIG. 4).
See B).

(C) After removing the resist 27, trenches 28 are formed in the N-epitaxial layer 3 and the P-silicon substrate 1 by anisotropic etching using the PSG film 26 as a mask (see FIG. 4(C)).

(D) Remove the PSG film 26, use the nitride film 25 as a mask, and oxidize the inner surface of the trench to a thickness of 50 to 300 nm.
Then, polysilicon 29 is deposited in the trench by CVD (see FIG. 4(D)). Polysilicon 9 is etched back and filled into the trench groove.

(E) Subsequently, leaving the nitride film 32 only in the element formation region,
Oxidizing the polysilicon 29 using the nitride film 32 as a mask,
A field oxide film 31 is formed (see FIG. 4(E)).

(F) The nitride film 32 formed in step (E) is removed using phosphoric acid boiling, the oxide film 24 is removed using a phosphoric acid etching solution, and a polysilicon layer 33, an oxide film 34 and a nitride film 35 are grown. let

The respective thicknesses are 33-0.2 to 0.5 μm, 34-
about 50 nm, 35-about 60-20 Q nm.

(G) The nitride film 32, oxide film 34 and polysilicon layer 33 formed in (F) are left only in the base region including the collector electrode and the base electrode (see FIG. 4(F)). At this time, a groove 36 is created by anisotropic etching, and the bottom of the groove 36 is made of N.
- Remove about 200 nm of epitaxial layer 3. In addition,
? 1136 is useful for separating the collector and base.

If the depth of the base is 1100 nm or less, this groove may not be formed.

(H) A nitride film 37 is grown to a thickness of about 30 nm over the entire surface,
RIE is performed to leave the nitride film 37 only on the side surfaces of the collector/base isolation trench 36 (see FIG. 4(H)).

(I) Using the nitride films 35 and 37 as a mask, the silicon exposed in the trench 36 is oxidized to grow the oxide film 22 to a thickness of about 400 nm (see FIG. 4(I)).

(J) Next, using a resist pattern, N-type impurities (
P) was implanted into the polysilicon layer 13a with an energy of 100
keV and 400 keV to a concentration of 10"cm-', annealed at about 900°C to create an NI collector contact 41, and then masking the upper part of the collector contact 21 with a resist pattern and forming a polyimide. P-type impurity (B) ions are implanted from the silicon layer 13b into the base region (see FIG. 4(J)).

(K) The oxide film 40 is formed by CVD to a thickness of 0.3 to 0.4μ.
m (see Figure 4 (J)).

(L) Forming the emitter window 21 (see Fig. 4 (K))
.

(M) Polysilicon layer 1 exposed in emitter window 21
3 and epitaxial silicon is oxidized to form an oxide film 43 (see FIG. 4 (M)), followed by ion implantation of P-type impurities at low energy of 30 keV or less to form the oxide film to form the internal base 56. 43.

(N) An oxide film 45 is formed on the side wall of the emitter window 21, and a second polysilicon layer 7 is formed to a thickness of 2 to form an emitter 6.
00 to 300 μm, and the ion concentration of N-type impurity is 1.
Ion implantation is performed so that the thickness is 0 cm or more (4th
(See figure (N)).

At this time, impurities may be mixed during polysilicon growth.

(0) The second polysilicon is left with the emitter as a pole, the collector contact window 45 and the base contact window 4.
6 (see Figure 4 (0)).

[Effects of the Invention] According to the present invention, by reducing the distance between the collector and the base, the element area can be reduced by up to 60% under the same design standard. Therefore, according to the present invention, a high-density device can be provided, and chip size and wiring load can be reduced. Furthermore, it is possible to reduce the collector resistance and the parasitic capacitance of the base, which are the parasitic resistances of the element.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of a pattern of a conventional double polysilicon element, Fig. 3 is an explanatory diagram of a pattern of a double polysilicon element of the present invention, and Fig. 4 (A). -(0) are process diagrams showing an embodiment of the method of the present invention, in which FIG. 4(A) is a step of forming an oxide film and a nitride film on a silicon substrate, and FIG. 4(B) is a step of forming an oxide film and a nitride film on a silicon substrate. , oxide film etching step, FIG. 4(C) is the trench groove forming step, FIG. 4(D) is the trench burying step, FIG. 4(E)
) is the oxidation process, Figure 4 (F) is the formation process of polysilicon, oxide film, and nitride film, Figure 4 (G) is the collector/base isolation trench formation process, and Figure 4 (H) is the collector/base isolation process. The process of forming a nitride film on the side surface of the trench, Figure 4 (I) is the process of forming an oxide film for collector-base insulation, Figure 4 (J) is the ion implantation process, and Figure 4 (K) is the process of forming the oxide film. Formation process, Figure 4 (L) shows emitter window formation process, Figure 4 (M) emitter window formation process, Figure 4 (N) shows emitter ion implantation process, Figure 4 (0)
5 corresponds to the second layer polysilicon growth and the collector and base contact window forming steps, respectively. FIG. 5 is a drawing showing the structure of a conventional double polysilicon element.

Claims (1)

[Claims] 1. In a semiconductor device including an element in which a base electrode and an emitter electrode are formed in a self-aligned manner, a conductive film exists on a base region and a collector region of a semiconductor substrate, and the base region and the collector region A semiconductor device having a structure in which an end portion of the conductive film contacts an insulator that partially protrudes into the semiconductor substrate in the middle of the semiconductor substrate. 2. A step of coating a continuous region including a base region and a collector region of a semiconductor substrate with a conductive film, and etching the conductive film and the semiconductor substrate between the base region and the collector region to remove the conductive film. and forming an isolation region made of an insulator in a portion of the semiconductor substrate exposed by etching.