JPS5915494B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a structure in which elements are separated by an isolation oxide film, such as an integrated circuit.

Generally, an integrated circuit includes a plurality of circuit elements electrically isolated from each other and formed on a single semiconductor substrate.

As this isolation method, a method of forming an isolation oxide film has been widely used in recent years because it enables high-speed integration and reduction of various parasitic capacitances. F5 Figure 1a
-f is a cross-sectional view of the semiconductor device at each step when manufacturing the semiconductor device by such a conventional method.

As a semiconductor device, a bipolar integrated circuit having an npn transistor as an element is used. As shown in FIG. 1a, first, a semiconductor substrate 1 made of p-type silicon is prepared, and a plurality of buried semiconductor regions 2 to be used as an nf-type collector buried layer are formed on the surface thereof, separated from each other. Furthermore, an n-type epitaxial layer 3 is formed entirely on this surface.
is formed to a predetermined thickness, and a thin silicon oxide film 10 is formed on the surface of this epitaxial layer 953 (basically, this is not always necessary).
A silicon nitride film 20 is formed on the surface of the silicon nitride film 20 as an oxidation-resistant film, then a resist 30 is formed on the surface of the silicon nitride film 20, and this resist 30 is selectively etched away to form a predetermined pattern. After forming into
Using the resist 30 as a mask, the silicon nitride film 20 is selectively etched away to form a desired pattern.

Next, as shown in FIG. 1B, after the resist 30 is completely removed, the silicon oxide film 10 is selectively etched away using the patterned silicon nitride film 20 as a mask. Thereafter, epitaxial layer 3 is selectively etched away to a predetermined depth using silicon oxide film 10 and silicon nitride film 20 as masks. Note that the etching in each of the above steps can be performed by a well-known dry etching method or wet etching method. Next, as shown in FIG. 1c, an isolation oxide film 11 is formed using the silicon nitride film 20 as a mask. At this time, if the thickness of the epitaxial layer 3 is, for example, 1.6 μm, the isolation oxide film 1
Collector buried layer 2 and the epitaxial layer portion above it are formed to have a thickness of 1.6 μm or more, and its bottom surface is in contact with p-type semiconductor substrate 1 in a portion where n+ buried semiconductor region 2 is not present. The upper side is due to the isolation oxide film 11, and the lower side is due to the Pn junction.
are isolated from each other. Next, the silicon nitride film 20 is removed as shown in FIG. A base layer 4 is formed in a part of the epitaxial layer 3 by ion implantation.

Next, as shown in FIG. 1e, after removing the entire resist 31, a resist 32 is formed on the surface and selectively etched away, and then the silicon oxide film 10 is selectively etched using the resist 32 as a mask. to be removed.

Further, using this resist 32 as a mask, n+ type impurities such as phosphorus or arsenic are ion-implanted to form an emitter layer 5 in a part of the base layer 4 and a collector electrode extraction layer 6 in a part of the epitaxial layer 3. . Next, Figure 1 f
As shown in the figure, the resist 32 is completely removed, a new resist is formed, and this is selectively removed by etching.
Using this as a mask, the silicon oxide film 10 is selectively etched away to form a base electrode outlet 10a at a part of the base layer 4. After that, the resist is completely removed and the isolation oxide film 11 is removed. It is possible to obtain a semiconductor device in which an Npn transistor is surrounded and insulated from other elements and is insulated from the other elements.

However, integrated circuits manufactured by such a conventional method have a wall emitter structure in which the emitter layer 5 is in contact with the isolation oxide film 11 as shown in FIG. There is a problem in that the leakage current between the

Therefore, in order to reduce leakage current in the prior art, it was necessary to use a general transistor structure that does not use a washed emitter structure, as shown in FIG.

However, if such a general transistor structure is used, there is a problem that the device area becomes large. The problems will be explained below with reference to FIGS. 2 to 5. Note that in FIGS. 2 to 5, corresponding parts to those in FIG. 1 are given the same numbers. Isolation oxide film 11 shown here
The thickness (t) of the emitter layer 5 and the distance w between the edge of the emitter layer 5 and the isolation oxide film 11 are determined by the collector-emitter leakage rate and emitter grounding amplification factor (H
FE). Figure 3 is a graph showing the relationship between the distance w and the leakage current generation rate when 100 transistors are arranged in parallel, with the thickness (t) as a parameter, and Figure 4 is a graph showing the relationship between the leakage current generation rate when 100 transistors are arranged in parallel, and the thickness (t) as a parameter. It is a graph showing the relationship between the distance w and the emitter grounding amplification factor. In Figure 3, characteristic a is t-1.6μm1 characteristic b is t=
The case of 1.2 μm is shown.

Here, it can be seen that the smaller the distance or the thicker the thickness (t), the higher the leakage current generation rate due to strain in the isolation oxide film. Also, in FIG. 4, the characteristic a
is Tl. 6 μm, and characteristic b shows the case of t-1.2 μm. Here, it can be seen that the smaller the distance w and the thicker the thickness (t), the lower the emitter ground amplification factor. Therefore, the thickness (t) of the isolation oxide film 11 is 1.6.
I! If the thickness is approximately 1.5 m, the distance (substance) must be 5 μm or more.

Further, if the thickness (t) of the isolation oxide film 11 is as thin as about 1.2 μm, the distance W may be 2 μm. Considering these points and considering the element area, the result is as follows.
In the case of a transistor when the distance (substance) is 5 μm,
As shown in FIG. 5, the area of the base layer 4 is 18×14=252μ, and the area of the transistor is 34×2.
2=748 μM2.

On the other hand, when the distance w is 2 μm, the area of the base layer 4 is 15×8120Itm2 as shown in the plan view in FIG.
, the transistor area is 28×16448μ. Therefore, if the distance is 2 μm, the area of the base layer will be 48% and the area of the transistor will be 6% compared to the case of 5 μm.
0% respectively. However, the first
As explained with reference to FIG. c, the isolation oxide film must be formed until it reaches the p-type semiconductor substrate, so it cannot be made thinner than a predetermined thickness.

Furthermore, if the epitaxy layer is made thinner, the withstand voltage characteristics between the collector base and further between the collector emitter will decrease. Therefore, in the conventional manufacturing method of semiconductor devices, it is impossible to reduce the distance between the edge of the emitter layer and the isolation oxide film, which has the disadvantage that it is difficult to increase the degree of integration. Ta.

The present invention has been made to eliminate these conventional drawbacks, and its purpose is to reduce the device area and improve the integration density without deteriorating the functional characteristics of the semiconductor device. An object of the present invention is to provide a method for manufacturing a semiconductor device.

Hereinafter, the present invention will be explained in detail based on examples. 7th
The figures are cross-sectional views of a semiconductor device at each step according to an embodiment of the method for manufacturing a semiconductor device according to the present invention.

It should be noted that the steps up to the state shown in FIG. 1a are the same as in the conventional process, so the explanation will be omitted. After forming the state shown in FIG. 1a, as shown in FIG. 7a, the resist 30 is left as it is, and the silicon nitride film 20 is etched away by a predetermined amount using a side etching phenomenon. Next, as shown in FIG. 7b, the resist film 30 is made loose by baking, and the silicon nitride film 2 is
The side-etched part of 0 is removed (this step uses a general negative type photosensitive resist film as the resist film 30), and it is exposed to 200'C3O in nitrogen (N2).
The heat treatment can be carried out easily because the resist film 30 will sag appropriately.

Next, using this sagging resist film 30 as a mask, the silicon oxide film 10 is selectively etched away.

Next, as shown in FIG. 7c, the epitaxial layer 3 is selectively etched away to a predetermined depth using the resist film 30 and/or thin oxide film 10 as a mask, and then the resist film 30 is completely removed.

Next, as shown in FIG. 7D, this wafer is heat-treated in an oxidizing atmosphere to selectively oxidize using the silicon nitride film 20 as a mask to form an isolation oxide film 11.

At this time, the isolation oxide film 11 is formed deeply until it reaches the p-type semiconductor substrate 1 in order to isolate the elements. According to this method, the oxide film 11a at the end of the isolation oxide film 11
Since this portion of the epitaxial layer 3 is not etched away due to the silicon oxide film 10, it is formed protruding from the substrate surface.

Approximately 55% of the area of the oxide film 11a is formed on the substrate surface, and the thickness is approximately 0.8 μm, assuming that the thickness of the isolation oxide film 11 is 1.6 μm. After this, for example, if you go through the steps shown in Figure 1 d-f in the same way as before, Npn
integrated circuits including shaped transistors can be obtained.

As a result, the isolation oxide film has a two-stage structure, consisting of a part that reaches the p-type semiconductor substrate and a part of the oxide film that is formed around it and surrounds a part of the base region and emitter region. Since the thickness of the portion below the substrate surface of the thick oxide film that surrounds the part can be made approximately 45% of the thickness of the isolation oxide film, the strain caused by the isolation oxide film is alleviated. The distance between the edge of the emitter layer and the isolation oxide film can be reduced without increasing the incidence of leakage between the collector and emitter and without reducing the emitter-to-ground amplification factor.

Therefore, for the same width of the isolation oxide film, it is possible to effectively reduce the transistor area without reducing the voltage resistance by thinning the epitaxial layer, thereby significantly increasing the integration density. You can improve. Furthermore, since the base area can be reduced, the collector-base capacitance can also be reduced, and the frequency characteristics of the transistor can be significantly improved.

In the above embodiment, an Npn type transistor was explained, but by replacing the n type and p type conductivity types, a Pnp
It can be similarly applied to type transistors, and furthermore, it can be applied to single elements as well as integrated circuits. As described above, according to the method of manufacturing a semiconductor device according to the present invention, by forming the isolation oxide film into a two-stage structure, the distance between the emitter layer and the isolation oxide film can be reduced, so that the integration density is high. In addition, since side etching is used to form the mask when forming the isolation oxide film into a two-stage structure, the number of masks required is the same as in the conventional example shown in Figure 1. Therefore, it can be manufactured with high precision and the yield is also good.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a semiconductor device at each step in a conventional semiconductor device manufacturing method, Figure 2 is a cross-sectional view of a general transistor, and Figure 3 shows the relationship between distance (substitution) and peak generation rate. Graph, Fig. 4 is a graph showing the relationship between distance (substance) and emitter amplification factor, Fig. 5 is a plan view of the transistor when the distance w is 5 μm, and Fig. 6 is a plan view of the transistor when the distance w is 2 μm. 7 are cross-sectional views of a semiconductor device at each step according to an embodiment of the method for manufacturing a semiconductor device according to the present invention. 1... Semiconductor substrate, 2... Buried layer,
3...Epitaxial layer, 4...Base layer, 5...Emitter layer, 6...Collector electrode extraction layer, 10, 10a... ...Silicon oxide film, 11, 11a...Isolation oxide film, 20.
...Silicon nitride film, 30, 31, 32...
...Resist.

Claims (1)

[Claims] 1. An oxidation-resistant film is formed on the surface of a semiconductor substrate, a resist film is formed on the oxidation-resistant film, and a predetermined pattern is formed by selectively etching away the resist film. Using this resist film as a mask, the oxidation-resistant film in the area where no mask is formed and the peripheral area under the mask is etched away using a side etching phenomenon, and then heat treatment is performed to loosen the resist film and make it oxidation-resistant. The part where the side-etched side film has been etched is covered with a resist film, and the sagging resist film is selectively etched away from the semiconductor substrate to a predetermined depth along the mask pattern. By selective oxidation treatment using the oxidation-resistant film as a mask, two steps are formed on the etched away portion of the semiconductor substrate and the surrounding semiconductor substrate portion where the oxidation-resistant film was not etched away. 1. A method of manufacturing a semiconductor device, comprising forming an oxide film having a structure. 2. Forming an oxidation-resistant film on the surface of the semiconductor substrate via an oxide film, etching the oxide film using the sagging resist film as a mask, and etching the semiconductor substrate using the oxide film as a mask. A method for manufacturing a semiconductor device according to claim 1. 3. A first semiconductor region of the first conductivity type, a plurality of buried semiconductor regions of the second conductivity type formed on the surface thereof, and a second semiconductor region of the second conductivity type formed on the upper surfaces of both of the regions. forming an oxide film on the etched away portion of the surface of the second semiconductor region of the semiconductor substrate up to the first conductivity type semiconductor region; 2. The method of manufacturing a semiconductor device according to claim 1, wherein an oxide film that does not reach the first conductivity type semiconductor region is formed in the portion where the oxidation-resistant film has been removed.