JP3224320B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a base region of a bipolar transistor.

[0002]

2. Description of the Related Art A conventional manufacturing method of this kind is disclosed, for example, in Japanese Patent Application Laid-Open No. Sho 59-107573. FIGS. 3 and 4 show sectional views of the manufacturing process (partly a plan view for reference). ) Are also described below.

First, as shown in FIG. 3A, a silicon nitride film is formed on a semiconductor substrate (a P-type silicon substrate in this example, hereinafter simply referred to as a substrate) 201 by a CVD (chemical vapor deposition) method. (An oxidation-resistant film, hereinafter simply referred to as a nitride film) 202 is formed, and an oxide film 203 which is also an insulating film is formed thereon by the CVD method.

Next, as shown in FIG. 3B, the oxide film 203 is etched to a predetermined area (element formation area) by a known photolithography (photolithography) etching technique. Using the mask 203 as a mask, the nitride film 202 is undercut (a method of etching so as to remove a portion below the periphery of the oxide film 203). Next, P ⁺ -type impurities are ion-implanted into the exposed substrate 201 to form a P ⁺ -type region 204 (so-called field implantation).

Next, as shown in FIG. 3C, the oxide film 203 is removed, and then selective oxidation (generally thermal oxidation) is performed using the nitride film 202 as a mask to form a field oxide film 205. I do.

Next, as shown in FIG. 3D, the nitride film 202 is removed, and impurities (for example, phosphorus) are ion-implanted at an energy of 350 keV and a dose of about 2 × 10 ¹² cm ^−2. By heating for about 6 hours, a collector region (n-type region) 206 as a bipolar transistor is formed.

Next, as shown in FIG. 3 (E), a nitride film 207 and an oxide film 208 are formed again by the CVD method, and a predetermined portion (collector outlet portion) is removed by etching by a known photolithographic etching technique. I do. And
The energy is 120 keV and the dose is 1 × 10
Impurity (for example, arsenic) is ion-implanted at about ¹⁴ cm ^-2 to form an n ⁺ -type region (collector extraction portion) 209.

Next, as shown in FIG. 4F, the oxide film 208 is removed, and then the remaining nitride film 207 is removed.
The selection is made oxide as a mask, the n ⁺ -type region 20
9 is covered with an oxide film 210. Next, the nitride film 207 is formed.
Is removed, and the nitride film 211 is again formed thereon.
Is formed by CVD, and a predetermined portion of the oxide film 212 (so as to leave at least a portion above the intrinsic base region) is removed by etching using a photolithography etching technique.
Using the oxide film 212 as a mask, etching is performed so that the nitride film 211 is undercut. Then, the oxide films 205, 210, 211 and the nitride film 2
12 or the like as a mask, an impurity (for example, boron) is implanted into the substrate 201 at an energy of 25 keV and a dose of 1 × 10 ¹⁵ c.
^Implanted at m ⁻² , the P ⁺ type region (as is well known, this is a base outlet (right side in the figure), a role of low resistance for the collector side junction (left side in the figure), the so-called external 213, which is the base).

Next, as shown in FIG. 4G, the oxide film 212 is removed, and then the remaining nitride film 211 is removed.
Is used as a mask to perform selective oxidation to form an oxide film 214 in a predetermined region (a region on the intrinsic base). Then
The nitride film 211 is removed, and impurities (for example, boron) are applied at an energy of 25 keV and a dose of 5.25 × 10 ¹² cm ^−2.
Is implanted to form a P-type region 215 serving as an intrinsic base region of the bipolar transistor (as is well known, a portion having the function of the original base as a transistor with respect to the aforementioned external base). I do.

Next, as shown in FIG.
Oxide film 210 on ⁺ type region 209 is removed, and collector contact portion 216 is opened. Next, an impurity (for example, arsenic) is ion-implanted above the intrinsic base region 215 at an energy of 40 keV and at a dose of 3.25 × 10 ¹⁵ cm ⁻² , and an n ⁺ -type emitter region 217 is implanted above the intrinsic base region 215. To form

Next, as shown in FIG. 4I, one of the external bases (P ⁺ -type regions) 213 (the side to be a base contact, the right side in the figure) is selectively removed by photolitho etching. Then, a base contact portion 218 is formed. Hereinafter, although not shown or described, a bipolar transistor portion is completed by forming a wiring, a protective film, and the like in necessary places.

[0012]

However, the conventional manufacturing method described above has a problem that the emitter-base junction breakdown voltage is deteriorated. The reason will be described below with reference to FIGS.

First, after the nitride film 211 is undercut-etched using the oxide film 212 as a mask, ion implantation for forming the P ⁺ type region 213 is performed. Boron ions penetrate the eaves of the oxide film 212. And the P ⁺ type region 21
3 are distributed under the eaves (FIG. 4 (F)).

The P ⁺ type region 213 and the emitter region 21
When the high-concentration region 7 comes into contact, a leak current is generated between the emitter and the base junction, and the junction breakdown voltage is deteriorated (FIG. 4).
(H)).

Furthermore, since the emitter-base junction breakdown voltage depends only on the undercut of the nitride film 211,
Due to the in-plane distribution of the amount of undercut, there is a problem that the breakdown voltage of the emitter-base junction is varied and the yield is deteriorated.

According to the present invention, the breakdown voltage of the emitter-base junction described above is (1) the P ⁺ type region 213 and the emitter region 2
(2) The problem that the junction withstand voltage varies due to the variation of the undercut amount within the wafer surface and between wafers due to the undercut amount of the nitride film 211 is eliminated. Therefore, P ⁺
Before the ion implantation for forming the mold region 213, the oxide film 212 is formed.
And a sidewall is formed on the side wall of the nitride film 211 to control the interval between the P ⁺ type region 213 and the emitter region 217 and reduce the dependency of the breakdown voltage of the emitter-base junction on the nitride film undercut. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a stable base junction breakdown voltage.

[0017]

SUMMARY OF THE INVENTION The present invention, for the purpose achieved, in the manufacturing method described above, P ⁺ -type region 21
3 is formed such that a sidewall of an insulating film is formed on the sidewalls of the nitride film 211 and the oxide film 212 before the ion implantation for forming the layer 3, and then a P ⁺ -type region is formed by ion implantation using the mask as a mask. It is.

[0018]

According to the present invention, as described above, before ion implantation for forming a P ⁺ type region (external base) region, a side wall is formed in a laminated film portion of a nitride film and an oxide film on an intrinsic base. Since the ion implantation is performed using the mask as a mask, a P ⁺ -type region is not formed below the eaves of the oxide film, and the emitter does not contact the P ⁺ -type region. The junction breakdown voltage between them is improved.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As a first embodiment of the present invention, a manufacturing process of a characteristic portion is shown in a sectional view of FIG. 1 and will be described below. FIGS. 7B to 7D are diagrams in which only a portion centered on the intrinsic base region portion is enlarged.

FIG. 1A shows the same process steps as FIG. 4F of the above-described conventional manufacturing process, and prior to this process, FIGS. 3A to 3E of the conventional process. The description is omitted because it is exactly the same.

As shown in FIG. 1A, the nitride film 101 (corresponding to 211 in FIG. 4F of the conventional example) is formed on the intrinsic base formation region, and the oxide film 102 (FIG. 4 (F) is selectively formed by photolithographic etching. In this embodiment,
When the nitride film 101 is etched using the oxide film 102 as a mask, the nitride film 101 is not undercut unlike the conventional example.

Next, as shown in FIG. 1B, a nitride film 103 which is an oxidation-resistant film is formed on the entire surface by a CVD method, and an oxide film 104 which is an insulating film is further formed thereon by the CVD method.
It is formed by a method.

Next, as shown in FIG. 1C, the oxide film 104 is etched by anisotropic etching, and a side wall is formed on the side walls of the nitride film 101 and the oxide film 102 (including the nitride film 103). A wall 105 is formed. Thereafter, using the portions of the nitride film 101 and the oxide film 102 on which the sidewalls 105 are formed as a mask, a P ⁺ type region, that is, an external base region 106 is formed by ion implantation as in the conventional example. At this time, the energy of the impurity (for example, boron) that penetrates the nitride film 103 is added to the energy of the conventional example as the energy of the implantation.
The impurity profile is made equal to the conventional example.

Next, as shown in FIG. 1D, the side wall 105 is removed. Thereafter, as shown in FIG. 1E, the nitride film 103 is removed, and then the oxide film 102 is used as a mask to form the nitride film 10 thereunder.
Undercut 1

Thereafter, the bipolar transistor portion is completed in exactly the same manner as in the steps after FIG. 4 (G) of the conventional example. Therefore, the description is omitted.

Next, the second embodiment of the present invention will be described below with reference to FIG. FIGS. 7B and 7C are enlarged views of only the portion centered on the intrinsic base region portion, as in the first embodiment.

FIG. 2A shows the same process steps as those of the first embodiment shown in FIG. 4F of the conventional manufacturing process. That is, the steps before this step are exactly the same as those of the steps of the conventional example shown in FIGS.

2A, the nitride film 301 (corresponding to 211 in FIG. 4F of the conventional example) is formed on the intrinsic base formation region, and the oxide film 302 (FIG. 4 (F) corresponding to 212) is selectively formed by a photolithographic etching technique. In the present embodiment, unlike the first embodiment, when etching the nitride film 301 using the oxide film 302 as a mask, the nitride film 301 is undercut as in the conventional example.

Next, as shown in FIG.
03 is generated on the entire surface by the CVD method. Then, FIG.
As shown in FIG. 3C, the oxide film 303 is etched by anisotropic etching to form a sidewall 304 on the side wall of the stacked film of the nitride film 301 and the oxide film 302. Then, using the portion of the laminated film (301, 302) on which the sidewall 304 is formed as a mask, impurities are ion-implanted to form a P ⁺ type region (external base) 305 as in the conventional example.

Thereafter, as shown in FIG. 2D, the side wall 304 is removed and the oxide film 3 is removed.
02 is also removed.

Thereafter, the bipolar transistor portion is completed in exactly the same manner as in the steps after FIG. 4G of the conventional example. Therefore, the description is omitted.

[0032]

As described above, according to the manufacturing method of the present invention, a sidewall is formed on the side wall of the nitride film and the oxide film formed on the intrinsic base region, and this is used as a mask. Therefore, the P ⁺ -type region, that is, the impurity ion implantation for forming the external base region is performed, so that the P ⁺ -type region extends under the oxide film formed by the undercut of the nitride film as in the conventional example. No distribution and no contact between the emitter and the external base. Therefore, the emitter
The leak current between the base junctions is reduced, the junction breakdown voltage is improved, and the junction capacitance can be reduced.

Further, by forming the sidewalls, particularly in the first embodiment, the nitride film is not undercut first, so that the distance between the nitride film and the P ⁺ type region can be easily controlled.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a first embodiment of the present invention.

FIG. 2 is a process sectional view of a second embodiment of the present invention.

FIG. 3 is a sectional view of a process of the prior art (part 1).

FIG. 4 is a sectional view of a process of the related art (part 2).

[Explanation of symbols]

101,103 nitride film 102,104 oxide film 105 sidewall 106 P ⁺ type region (external base)

Claims (2)

(57) [Claims] 1. A method of forming a bipolar transistor on a semiconductor substrate, comprising the steps of: (a) forming a first oxidation-resistant film and a first insulating film thereon on an intrinsic base region of the transistor formed on the semiconductor substrate; Forming a second oxidation-resistant film on the entire surface after selectively forming the first and second oxidation-resistant films, respectively, and (b) forming a laminated film of the selectively formed first oxidation-resistant film and the first insulating film. Forming side walls with a second insulating film on both side walls of the portion; (c) using the portion of the first oxidation-resistant film, the first insulating film, and the side wall as a mask, Introducing an impurity into the semiconductor substrate via the oxidation-resistant film; (d) removing the sidewall and the second oxidation-resistant film, and then using the first insulating film as a mask to form the first acid-resistant film; Undercutting the passivation film, including the above steps The method of manufacturing a semiconductor device according to symptoms. 2. A method of forming a bipolar transistor on a semiconductor substrate, comprising the steps of: (a) forming a first oxidation-resistant film and a first insulating film thereon on an intrinsic base region of the transistor formed on the semiconductor substrate; Selectively forming each of the following, and undercutting the first oxidation-resistant film using the first insulation film as a mask: (b) the first oxidation-resistant film and the first insulation film Forming side walls with a second insulating film on both side walls of the laminated film of (c), using a portion of the first oxidation-resistant film, the first insulating film, and the side wall as a mask; And (d) removing the side wall and the first insulating film. The method of manufacturing a semiconductor device according to claim 1, further comprising: