JP3373995B2 - High frequency semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a single transistor for high frequency and high breakdown voltage.

[0002]

2. Description of the Related Art Shallow base diffusion and fine emitter processing are inevitably required to promote higher frequency transistors. However, since there is a limit to the fine processing in the conventional emitter formation using the photolithography technique, a method is known in which the polysilicon layer as the emitter diffusion source is used as the emitter electrode as it is. Further, there is known a structure in which a high-concentration layer is formed in a contact portion with an electrode corresponding to a base region having a low concentration.

The applicant of the present application has proposed a method for realizing finer dimensions while adopting these structures (Japanese Patent Laid-Open No. 02-126644). Figure 5 shows the method.
Will be explained. (A) A LOCOS oxide film 2 is formed on the surface of the P-type epitaxial layer 1, and phosphorus (P) that forms the base region 3 is ion-implanted on the entire surface. Then, a base contact hole 4 and an emitter contact hole 5 are formed in the oxide film, a polysilicon layer 6 is deposited on the entire surface, and then boron for emitter formation is ion-implanted (FIG. 5A).

(B) The polysilicon layer 6 is photoetched to form an emitter electrode 7 on the emitter contact hole 5.
Phosphorus (P) is ion-implanted with the resist mask 7 left (FIG. 5B). Phosphorus is ion-implanted into the surface of the base region 3 through the base contact hole 4, and the others are masked by an oxide film or the like. (C) By performing heat treatment, boron is diffused from the polysilicon layer 6 to form the emitter region 8. Phosphorus ion-implanted through the base contact hole 4 compensates (cancels) boron from the polysilicon layer 6 and at the same time N +
A mold base contact region 9 is formed (FIG. 5C).

In the above method, since the base contact hole 4 and the emitter contact hole 5 are opened at the same time, further miniaturization is possible, and since the base contact region 9 is formed through the base contact hole 4, the base electrode is formed. The contact resistance can be reduced. Then, with a base diffusion depth of 0.5 μm and an emitter diffusion depth of 0.2 μm, high frequency characteristics of about ft = 3 GHz can be obtained.

[0006]

However, even with such a high frequency type element, the high withstand voltage characteristic (Vc
(bo, Vceo) is also required. The present invention provides a semiconductor device having a high frequency and a high breakdown voltage in order to satisfy such requirements.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, in which a base is formed in a stepwise manner in multiple steps, and the outermost base region is formed deeper than the LOCOS oxide film. By making the PN junction formed by the base region of the outermost shell contact the LOCOS oxide film at a position deeper than the bird's beak portion of the LOCOS oxide film,
A high frequency and high breakdown voltage semiconductor device is formed. Further, the present invention provides a simplified manufacturing method by forming a multi-step base region using a base emitter hole, an emitter contact hole, and an emitter diffusion source.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below.
An NP transistor will be taken as an example and described in detail with reference to the drawings. FIG. 1 is a sectional view showing a high frequency semiconductor device of the present invention. Reference numeral 11 is a P + / P type silicon semiconductor substrate which serves as a collector, and 12 is a LOCO formed on the surface of the substrate 11.
S oxide film, 13 is the surface of substrate 11 and LOCOS oxide film 12
A surface is a silicon nitride film, 14 is an N-type base region formed on the surface of the substrate, 15 is a P + type emitter region formed on the surface of the base region 4, 16a and 16b are boron-doped polysilicon layers, 17a, 17b and 17c are the first aluminum electrode layer, 17a is the emitter electrode,
b serves as a base electrode. Reference numeral 18 denotes a P + type channel stopper region, 19 denotes an interlayer insulating film such as a silicon nitride film, 2
Reference numeral 0 is a second electrode layer forming an electrode pad.

The LOCOS oxide film 12 is formed at a depth of about 0.6 μm from the surface of the substrate 11 to form a base region 1.
4 and the channel stopper region 18 is LOCOS.
The outer side of the oxide film 12 is surrounded in a ring shape. The surface of the substrate 11 (the surface of the semiconductor chip) is covered with the LOCOS oxide film 12 except for the region where the base region 14 and the channel stopper region 18 are formed. This reduces the stray capacitance between the second layer electrode 20 and the base or collector.

The emitter region 15 is a polysilicon layer 16a.
Similarly, the channel stopper region 18 is formed by solid-phase diffusion from the polysilicon layer 16b by the solid-phase diffusion from, and its diffusion depth is about 0.1 micron. The base region 14 is further subdivided into the first base region 14a located directly below the emitter region 15 and the first base region 14a.
Second base region 14b located outside the base region 14a, and third base region located outside the second base region 14b.
And a fourth base region 14d located outside the base region c and the third base region 13c and serving as the outermost peripheral base.
And.

The first base region 14a forms an EB junction with the emitter region 15 and is a diffusion region having a shallow diffusion depth of about 0.1 micron and a low impurity concentration in order to obtain high frequency characteristics. A cutoff frequency ft of about 2.0 GHz can be obtained at this diffusion depth. Second base region 14b
Has a higher impurity concentration and a deeper diffusion depth than the first base region 14a. Further outer third base region 14
c has a higher impurity concentration and a deeper diffusion depth than the second base region 13, and the base electrode 17b makes ohmic contact with the surface. These second and third base regions 14
b and 14c have a function of reducing the base resistance rbb from the first base region 14a to the base electrode 17b.

The fourth base region 14d has the deepest diffusion depth of the base region 14 of about 2 microns, and the LOC
It is formed deeper than the OS oxide film 12. Since the base region 14 has a structure in which the depth gradually increases stepwise, the curvature of the depletion layer formed in the CB junction is gradually relaxed, and finally the curvature of the CB junction in the fourth base region 14d having the deepest diffusion depth. Determines the final breakdown voltage of this transistor. According to the present invention, the emitter-collector breakdown voltage (Vceo) of about 140V can be obtained by providing the fourth base region 14d with a diffusion depth of about 2 microns.

By the way, the LOCOS oxide film 12 forms a bird's beak 21 at the boundary with the exposed surface of the substrate 11. An enlarged cross-sectional view is shown in FIG. Birds beak 21
The crystalline state of the substrate 11 in the vicinity is extremely bad. Therefore, when the terminal end of the base region 3 is formed near the bird's beak 21 as in the conventional example, the electric field of the CB junction is most concentrated, and the leakage in the opposite direction of the CB junction is caused. The current becomes extremely large. Therefore, in the present invention, the EB junction formed by the fourth base region 14d is formed by utilizing the deep formation of the outermost base region in order to obtain a high breakdown voltage.
2 bottom surface 22, that is, the surface of the substrate 11 and the bird's beak 2
By terminating the LOCSOS oxide film 12 at a position deeper than 1, the leak current IR can be significantly reduced as shown in FIG. 4 (B).

FIG. 2 is a sectional view for explaining the method of manufacturing the semiconductor device. Hereinafter, the steps will be described in order. Referring to FIG. 2A, first, a P-type substrate having a P + -type layer formed on the back surface, or a P + -type substrate is formed on the P + -type substrate by an epitaxial method.
A silicon substrate 11 having a mold layer is prepared. Board 11
After oxidizing the surface, a selective mask is formed by a normal photoetching technique, and phosphorus is thermally diffused on the surface of the substrate 11 to form the deepest fourth base region 14d.

Referring to FIG. 2B, a thin oxide film is formed on the surface of the substrate 11, a silicon nitride film is formed as an oxidation resistant film on the oxide film, and selective oxidation is performed to perform LOCOS oxide film 1.
Form 2. After that, the oxidation resistant film is removed, a clean oxide film having a film thickness of about 500 Å is formed on the surface of the substrate 11, masked with a photoresist film, and phosphorus is ion-implanted from above the oxide film to form a fourth base region 14d. Board 1 between
A first base region 14a having a low impurity concentration is formed on one surface.

Referring to FIG. 2C, the photoresist film is removed and the silicon nitride film 13 covering the LOCOS oxide film 12 is removed.
(SiN) is formed. A photoresist film is formed on the silicon nitride film 13, exposed and developed, and then the silicon nitride film 13 and the silicon oxide film thereunder are opened by dry etching to form an emitter contact hole 23a, a base contact hole 23b, and a channel stopper. The hole 23c is formed. The stripe line width of the emitter contact hole 23a is 0.8 μm.

Referring to FIG. 3A, a polysilicon layer is deposited on the entire surface of silicon nitride film 13. The polysilicon layer is either boron-doped or non-doped, and then boron is ion-implanted into the entire surface to be boron-doped. After that, a photoresist film 24 is formed on the polysilicon layer, and the polysilicon layer is photo-etched to form a polysilicon layer 16a covering the emitter contact hole 23a and a polysilicon layer 16b covering the channel stopper hole. The base contact hole 23b is exposed.

Referring to FIG. 3B, second and third base regions 14b and 14c are formed by ion-implanting boron from above while leaving the above photoresist film. At this time, the thickness of the oxide film on the surface of the substrate 11 is about 500.
Angstrom, the thickness of the silicon nitride film 13 is about 10
The accelerating voltage for ion implantation is set to a voltage that penetrates the oxide film and the silicon nitride film 13. In the emitter polysilicon layer 16a portion, the photoresist film 24 blocks the ions so that the ions do not reach the polysilicon layer 16a.
A second base region 14b is formed around a and penetrates the oxide film and the silicon nitride film 13. Since there is no obstacle at the base contact hole 23b, the second base region 14b is implanted deeper than the second base region 14b. To form the third base region 14c.

Thereafter, the photoresist film is removed, and the entire substrate 11 is heated by heat treatment in a nitrogen atmosphere to activate the ion-implanted impurities. By this heat treatment, boron is diffused from the boron-doped polysilicon layers 16a and 16b to the surface of the substrate 11 to form the emitter region 15 and the channel stopper region 18. Referring to FIG. 3C, an aluminum layer is deposited on the entire surface, and electrodes 17a, 17b, and 17c are formed by anisotropic dry etching. The electrode 17c was left for the purpose of preventing the polysilicon layer 16b from being removed by a chlorine-based etchant when the aluminum layer is etched.

Then, a silicon nitride film serving as an interlayer insulating film 19 is formed, and a through hole is opened in the silicon nitride film,
An aluminum layer is formed again on the insulating film to form an electrode pad. The above-described manufacturing method can simplify the process because the four-step base region can be formed by two thermal diffusions. Further, by leaving the electrode 17c above the polysilicon layer 16b during the dry etching of the electrode layer, it is possible to avoid the problem that the polysilicon layer 16b is removed. Further, the surface of the substrate 11 is covered with a silicon nitride film 13
By coating with, the moisture resistance can be improved, and the reliability can be improved by preventing the entry of sodium ions (Na +) into the oxide film.

In the above description, the PNP transistor is explained, but the NPN transistor can be similarly implemented by reversing the conductivity type.

[0022]

As described above, according to the present invention,
Since a very small base width Wb is obtained by the solid phase diffusion from the shallow and low impurity concentration active base and the polysilicon layer, it is possible to manufacture a transistor having a gain bandwidth product ft of 2 GHz or more. Further, since the second and third base regions 14b and 14c are formed around the first base region 14a which becomes the active base, the base resistance rbb can be reduced, so that the high frequency noise figure NF can be lowered.

Furthermore, outside the second and third base regions 14b and 14c for lowering the base resistance rbb, a fourth base region 14d having the deepest diffusion depth is formed continuously from these. Thus, by expanding the depletion layer in the collector-base junction and relaxing its curvature, Vceo = 100V or more can be achieved. Moreover, the fourth base region 14d formed to improve the breakdown voltage
Has no effect on the high frequency properties of the active base.

Further, by preventing the base-collector junction formed by the fourth base region 14d from contacting the bird's beak portion of the LOCOS oxide film 12, an increase in reverse leakage current of the base-collector junction is prevented. it can. The leak current hinders high breakdown voltage. Further, according to the manufacturing method of the present invention, the second and third base regions 14b are formed by one ion implantation. Since 14c is formed and the emitter region 15 and the channel stopper region 18 are formed by diffusion from the polysilicon layer, the process can be simplified.

Further, since the aluminum layer is left on the polysilicon layer 16b when the aluminum layer is etched, the problem that the polysilicon layer 16b is removed together with the aluminum etchant can be avoided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 3 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 4 is a sectional view (A) for explaining the present invention;
It is a characteristic diagram.

FIG. 5 is a cross-sectional view for explaining a conventional example.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/331 H01L 29/732

Claims (5)

(57) [Claims] 1. A one-conductivity-type collector layer, a LOCOS oxide film formed on the surface of the collector layer to a first depth from the surface of the collector layer, and the collector layer surrounded by the LOCOS oxide film. A base region of opposite conductivity type formed on the surface of the base region and an emitter region of one conductivity type formed on the surface of the base region, wherein the base region is a plurality of base regions having different diffusion depths.
At the bottom of the emitter region,
On the side, the diffusion depth increases stepwise so that it becomes the deepest, and the diffusion depth of the outermost base region is the LOC.
A high frequency semiconductor device having a base contact region which is larger than a first depth of an OS oxide film and is provided in a base region other than the base region below the emitter region and the outermost base region. . 2. The high frequency semiconductor device according to claim 1, wherein the PN junction of the outermost base region is in contact with the LOCOS oxide film at a position deeper than the bird's beak of the LOCOS oxide film. 3. The base, wherein the stepped base region is formed deeper than the shallowest first base region below the emitter region, and the first base region located outside the first base region. A second base region for reducing the base resistance of the region, a third base region for making contact with the base electrode, which is formed deeper than the second base region located outside the second base region, It comprises a fourth base region formed outside the third base region and deeper than the third base region for increasing the breakdown voltage between the base and the collector, and at least the fourth base region is The high frequency semiconductor device according to claim 1 or 2, wherein the LOCOS oxide film has a diffusion depth deeper than the first depth. 4. The impurity concentration of the fourth base region is
The high frequency semiconductor device according to claim 3, wherein the impurity concentration is higher than that of the first base region. 5. A step of forming a base region of opposite conductivity type having the deepest diffusion depth and a base region having the shallowest diffusion depth on the surface of the one conductivity type collector layer, and forming a LOCOS oxide film on the surface of the collector layer. And a step of forming an insulating film on the entire surface, a step of forming an emitter contact hole, a base contact hole, and a channel stopper region diffusion hole in the insulating film, and forming a polysilicon layer on the entire surface. Patterning and leaving it above the emitter contact hole and the channel stopper region diffusion hole and removing it from above the base contact hole; and stacking one conductivity type impurity in the polysilicon layer by doping, or A step of doping an impurity of one conductivity type all over the surface, forming a photoresist film on the polysilicon layer, and Patterning so that the photoresist film remains above the contact hole, and by doping an impurity of the opposite conductivity type from above the polysilicon layer, a second diffusion depth is formed in a portion penetrating the base contact hole. A step of forming a deep base region in the portion penetrating the insulating film by using the polysilicon layer as a mask, and forming a base region having a third deepest diffusion depth; and one conductivity type pre-doped from the polysilicon layer. Diffusion of impurities to form an emitter region and a channel stopper region, an electrode material is formed on the entire surface, and this is patterned to form a base electrode and an emitter electrode. A method of manufacturing a high-frequency semiconductor device, which further comprises the step of leaving the electrode material.