JP2003258216A - Method for manufacturing optical semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that in a method for manufacturing an optical semiconductor integrated circuit device in which a vertical pnp transistor and a photodiode are built, two elements having different characteristics are formed on the same substrate, and hence it is difficult to simultaneously improve the respective characteristics. <P>SOLUTION: The method for manufacturing the optical semiconductor integrated circuit device comprises the steps of forming a p<SP>+</SP>-type exudated region of an emitter region in a vertical pnp transistor 21 by exudating an impurity from an emitter retrieving electrode 41, and forming an n<SP>+</SP>-type diffused region 39 of a base leading region by ion implanting. Then, the region 39 is formed in the same step of forming the region 40 of the photodiode 22. Thus, a cell size of the transistor 21 can be reduced, and further high-frequency characteristics of the transistor 21 can be improved. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is directed to a method of manufacturing an optical semiconductor integrated circuit device in which a photodiode and a bipolar IC are integrated with each other, and an object thereof is to form the bipolar IC in a non-doped epitaxial layer which enables a high speed response of the photodiode. And

[0002]

2. Description of the Related Art An optical semiconductor integrated circuit device in which a light receiving element and a peripheral circuit are integrated to form a monolithic device can be expected to reduce costs unlike a hybrid IC in which the light receiving element and the circuit element are separately formed. Further, the hybrid IC described above has an advantage that it is resistant to noise caused by an external electromagnetic field.

A conventional structure of such an optical semiconductor integrated circuit device is, for example, Japanese Patent Laid-Open No. 09-01805.
One embodiment is described in Japanese Patent Laid-Open No. The structure will be described below with reference to FIG.

First, FIG. 12 is a sectional view of a conventional optical semiconductor integrated circuit device. Specifically, it is a sectional view of an IC incorporating a photodiode 1 and an NPN transistor 2. As shown in the figure, a first epitaxial layer 4 is formed on the P-type single crystal silicon semiconductor substrate 3 by vapor phase epitaxy so as to be non-doped and has a thickness of, for example, about 15 to 20 μm. Similarly, on the first epitaxial layer 4, a second epitaxial layer 5 laminated by phosphorus (P) doping by a vapor phase growth method is formed, for example, 4
It is formed with a thickness of about 6 μm. Then, the first and second epitaxial layers 4 and 5 are electrically separated into a first island region 7 and a second island region 8 by a P + type isolation region 6 that completely penetrates both. The photodiode 1 is formed in the first island region 7, and
The NPN transistor 2 is formed in the second island region 8.

In the first island region 7, an N + type diffusion region 9 serving as a cathode is formed over the entire surface of the second epitaxial layer 5, and the surface of the second epitaxial layer 5 is oxidized. The film 10 is formed. And
The cathode electrode 11 contacts the N + type diffusion region 9 through a contact hole which is partially opened in the oxide film 10. On the other hand, the isolation region 6 is used as the anode-side low resistance extraction region of the photodiode 1, and the anode electrode 12 contacts the surface of the isolation region 6. As a result, the photodiode 1 is constructed.

On the other hand, in the second island region 8, an N + type buried layer 13 is buried in the boundary between the first epitaxial layer 4 and the second epitaxial layer 5. This N
Second epitaxial layer 5 above + type buried layer 13
On the surface, the P-type base region 1 of the NPN transistor 2
4, an N + type emitter region 15 and an N + type collector region 16 are formed. Then, on each diffusion area, A
l electrode 17 contacts and extends over oxide film 10
The l wiring connects each element. As a result, the NPN transistor 2 is formed, the photodiode 1 forms an optical signal input section, and the NPN transistor 2 forms a signal processing circuit together with other elements.

Next, referring to FIGS. 13 and 14,
A method of manufacturing the above-described optical semiconductor integrated circuit device will be described.

First, as shown in FIG. 13, first and second epitaxial layers 4 and 5 are formed on a P-type single crystal silicon semiconductor substrate 3 by non-doping by vapor phase epitaxy.
To form. At this time, in the second island region 8, the first
An N + type buried layer 13 is formed between the epitaxial layer 4 and the second epitaxial layer 5. After that, a P-type impurity such as Hooker boron (BF ₂ ) is ion-implanted and diffused into the surface of the second epitaxial layer 5 in the second island region 8. By this step, the P type diffusion region 14
To form.

Next, as shown in FIG. 14, N-type impurities such as arsenic (A) are formed on the surface of the second epitaxial layer 5.
s) is ion-implanted and diffused. By this step, the P type diffusion region 14 is formed. By this step, the N + type diffusion region 9 of the photodiode 1 and the NPN transistor 2 are formed.
The emitter region 15 and the collector region 16 are simultaneously formed. After that, the electrodes 11, 12, and 17 are formed to complete the optical semiconductor integrated circuit device shown in FIG.

[0010]

As described above, in the conventional method of manufacturing an optical semiconductor integrated circuit device, as a method of forming the emitter region 15 of the NPN transistor 2, N-type impurities are added to the second epitaxial layer 5. For example, arsenic (As) is ion-implanted and diffused to form. At this time, for example, the emitter region 15 was formed in a desired region by using a photoresist as a mask. However, since the photoresist is used as a mask, there is a problem that it is difficult to miniaturize the cell size of the NPN transistor 2 because it is necessary to consider a mask shift to some extent.

As means for solving the above problems, there are the following methods. It forms an emitter extraction electrode made of, for example, polysilicon on the emitter region 15 formation region. Then, the impurity implanted into the emitter extraction electrode is heat-treated, and the emitter region is formed by the impurity leached from the electrode. Then, in order to reduce the cell size of the NPN transistor, it is conceivable to form the emitter extraction electrode and the base extraction electrode with polysilicon.

However, in this case, it is necessary to secure a certain distance between the emitter extraction electrode and the base extraction electrode. Therefore, even though it is used to solve the problem of reducing the cell size of the NPN transistor 1, the NPN transistor 1 can be made to seep out from the electrode even if it is used.
There is a problem that the cell size of the transistor 1 cannot be reduced. In addition, in the NPN transistor 2,
If the distance between the emitter region and the base region cannot be reduced, the parasitic resistance of the base cannot be reduced, resulting in a problem that excellent high frequency characteristics cannot be obtained.

[0013]

The present invention has been made in view of the above-mentioned conventional problems, and in the optical semiconductor integrated circuit device of the present invention, a step of preparing a semiconductor substrate of one conductivity type; Forming a plurality of substantially undoped epitaxial layers on a semiconductor substrate; forming an isolation region of opposite conductivity type penetrating the epitaxial layer, and isolating at least first and second island regions; Forming a one conductivity type vertical transistor in a first island region and forming a photodiode in the second island region, wherein the one conductivity type vertical transistor and the photodiode are formed. Forming a reverse conductivity type base lead region of the one conductivity type vertical transistor and a reverse conductivity type cathode region of the photodiode in the same ion implantation step. The features.

In the optical semiconductor integrated circuit device of the present invention, preferably, in the emitter region of the one-conductivity-type vertical transistor, the polycrystalline silicon formed on the upper surface of the emitter region is subjected to heat treatment to obtain the polycrystalline silicon. The impurity of one conductivity type injected into the epitaxial layer is thermally diffused and formed on the surface of the epitaxial layer.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view of an optical semiconductor integrated circuit device incorporating a vertical PNP transistor 21 and a photodiode 22 according to the present invention.

As shown in the figure, a first non-doped layer having a specific resistance of 100 Ω · cm or more and a thickness of 6.0 to 8.0 μm is formed on the P-type single crystal silicon substrate 23.
Epitaxial layer 24 is formed. On the first epitaxial layer 24, for example, a specific resistance of 100Ω
An undoped second epitaxial layer 25 having a thickness of not less than cm and a thickness of 6.0 to 8.0 μm is formed. Then, the substrate 23 and the first epitaxial layer 24
In the second epitaxial layer 25, the first island region 29, the second
The island region 30 and the third island region 31 are formed.

The isolation region 26 includes a first isolation region 29 vertically diffused from the surface of the substrate 23, a second isolation region 30 and a second epitaxial layer vertically diffused from the surface of the first epitaxial layer 24. It consists of a third isolation region 31 diffused from the surface of 25. Then, by connecting the three members, the first and second epitaxial layers 24,
25 is separated into islands. Further, since the LOCOS oxide film 32 is formed on the P + type isolation region 26, more element isolation is achieved. Here, LOCOS oxide film 3
2 can be replaced with a thick insulating film.

A vertical PNP is formed in the first island region 27.
A transistor 21 is formed and a photodiode 22 is formed in the second island region 28. The respective structures will be described below.

First, the vertical PNP transistor 21 formed in the first island region 27 will be described. As shown in the figure, this structure has P + so as to sandwich the boundary between the first epitaxial layer 24 and the second epitaxial layer 25.
A buried layer 33 of the mold is formed. Further, in this region, an N + type buried layer 34 is formed so as to overlap the P + type buried layer 33. Then, in the second epitaxial layer 25, the P + type well region 36 has a deep P
It is formed so as to overlap with the + type buried layer 33. In this P + type well region 36, a P + type diffusion region 38 is formed as a collector region, a P + type leaching region 42 is formed as an emitter region, and an N + type well region 37 is formed as a base region. Further, in the N + type well region 37, an N + type diffusion region 39 is also formed as a base leading region. Further, under the LOCOS oxide film 32 of the second epitaxial layer 25, an N + type diffusion region 35 is formed so as to overlap with an end of the N + type buried layer 34.

A silicon oxide film 43, a silicon nitride film 44 and an insulating layer 46 are formed on the surface of the second epitaxial layer 25. P + type seepage region 42
On the upper surface, the silicon oxide film 43 and the silicon nitride film 4 are formed.
A contact hole 45 is formed at 4. And
An emitter extraction electrode 41 made of, for example, polysilicon is formed on the upper surface of the P + type seepage region 42 through the contact hole 45. On the other hand, the collector electrode 47, the base electrode 49, and the emitter electrode 48 are formed through the contact holes formed by the above three persons. Although not shown, the N + type diffusion region 35 is connected to the power supply (VCC). for that reason,
Since the vertical PNP transistor 21 is surrounded by the N + type regions 34 and 35 to which the power supply potential is applied, the parasitic effect can be suppressed.

Next, the N + type diffusion region 35, which is a feature of the optical semiconductor integrated circuit device according to the present embodiment, will be described. In the present embodiment, the vertical PNP transistor 2
N + type diffusion region 35 so as to surround the region forming 1
Is formed. Specifically, N +
The mold diffusion region 35 is formed inside the isolation region 26. That is, on the collector region side, the P + type diffusion region 3
8 and the P + third isolation region 31 form an N-type region to form a PN junction region. As a result, it is possible to prevent the surface of the second epitaxial layer 25 between them from changing to P-type. As a result, the undoped first and second epitaxial layers 24, 2 are stacked.
It is feasible to form the vertical PNP transistor 21 in the cell 5. Then, this structure will be described below.

As described above, the vertical PNP transistor 21 is formed on the first and second epitaxial layers 24 and 25 which are laminated without doping. And the first
And a P + type well region 36 and an N + type well region 37 are formed in the second epitaxial layers 24 and 25,
A vertical PNP transistor 21 formation region is secured.
Therefore, when the N + type diffusion region 35 is not formed, for example, only the intrinsic layer exists between the P + type diffusion region 38 and the P + type isolation region 26. Although not shown, the silicon nitride film 44
On the upper side, for example, Al wiring and the like are formed. In this case, when a current flows through the wiring described above, the second
The surface of the epitaxial layer 25 inverts to a P-type region. As a result, the P + type diffusion region 38 and the P + type isolation region 26 are short-circuited, and the vertical PNP transistor 2
1 is a defective product. At this time, since the second epitaxial layer 25 is non-doped and has a high specific resistance,
For example, when a voltage of about 1 to 2 V is applied, the surface P
It flips over to the mold area. That is, the vertical PNP transistor 21 has a structure with very poor withstand voltage.

However, in the vertical PNP transistor 21 of the present embodiment, in the second epitaxial layer 25, the N + is formed in the intrinsic layer between the P + type diffusion region 38 and the P + type isolation region 26. A mold diffusion region 35 is formed. For this reason, a PN junction region is formed between the two, and even if the surface of the intrick layer changes to the P-type region, the two do not short-circuit. That is, P +
By forming the N + type diffusion region 35 in a ring shape inside the isolation region 26 of the type, the breakdown voltage of the vertical PNP transistor 21 can be significantly improved. Here, the N + type diffusion region 35 does not always need to be formed in a ring shape, and may be formed only in a region where the withstand voltage of the vertical PNP transistor 21 can be improved. That is, the vertical PNP transistor 21 is formed in a region surrounded by the substantially N + type diffusion region 35.

In the optical semiconductor integrated circuit device of the present invention, in the vertical PNP transistor 21, the emitter region is formed by thermal diffusion of impurities from the emitter extraction electrode 41, which will be described in detail in the manufacturing method. . On the other hand, the N + type diffusion region 39 serving as the base lead-out region is formed by ion implantation in the same process as the N + type diffusion region serving as the cathode region of the photodiode 22. As a result, only the emitter extraction electrode 41 made of polysilicon is formed on the surface of the second epitaxial layer 25. That is, by forming the emitter region using the emitter extraction electrode 41, it is not necessary to consider a mask shift or the like, and the cell size of the vertical PNP transistor 21 can be reduced. Furthermore, since the base lead-out region is formed by ion implantation, there is no electrode made of polysilicon on the surface thereof, and there is no hindrance to the reduction in the cell size of the vertical PNP transistor 21.
By not forming the electrode made of polysilicon on the base lead-out region, the distance between the emitter region and the base region can be reduced and formed. As a result, since the base region of the vertical PNP transistor 21 can also be formed in a reduced size, the parasitic resistance in the base region can be significantly reduced. With this structure, the vertical PNP transistor 21 having excellent high frequency characteristics can be realized.

Next, the photodiode 22 formed in the second island region 28 will be described. As shown in the figure, in this structure, the surface of the second epitaxial layer 25 has N
A + type diffusion region 40 is formed on almost the entire surface. Then, as described above, the first and second epitaxial layers 24 and 25 are formed undoped, and the N + type diffusion region 40 is used as a cathode region. And
The N + type diffusion region 40 includes the second epitaxial layer 25.
It is formed on the surface, and a silicon nitride film 44 and an insulating layer 46 are deposited on the surface. The cathode electrode 50 is connected through the contact hole formed in the silicon nitride film 44 and the insulating layer 46. on the other hand,
As described above, the substrate 23 is a P− type single crystal silicon substrate and is connected to the P + type isolation region 26. Although not shown, an anode electrode is formed on the surface of the separation region 26, and the substrate 23 connected to the separation region 26 is used as the anode region. The separation region 26 serves as an anode lead-out region.

The action of the photodiode 22 is as described below. For example, a VCC potential such as + 5V is applied to the cathode electrode 50 of the photodiode 22 and a GND potential is applied to the anode electrode thereof, so that the photodiode 22 is reverse biased. At this time, in the photodiode 22, as described above, the first and second epitaxial layers 24 and 25 are formed by non-doping, so that a depletion layer forming region having a wider width can be secured as compared with the conventional structure. can do. That is, the first and second epitaxial layers 2 formed without doping
Almost all the regions 4 and 25 can be used as the depletion layer forming region. Therefore, in the photodiode 22 of the present invention, the junction capacitance can be reduced, and the depletion layer can be expanded. And the photodiode 22
Since the depletion layer is widely formed in the state in which the reverse bias is applied to, the moving speed of the generated carriers generated by the incidence of light can be improved. As a result, high speed response of the photodiode 22 can be realized.

That is, in the photodiode 22, the characteristics of the photodiode 22 are improved as the non-doped epitaxial layers are laminated in multiple layers to secure a depletion layer forming region, although it depends on the intended use such as the wavelength of light. be able to. Further, by stacking a plurality of non-doped epitaxial layers, the epitaxial layer becomes a high resistance region. As a result, it is possible to suppress parasitic effects such as leakage current due to the parasitic transistor.

The optical semiconductor integrated circuit device according to the present invention is characterized in that in the photodiode 22, the silicon nitride film 44 is formed on substantially the entire surface of the N + type diffusion region 40 which is the cathode region. is there. As a result, as compared with the conventional structure in which the silicon oxide film is used as the antireflection film, the light transmittance on the upper surface of the photodiode 22 can be improved and the light sensitivity of the photodiode can be improved.

As described above, in this embodiment, the case where the non-doped epitaxial layer has a two-layer structure has been described, but it is not particularly limited to this structure. Similar effects can be obtained even when a plurality of non-doped epitaxial layers are stacked depending on the intended use of the photodiode. In addition, various modifications can be made without departing from the scope of the present invention.

A method of manufacturing an optical semiconductor integrated circuit device incorporating a vertical PNP transistor and a photodiode, which is an embodiment of the present invention, will be described below with reference to FIGS. . In the following description, the same components as those described in the optical semiconductor integrated circuit device shown in FIG. 1 are designated by the same reference numerals.

First, as shown in FIG. 2, a P--type single crystal silicon substrate 23 is prepared. Then, the surface of the substrate 23 is thermally oxidized to form an oxide film on the entire surface, for example, 0.03 to
The thickness is about 0.05 μm. Then, the first isolation region 29 of the isolation region 26 is formed by a known photolithography technique.
A photoresist having an opening formed in a portion where is formed is formed as a selection mask. Then, a P-type impurity such as boron (B) is ion-implanted at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² , and diffused. Then, the photoresist is removed.

Next, as shown in FIG. 3, the silicon oxide film formed in FIG. 2 is completely removed, and the substrate 23 is placed on the susceptor of the epitaxial growth apparatus. Then, the substrate 23 is heated to a high temperature of, for example, about 1000 ° C. by the lamp heating, and SiH ₂ Cl ₂ gas and H ₂ are introduced into the reaction tube.
Introduce gas. As a result, on the substrate 23, for example, a specific resistance of 100 Ω · cm or more and a thickness of 6.0 to 8.0 μm.
The first epitaxial layer 24 of about m is grown. Then, the surface of the first epitaxial layer 24 is thermally oxidized to form a silicon oxide film, for example, about 0.5 to 0.8 μm. Then, the oxide film corresponding to the N + type buried layer 34 of the vertical PNP transistor 21 is photoetched by a known photolithography technique to be used as a selective mask. Then, an N-type impurity such as phosphorus (P) is introduced at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ¹³ to 1.
Ion implantation is performed at 0 × 10 ¹⁵ / cm ² and diffusion is performed. At this time, the first isolation region 29 of the isolation region 26 is simultaneously diffused.

Next, as shown in FIG. 4, the silicon oxide film formed in FIG. 3 is completely removed. After that, the surface of the first epitaxial layer 24 is again thermally oxidized to form an oxide film on the entire surface, for example, about 0.03 to 0.05 μm.
Then, using a known photolithography technique, a photoresist having an opening is formed as a selection mask in a portion where the second isolation region 30 of the isolation region 26 and the P + type buried layer 33 of the vertical PNP transistor 21 are formed. . Then, a P-type impurity such as boron (B) is introduced at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ¹³ to.
Ion implantation is performed at 1.0 × 10 ¹⁵ / cm ² and diffusion is performed. Then, the photoresist is removed. At this time, the N + type buried layer 34 is simultaneously diffused.

Next, as shown in FIG. 5, first, all the silicon oxide film formed in FIG. 4 is removed, and the substrate 23 is placed on the susceptor of the epitaxial growth apparatus. Then, by heating the lamp, for example, 1000
A high temperature of about 0 ° C. is applied and SiH ₂ Cl ₂ gas and H ₂ gas are introduced into the reaction tube. Thereby, on the first epitaxial layer 24, for example, a specific resistance of 100 Ω · cm
As described above, the second epitaxial layer 25 having a thickness of about 6.0 to 8.0 μm is grown. Then, the surface of the second epitaxial layer 25 is thermally oxidized to form a silicon oxide film of, for example, about 0.5 to 0.8 μm. Then, the oxide film corresponding to the N + type diffusion region 35 of the vertical PNP transistor 21 is photo-etched by a known photolithography technique to form a selective mask. After that, N-type impurities,
For example, phosphorus (P) is ion-implanted at an accelerating voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² and diffused. At this time, the second isolation region 30 of the isolation region 26 and the P + type buried layer 33 are simultaneously diffused, and the first and second isolation regions 29 and 30 are connected.

Next, as shown in FIG. 6, the silicon oxide film formed in FIG. 5 is completely removed. After that, the surface of the second epitaxial layer 25 is thermally oxidized to form an oxide film on the entire surface, for example, about 0.03 to 0.05 μm. On this oxide film, a photoresist having an opening formed in a portion where the P + type well region 36 of the vertical PNP transistor 21 is formed is formed as a selection mask by a known photolithography technique. Then, a P-type impurity, for example,
Boron (B) is ion-implanted at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² , and diffused. Then, the photoresist is removed. At this time, the N + type diffusion region 35 is simultaneously diffused.

Next, as shown in FIG. 7, the third isolation of the P + type diffusion region 38 and the isolation region 26 of the vertical PNP transistor 21 is formed on the silicon oxide film formed in FIG. 6 by a known photolithography technique. A photoresist provided with an opening in a portion where the region 31 is formed is formed as a selection mask. Then, a P-type impurity such as boron (B) is introduced at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.
Ion implantation at 0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² ,
Spread. Then, the photoresist and the silicon oxide film are removed. At this time, the P + type well region 36 is also diffused at the same time.

Next, as shown in FIG. 8, first, a LOCOS oxide film 32 is formed on a desired region of the second epitaxial layer 25.
To form. Although not shown, the surface of the second epitaxial layer 25 is thermally oxidized to form a silicon oxide film on the entire surface.
For example, the thickness is about 0.03 to 0.05 μm. Then, a silicon nitride film is formed on the oxide film, for example, 0.0
The thickness is about 5 to 0.2 μm. Then, the silicon nitride film is selectively removed so that an opening is provided in a portion where the LOCOS oxide film 32 is formed. Then, using this silicon nitride film as a mask, an oxide film is attached from above the silicon oxide film by steam oxidation at about 800 to 1200 ° C., for example. At the same time, heat treatment is applied to the entire substrate 23 to form the LOCOS oxide film 32. In particular, by forming the LOCOS oxide film 32 on the P + type isolation region 26, more element isolation is achieved. Here, the LOCOS oxide film 32 is formed to have a thickness of about 0.5 to 1.0 μm, for example.

Next, after the silicon nitride film and the silicon oxide film are all removed, the second epitaxial layer 2 is again formed.
The surface of No. 5 is thermally oxidized to form a silicon oxide film 43 on the entire surface, for example, about 0.03 to 0.05 μm. A vertical type P is formed on the oxide film 43 by a known photolithography technique.
A photoresist having an opening in a portion where the N + type well region 37 of the NP transistor 21 is formed is formed as a selection mask. Then, an N-type impurity, for example, phosphorus (P) is added at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 ×.
Ion implantation is performed at 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² and diffusion is performed. Then, the photoresist is removed. At this time,
The P + type diffusion region 38 and the third isolation region 31 are simultaneously diffused. Then, the P + type isolation region 26 is formed by connecting the first, second and third isolation regions 29, 30, 31. In this process, LOCOS
Since the oxide film 32 can be used as a mask, N
The + type well region 37 can be formed with high positional accuracy.

Next, as shown in FIG. 9, according to the manufacturing method of the present invention, an N + type diffusion region 39 which is a base leading region of the vertical PNP transistor 21 and an N + type diffusion region 40 which is a cathode region of the photodiode 22 are formed. Are formed in the same process. First, an opening is provided on the oxide film 43 formed in FIG. 8 at a portion where the N + type diffusion region 39 of the vertical PNP transistor 21 and the N + type diffusion region 40 of the photodiode 22 are formed by a known photolithography technique. The photoresist is formed as a selective mask. Then, an N-type impurity, such as arsenic (As), is applied at an acceleration voltage of 80 to 120 keV and an introduction amount of 1.0 × 10 ¹³ to 1.
Ion implantation is performed at 0 × 10 ¹⁵ / cm ² and diffusion is performed. Then, the photoresist is removed. At this time, the N + type well region 37 is also diffused at the same time.

By this step, it is possible to realize a structure in which the distance between the emitter region and the base lead region of the vertical PNP transistor 21 is reduced. As described above, the effect of having this structure is referred to the description of the structure of the optical semiconductor integrated circuit device, and the description is omitted here.

Further, in order to reduce the cell size of the vertical PNP transistor 21, the base lead-out region is formed by ion implantation. However, by forming it in the same process as the N + type diffusion region 40 of the photodiode 22, the manufacturing cost is reduced. And the manufacturing time can be shortened.

Next, as shown in FIG. 10, first, the silicon oxide film 43 on the photodiode 22 is removed by a known photolithography technique. Then, a silicon nitride film 44 having a thickness of 450 to 450 is formed on the surface of the second epitaxial layer 25 by, for example, a CVD method at 800 ° C. for about 2 hours.
Deposit about 1000Å. By this step, the silicon nitride film 44 is formed as a single layer on the photodiode 22. As a result, as described above, in the photodiode 22, the silicon nitride film 44 can be used as the antireflection film, and the light sensitivity can be improved as compared with the conventional structure. Then, the vertical PNP transistor 21
A contact hole 45 for forming the emitter extraction electrode 41 of is made of polysilicon is formed.

Here, the contact hole 45 is formed by utilizing the difference in etching selectivity between the silicon nitride film 44 and the silicon oxide film 43. For example, the etching selection ratio between the silicon nitride film 44 and the silicon oxide film 43 differs by about 10: 1. Utilizing this characteristic, first, only the silicon nitride film 44 is etched by the first dry etching using a hydrofluoric acid-based etchant. At this time, the silicon oxide film 43 is used as an overetching protection film for the silicon nitride film 44. Then, the silicon oxide film 43 is etched by wet etching to form a contact hole 45. As a result, it is possible to prevent unevenness from being formed on the surface of the second epitaxial layer 25 due to overetching of the silicon nitride film 44.

Next, polysilicon 51 is deposited on the entire surface of the silicon nitride film 44 provided with the contact holes 45, for example, about 0.1 to 0.3 μm. Then, on the polysilicon 51, a photoresist having an opening formed in a portion where the emitter extraction electrode 41 of the vertical PNP transistor 21 is formed is formed as a selective mask by a known photolithography technique. Then, a P-type impurity, for example, Hooker boron (BF ₂ ) is added at an acceleration voltage of 30 to
75 keV, introduction amount 1.0 × 10 ^{15 to} 1.0 × 10 ¹⁷ /
Ion implantation is performed at cm ² , and diffusion is performed. Then, the photoresist is removed. At this time, the N + type diffusion regions 39, 4
0 is also diffused at the same time.

Next, as shown in FIG. 11, in the manufacturing method of the present invention, a P + type leaching region 42 which becomes an emitter region of the vertical PNP transistor 21 is formed by applying heat treatment to the emitter extraction electrode 41. First, a resist is formed as a selective mask on the polysilicon into which arsenic (As) has been implanted in the process of FIG. 10 by a known photolithography technique. Then, the vertical PNP transistor 2 is selectively etched by etching polysilicon.
The emitter extraction electrode 4 of 1 is formed.

Then, at this time, heat treatment is applied to the emitter extraction electrode 41 into which the impurities are implanted. As a result, P-type impurities are leached and diffused from the emitter extraction electrode 41. As a result, the emitter extraction electrode 41
A P + type seepage region 42 is formed in the lower region. With this manufacturing method, the individual cell size of the vertical PNP transistor 21 can be reduced. Further, as described above, the effect of this structure is referred to the description of the structure of the optical semiconductor integrated circuit device, and the description is omitted here.

After that, for example, a BPSG (Boron Phosp) is formed as an insulating layer 46 on the entire surface of the above-mentioned element.
ho Silicate Glass) film, SOG (S
A pin on glass) film or the like is deposited. And
A contact hole for forming an external electrode is formed by a known photolithography technique. External electrodes 47, 48, 4 made of, for example, Al are formed through the contact holes.
9 and 50 are formed, and the optical semiconductor integrated circuit device incorporating the vertical PNP transistor 21 and the photodiode 22 shown in FIG. 1 is completed.

In the above-described embodiment, the vertical PN
Although the optical semiconductor integrated circuit device incorporating the P-transistor and the photodiode has been described, it is not particularly limited to the above-mentioned form. In addition, the same effect can be obtained in an IC incorporating a photodiode and a peripheral circuit. In addition, various modifications can be made without departing from the scope of the present invention.

[0050]

First, according to the method for manufacturing an optical semiconductor integrated circuit device of the present invention, an epitaxial layer, which is laminated in a substantially non-doped multilayer on a semiconductor substrate, is divided into a plurality of island regions, and the island regions are separated. At least a vertical PNP transistor and a photodiode are formed therein. And vertical PNP
The emitter region of the transistor is formed by applying heat treatment to an emitter extraction electrode made of polysilicon and leaching impurities from the emitter extraction electrode. On the other hand, the base lead-out region of the vertical PNP transistor is formed by ion-implanting impurities. As a result, it is possible to form the emitter region and the base lead-out region of the vertical PNP transistor with the separation distance reduced as much as possible. As a result, the cell size of the vertical PNP transistor can be reduced, and the base parasitic resistance can be reduced, so that the vertical PNP transistor excellent in high frequency characteristics can be realized.

Secondly, according to the method of manufacturing an optical semiconductor integrated circuit device of the present invention, an N + type diffusion region which is a base lead-out region of a vertical PNP transistor and an N + type diffusion region which is a cathode region of a photodiode are formed. Can be formed in the same process. As a result, it is possible to realize a structure capable of obtaining the above-described effects, further reduce the manufacturing cost, and shorten the manufacturing time.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating an optical semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the method of manufacturing the optical semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating the method of manufacturing the optical semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 4 is a sectional view illustrating the method for manufacturing the optical semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the optical semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating the method of manufacturing the optical semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 7 is a sectional view illustrating the method for manufacturing the optical semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method for manufacturing the optical semiconductor integrated circuit device in the embodiment of the present invention.

FIG. 9 is a sectional view illustrating the method for manufacturing the optical semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 10 is a sectional view illustrating the method for manufacturing the optical semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating the method of manufacturing the optical semiconductor integrated circuit device according to the embodiment of the present invention.

FIG. 12 is a cross-sectional view illustrating an optical semiconductor integrated circuit device according to a conventional embodiment.

FIG. 13 is a sectional view illustrating the method for manufacturing the optical semiconductor integrated circuit device according to the conventional embodiment.

FIG. 14 is a sectional view illustrating the method for manufacturing the optical semiconductor integrated circuit device according to the conventional embodiment.

[Explanation of symbols]

21 Vertical PNP transistor 22 photodiode 23 P-type single crystal silicon substrate 24 First epitaxial layer 25 Second epitaxial layer 39 N + type diffusion region 40 N + type diffusion region 41 Emitter extraction electrode 42 P + type seepage area

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 4M118 AA10 AB01 BA02 CA05 EA01                       FC09 FC18                 5F003 BA11 BA97 BB08 BC08 BE07                       BE08 BJ12 BP21 BP31 BP46                       BS05                 5F082 AA06 AA08 AA24 BA02 BA04                       BA12 BA21 BA26 BA41 BA47                       BC01 BC11 DA03 DA10 EA02                       EA09 EA22

Claims (2)

[Claims] 1. A step of preparing a semiconductor substrate of one conductivity type, a step of forming a plurality of substantially non-doped epitaxial layers on the semiconductor substrate, and a separation region of an opposite conductivity type penetrating the epitaxial layer. And separating at least first and second island regions, and forming one conductivity type vertical transistor in the first island region and forming a photodiode in the second island region. In the step of forming the one conductivity type vertical transistor and the photodiode, the reverse conductivity type base lead region of the one conductivity type vertical transistor and the reverse conductivity type cathode region of the photodiode are formed by the same ion. A method for manufacturing an optical semiconductor integrated circuit device, which is characterized in that it is formed by an implantation process. 2. The emitter region of the one-conductivity-type vertical transistor is formed by subjecting the polycrystalline silicon formed on the upper surface of the emitter region to heat treatment so that the one-conductivity-type impurity implanted into the polycrystalline silicon is epitaxially grown. 2. The method for manufacturing an optical semiconductor integrated circuit device according to claim 1, wherein the layer surface is formed by thermal diffusion.