JPH02137262A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PURPOSE:To isolate a well region from a substrate, and make it possible to apply a back gate voltage different from a substrate voltage by forming an N<+> type buried layer on a semiconductor substrate and an epitaxial layer, and forming a P<+> type buried layer between the N<+> type buried layer and a P-type well region. CONSTITUTION:A third buried layer 18 is formed in the forming regions of a P-channel type MOS transistor 23 and an N-channel type MOS transistor 21, which buried layer is arranged between a semiconductor substrate 2 and an epitaxial layer 3. A fourth buried layer 19 of P<+> type is formed on a part of the third buried layer 18, so as to be in contact with the third buried layer 18. A P-type well region 20 is formed so as to be in contact with the fourth buried layer 19. The first MOS transistor 21 of N-channel type is formed in the well region 20. Thereby, the third buried layer 18 is isolated from a voltage of the semiconductor substrate 2, so that a back gate voltage different from the substrate voltage can be applied to the N-channel type MOS transistor 21.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention relates to complementary bipolar transistors and complementary MOS transistors.
Bi-CMO3 with transistors integrated on the same substrate
Concerning integrated circuits.

(b) Conventional Technology As semiconductor integrated circuits become more sophisticated and functional, composite devices that provide both analog and digital functions on the same chip are attracting attention.

One technology for realizing these circuit function requirements is Bi-0MO8 technology, which integrates bipolar transistors and MOS transistors on the same semiconductor substrate. This technology enables lower power consumption and higher integration of NO8 type integrated circuits,
This makes it possible to take advantage of the features of both bipolar integrated circuits, such as their high speed and current drive capability.

For example, FIG. 3 shows a cross-sectional view of a conventional semiconductor integrated circuit (101), in which (102) is a P-type semiconductor substrate, (103) is a P-type semiconductor substrate, and (103) is a P-type semiconductor substrate.
(104) is an N1 type buried layer provided in plural on the surface of the substrate (102), (105) is a buried layer (104) of the bipolar transistor section. A P+ type isolation region penetrates through the epitaxial layer (103) so as to surround each of the epitaxial layers (103), and (106) is an island region in which the epitaxial layer (103) is formed into an island shape by the isolation regions (105). (1
07) is the first vertical bipolar transistor NP
N transistor, (108) is one island region (106
), (109) is the base region (10
The same NPN transistor (10) formed on the surface of
7), and the collector contact region (110). (River) is a vertical PNP transistor, which is the second vertical bipolar transistor, and (112) is a vertical PNP transistor that overlaps the buried layer. (113) is a P type collector region formed from the surface of the island region (106) to the collector buried layer (112), (114) is formed on the surface of the collector region (113). (115) is a P-type emitter region formed on the surface of the base region (114), and (116) is a P-type collector contact region formed on the surface of the collector region (113). .Also, (11
7) is a LOGO8 oxide film for surface isolation, (118
) is a gate oxide film covering the epitaxial layer (103), (119) is a gate electrode provided on the gate oxide film (118), and (120) is a vertical type to form a P-channel MOS transistor (around). PNP transistor (1
These are P-type source and drain regions formed in the same process as the emitter region (115) of 11).

Furthermore, (122) is an N-channel type MOS transistor, (123) is a P" type buried layer formed on the surface of the substrate (102) in the same process as the collector buried layer (112) of the vertical PNP transistor (111), and (124) ) is the collector region (11) of the vertical PNP transistor (111).
P-type well region (125) formed in the same process as 3)
is the emitter region (10) of the NPN transistor (107)
These are N" type source and drain regions formed in the same process as 9).

(c) Problems to be Solved by the Invention In the above configuration, the P-type well region (124) is connected to the semiconductor substrate (102) via the P9-type buried layer (123).
), the MOS transistor (婬2)
The back gate voltage could not be applied to anything other than the substrate voltage.

For this purpose, the P+ type embedding J! When (123) is removed and an N-type epitaxial layer (103) is formed between the well region (124) and the substrate (102), there is a problem in that a parasitic transistor is generated.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes a P-channel type MO8I-transistor (E) and an N-channel type MMOS transistor.
One N''' type third buried layer 18) is formed on the semiconductor substrate (2) and epitaxial layer (3) corresponding to the region where the OS transistor (fu) is to be formed, and this buried layer ( This problem is solved by forming a P″ type fourth buried layer (19>) between the P type second well region (20) and the P type second well region (20).

(*) Effect As mentioned above, by providing the third buried layer (18),
Since the second well region (20) can be separated from the semiconductor substrate (2), the back gate voltage can be applied to the semiconductor substrate (2).
It can be anything other than voltage.

(Go) Example The present invention will be explained in detail below. First, Fig. 1 shows a Bi-C
The configuration of an MO8 integrated circuit (1) is shown.

This integrated circuit (1) first consists of a P-type semiconductor substrate (2), an N-type epitaxial layer (3) laminated on this semiconductor substrate (2), and a combination of the semiconductor substrate (2) and the epitaxial layer. (3), and the complementary bipolar transistor (NPN transistor) is provided between the transistor (4) and the P
N''-type first buried layer (6) and second buried layer (7) provided in the formation region of the NP transistor (5), and the first buried layer (6) and the second buried layer (7). Around the buried layer (7), a first island region (9>) and a second island region (9) formed by a P+ type isolation region (8) reaching the semiconductor substrate (2) from the surface of the epitaxial layer (3) are formed. A first vertical NP with an island region (10) and an epitaxial layer (3) of this first island region (9) as a lid.
N) - transistor (4) and here this first vertical NP
The N transistor <4) also has a P type base region (11
), an N3 type emitter region (12) and a collector contact region (13), and the second island region (
A first vertical PNP transistor (10) whose collector is a P-type first well region (14) formed in
) and here this first vertical PNP)-transistor (
The ear) also includes an N-type base region (15), a P+-type emitter region (16), and a collector contact region (17).
>, in contact with the third buried layer (18),
A P-type fourth buried layer (19) completely formed in a part of the third buried layer (18), and this fourth buried layer (19)
a P-type well region (20) formed in contact with a P-type well region (20), an N-channel type first MOS transistor (21) formed in this well region (20), and the first MOS transistor
a P-channel type second MOS transistor (23) adjacent to the transistor (KAI) via a LOGO8 oxide film (22) and formed in a region corresponding to a part of the third buried layer (18); Consists of.

The feature of the present invention lies in the N1 type third buried layer (18) in the above-described configuration. Since this third buried layer (18) is provided between the P3 type fourth buried layer (19) and the P type semiconductor substrate (2>), the semiconductor substrate (2)
It is separated from the voltage of Therefore, this N-channel type M
Since a back gate voltage different from the substrate voltage can be applied to the OS transistor (c), the threshold voltage can be made different.

Next, a method for manufacturing this semiconductor integrated circuit will be explained with reference to FIGS. 2A to 2H.

First, as shown in Figure 2A, the impurity concentration is 10'4 to 10
``atom/cm'' P-type silicon semiconductor substrate (
After forming a thermal oxide film on the surface of 2), the thermal oxide film is buttered to form N" type buried layers (6), (7), (
1B), and using this thermal oxide film pattern as a mask, add nitrogen such as antimony (Sb) or arsenic (As).
By selectively doping type impurities, N-type buried layers <6), (7), and (18) are formed.

Here (6) is the vertical first NPN transistor (4)
(7) is the second buried layer formed in the vertical second PNP transistor (21), and (18) is the first buried layer formed in the first MOS transistor (21). ) and a third buried layer formed over the entire second MOS transistor (23).

Next, the thermal oxide film on the surface of the substrate (2) is buttered again to open holes in the intended isolation region (8), and using this thermal oxide film pattern as a mask, P-type impurities such as boron (B) are doped. By this, N+ for bipolar transistor
A separation region (
8) Form the lower diffusion layer (31).

Next, as shown in FIG. 2B, boron (B), etc. The second transistor (5) is doped with P-type impurity.
) collector buried layer (32〉) and fourth buried layer (19
) to form.

Next, as shown in FIG. 2C, the thermal oxide film used to form the buried layer in the above step is completely removed to expose the surface of the substrate (2), and then the well-known vapor phase growth method is applied to the surface of the substrate (2). An N-type epitaxial layer (3) is laminated to a thickness of 2 to 5 .mu.m and a specific resistance of 1 to 5 .OMEGA..cITl. During this time, the previously doped impurity is normally re-diffused.

Next, as shown in the second diagram, an epitaxial layer (3) is formed.
A second layer is formed in the area corresponding to the collector buried layer (32) on the surface.
Vertical PNP transistor (5)
A first well region (14) serving as a collector region of the epitaxial layer (3) is provided in a region corresponding to a P'' type fourth buried layer (19) on the surface of the epitaxial layer (3). P-type impurities such as boron (B) are selectively ion-implanted to form the P-type second well regions (20).The conditions for ion implantation are an acceleration voltage of 80 to 100
Ke￥, dose amount 101! - IQ "cm-" is selected as appropriate.

Next, as shown in Figure 2E, boron (B>) is selectively diffused from the surface of the epitaxial layer (3) to a high impurity concentration, which is necessary to electrically isolate the bipolar transistor part from other elements. An upper diffusion layer (33) of the P4 type isolation region (8) is formed and connected to a lower diffusion layer (31) diffused upward from the surface of the substrate (2) to complete the isolation region (8). At the same time, the first well region (14), which becomes the collector region of the vertical PNP transistor (1), is transferred to the collector buried layer 32), and the P-type well region (14) of the N-channel type MO3)-transistor (21)
20) into the fourth buried layer (19) of P'' type until they are respectively connected.

The separation region (8) that diffuses from the surface of the epitaxial layer (3) has a surface concentration of 1018 to 1 due to high concentration diffusion.
In addition to using a diffusion region formed about 0° cm −”,
The same diffusion region as the P-type first well region (14) of the vertical PNP transistor (seat) may be used.Subsequently, a thermal oxide film (34) is formed on the surface of the epitaxial layer (3).
) and a non-oxidizing film such as a silicon nitride film by the CVD method are sequentially laminated, and the silicon nitride film is patterned to form an oxidation-resistant mask (35) covering the regions where each element is to be formed. Thereafter, P or N type impurity ions are implanted to form a channel cut region (not shown) for preventing inversion into the field region of the MOS transistor, if necessary.

Next, as shown in FIG. 2F, the buttered silicon nitride film (35) is used as an oxidation-resistant mask to
The surface of the epitaxial layer is selectively oxidized in a wet sail atmosphere at 0°C, and a LOCO8 oxide film (22 ) to form. Thereafter, the thermal oxide film (34) and the silicon nitride film (35) are removed to expose the surface of each element region, and thermal oxidation is performed again to form the gate oxide film (36) of the MOS transistor.

Next, as shown in FIG. 2G, a photoresist film is coated on the entire surface, exposed, and developed to form a resist pattern of a desired shape. Using this resist pattern as a mask, the first transistor (NPN) transistor (4) is formed. Boron (B) forming the P-type base region (11) is used at a dose of 10, for example.
Ion implantation is performed at +3 to 101acm-* and an acceleration voltage of 30 to 40 KeV. Subsequently, a resist pattern of a photoresist film is formed again, and phosphorus (P), which forms the N-type base region (15) of the PNP transistor (5) which is the second transistor, is applied at a dose of, for example, 10'' to 10''an.
-'', ion implantation is performed at an acceleration pressure of 30 to 50 KeV.Then, the ion-implanted P-type and N-type impurities are driven in to the respective required depths, and the P-type base region (
11) and an N-type base region (15) are formed. These drive-ins can be performed simultaneously by one heat treatment at about 1000°C. Further, the heat treatment is performed in a non-oxidizing atmosphere to avoid unnecessary growth of the gate oxide film (36). In addition, P-type and N-type base regions (11),
(15) may be formed immediately before forming the LOGO8 oxide film (22) or immediately before forming the gate oxide film (36).

Finally, as shown in Figure 2H, an undoped polycrystalline silicon layer with a thickness of 2,500 to 4,000 layers is deposited on the entire surface by the CVD method, and this polycrystalline silicon layer is doped with phosphorus as an N-type impurity. By doping at a predetermined concentration, an N+ type polycrystalline silicon layer is obtained. N
Since the type 3 polycrystalline silicon layer is used as the gate electrode (37) of the N-channel type MO8I-transistor (21) and the P-channel type MOS transistor (competition),
The impurity concentration is set so that the sheet resistance is about 30Ω/mouth. Then, the N+ type polycrystalline silicon layer is selectively removed by, for example, plasma etching or reactive sputter etching to form a gate electrode (37) on the gate oxide film (36) of the MOS transistor section.

Next, a photoresist is applied to the entire surface, exposed, and developed to cover all areas other than the area where the emitter region (16) of the Pf channel type MOS transistor section (23) and the vertical PNP transistor (5) will be formed with the resist pattern. In the channel type MO3) transistor part (?3), the gate electrode (37) and the LOCOS oxide film (22) are self-aligned as a love blocking mask, and in the vertical PNP transistor part (presentation), the resist pattern is used as a blocking mask. Boron (B) is ion-implanted into the P-type source of the P-channel MOS transistor (23),
A drain region (38) and a [type PNP transistor (5)
) and the P-type emitter region (16) are formed at the same time.Subsequently, the N-channel MOS transistor (21) is formed.
) part and the emitter region of the NPN transistor (4) (
12) Cover the area other than the area to be formed with a resist pattern again, and cover the gate electrode (37) and LOGO8 oxide film (22) in the N-channel MOS transistor (21) part, and use the resist pattern in the NPN transistor (4) part. Phosphorus (P) or arsenic (AS) is ion-implanted as a blocking mask to form the N-type source and drain regions (38) of the N-channel MOS transistor (21).
and the N-type emitter region (12) of the NPN transistor (4)
) are formed simultaneously. Incidentally, during the boron (B) ion implantation, the P-type collector contact region (17) of the vertical PNP transistor (5) and the N-type collector contact region (13) of the NPNh transistor (4) were simultaneously implanted with phosphorus (B).
P> or arsenic (As) is simultaneously formed by ion implantation. Then, the implanted P-type and N-type impurities are diffused by heat treatment at around 1000°C in a non-oxidizing atmosphere, and finally the h□ of the NPN transistor (4) and vertical PNP transistor (5) is Finally, a passivation film and electrodes are formed to complete the manufacturing process.

(g) Effect of the invention As is clear from the above explanation, the third buried layer (18
> with the P+ type fourth buried layer (19) and the semiconductor substrate (2
), a voltage other than the substrate voltage can be applied to the P type second well region (20) and the P+ type fourth buried layer (19). Therefore, the threshold voltage can be made different from the conventional voltage.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor integrated circuit according to the present invention, FIGS. 2A to 2H are cross-sectional views illustrating a method for manufacturing a semiconductor integrated circuit according to the present invention, and FIG. 3 is a cross-sectional view of a conventional semiconductor integrated circuit. It is a diagram.

Claims (3)

[Claims] (1) Complementary bipolar transistor and complementary MO
A semiconductor integrated circuit in which an S transistor is integrated on the same substrate, and this semiconductor integrated circuit comprises: a semiconductor substrate of one conductivity type; an epitaxial layer of an opposite conductivity type laminated on the semiconductor substrate; and the semiconductor. A first buried layer and a second buried layer of opposite conductivity types are provided between the substrate and the epitaxial layer and are respectively provided in the formation region of the complementary bipolar transistor, and between the semiconductor substrate and the epitaxial layer. A third buried layer of an opposite conductivity type provided in the formation region of the complementary MOS transistor, and around the first buried layer and the second buried layer, the semiconductor from the surface of the epitaxial layer. a first island region and a second island region formed by isolation regions of one conductivity type reaching the substrate;
A first vertical transistor whose collector is the epitaxial layer of the first island region, and a second vertical transistor whose collector is the first well region of one conductivity type formed in the second island region. a transistor; a fourth buried layer of one conductivity type formed in contact with the third buried layer and a part of the third buried layer; and a fourth buried layer of one conductivity type formed in contact with the fourth buried layer. a second well region, a first MOS transistor of a reverse conduction channel type formed in the second well region, and a third MOS transistor adjacent to the first MOS transistor via a LOCOS oxide film; a second MOS transistor of one conductive channel type formed in a region corresponding to a part of the buried layer of the semiconductor integrated circuit. (2) separating the fourth buried layer from the semiconductor substrate;
2. The semiconductor integrated circuit according to claim 1, further comprising a first MOS transistor whose threshold voltage is changed by changing a back gate voltage. (3) Complementary bipolar transistor and complementary MO
A method for manufacturing a semiconductor integrated circuit in which an S transistor is integrated on the same semiconductor substrate, the first transistor being of an opposite conductivity type formed on the surface of a semiconductor substrate of one conductivity type in the formation region of the complementary bipolar transistor. a third buried layer of an opposite conductivity type formed in the formation region of the complementary MOS transistor;
a step of depositing an impurity to form a buried layer and a lower diffusion layer of an upper and lower isolation region of one conductivity type formed around the second buried layer; depositing impurities to form a collector buried layer and a fourth buried layer of one conductivity type, respectively, on a region of the buried layer; forming an epitaxial layer of opposite conductivity type on the semiconductor substrate; An impurity of one conductivity type that forms a first well region and a second well region of one conductivity type is diffused into the surface of the epitaxial layer corresponding to the buried layer and the fourth buried layer, and A region is formed to connect the collector buried layer and the second well region to the fourth buried layer, respectively, and at the same time, an upper diffusion layer of one conductivity type is formed on the surface of the epitaxial layer corresponding to the upper and lower separation regions. forming a first base region of one conductivity type in the first island region of the epitaxial layer; forming a second base region of opposite conductivity type in the well region; forming gate electrodes of the complementary MOS transistors on the epitaxial layer; a second emitter region of a conductivity type, forming the source and drain regions of the MOS transistor of one conductivity channel type, and a first emitter region of an opposite conductivity type provided in the first base region; A method for manufacturing a semiconductor integrated circuit, comprising the step of forming source and drain regions of the channel-type MOS transistor.