JP2698088B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate.
The present invention relates to a method for manufacturing a semiconductor device realizing a MOS transistor.

(B) Conventional technology With the advancement of high performance and high function of a semiconductor integrated circuit, a composite device in which an analog function and a digital function coexist on the same chip is receiving attention. One technique for realizing such a demand for circuit functions is the Bi-CMOS technique in which a bipolar transistor and a MOS transistor are integrated on the same semiconductor substrate. This technology can make use of the characteristics of both the low power consumption and high integration of a MOS integrated circuit and the high speed and current drive capability of a bipolar integrated circuit.

2A to 2G show a Bi-CMOS technology disclosed in Japanese Patent Application No. 62-95560, for example.

First, as shown in FIG. 2A, an N ⁺ -type buried layer (32), a P ⁺ -type buried layer (33) and a lower isolation region ( 34 ) are formed on the surface of a P-type semiconductor substrate (31). 35), and an N-type epitaxial layer (36) is formed on the entire surface of the substrate (31) to a thickness of, for example, 5 μm by a known vapor deposition method.

Subsequently, as shown in FIG. 2B, the epitaxial layer (36)
After ion implantation of boron (B) for forming a P-well (38) of an N-channel MOS transistor ( 37 ) on the surface,
The P ⁺ type upper isolation region (39) is diffused from the surface of the epitaxial layer (36), and is connected to the lower isolation region (35), thereby simultaneously forming the P well (38) and the isolation region (34). By separating the upper and lower sides in this manner, the region for forming the bipolar transistor ( 40 ) and the region for forming the MOS transistors ( 37 ) and ( 41 ) are electrically separated and the diffusion time is shortened. N ⁺ type buried layer (32)
Is suppressed in the upward direction to prevent deterioration of the breakdown voltage of the element.

Then, as shown in FIG. 2C, the epitaxial layer (36)
Silicon nitride film (Si ₃ N ₄ ) on oxide film (42) covering
Is deposited and selectively removed to remove the oxidation resistant mask (4
After forming 3), oxidation is performed under high temperature and high humidity conditions to form a thick field oxide film (44) for surface isolation.

Next, as shown in FIG. 2D, after removing the oxidation-resistant mask (43), a P-type base region (45) is formed using a well-known ion implantation method, and then an oxide film (42) on the surface is formed. Is removed to expose the epitaxial layer (36), and gate oxidation is performed to form a thin gate oxide film (46) on the surface of each element formation region.

Next, as shown in FIG. 2E, the gate electrodes (4) of the MOS transistors ( 37 ) and ( 41 ) are formed on the entire surface of the epitaxial layer (36).
7) The polycrystalline silicon layer (48) to be deposited is deposited, and the polycrystalline silicon layer (48) on the emitter region (49) and the collector contact region (50) of the bipolar transistor ( 40 ) is oxidized using a photoresist as a mask. The film (46) is removed.

Next, as shown in FIG. 2F, a ring lath film (51) is formed on the polycrystalline silicon layer (48) by a known method,
By introducing phosphorus (P) into the polycrystalline silicon layer (48), the resistance of the polycrystalline silicon layer (48) is reduced, and
Phosphorus (P) is also deposited on the surface of the base region (45) of the bipolar transistor ( 40 ) to diffuse and form an N ⁺ type emitter region (49) and a collector contact region (50).

Next, as shown in FIG. 2G, after removing the ring lath film (51), the polycrystalline silicon layer (48) into which phosphorus (P) is introduced.
Is selectively etched to form a gate electrode (47),
The P-channel MOS transistor ( 41 ) and the N-channel MOS transistor ( 37 ) are alternately exposed by the photoresist, and boron (B) and phosphorus (P) are sequentially formed using the respective gate electrodes (47) as a mask. The source / drain region (52) of the P-channel MOS transistor ( 41 ) and the source / drain region (53) of the N-channel MOS transistor ( 37 ) are formed by ion implantation, and the manufacturing process is completed.

(C) Problems to be Solved by the Invention In the above steps, when a silicon nitride film (Si ₃ N ₄ ) is used as an oxidation resistant mask (43), NH ₃ is reacted by Si ₃ N ₄ and H ₂ O.
₃ is formed, this NH ₃ reacts with Si to form Si ₃ N ₄ ,
For example, a phenomenon occurs in which the Si ₃ N ₄ (54) is formed in a black area in the oxide film (42) in FIG. 2C. This phenomenon is described, for example, in J. Electrochem, Soc, 123: P1117: 1976.

Further, even if the oxide film (42) is removed and the gate is oxidized as shown in FIG. 2D, Si ₃ N ₄ (54) shown in black remains, and a part (Si ₃ N ₄ ) of the gate oxide film (46) is left. (A region where (54) remains)), there is a problem that a region having a small film thickness is formed and a portion having a weak gate breakdown voltage is generated.

To this end, the gate oxide film (46) may be removed and a gate oxide film (dummy oxide film) may be formed again. However, the formation and removal of the oxide film causes a redistribution phenomenon of impurities, and in particular, a bipolar transistor. There is a problem that the predetermined characteristics of the type transistor change. It is considered that this is because impurities in the semiconductor substrate are diffused into the oxide film.

(D) Means for Solving the Problems In view of the above problems, the present application is to form the silicon nitride film (1) between the LOCOS oxide film (14) after forming the LOCOS oxide film.
3) and the underlying silicon oxide film (12) are removed, the exposed semiconductor substrate is thermally oxidized to form a dummy oxide film (16), and the silicon nitride film (16) corresponding to the MOS transistor region is removed. In addition, the above problem is solved by forming a gate oxide film (19) in the removed region after leaving a dummy oxide film corresponding to the bipolar transistor region.

Further, after the formation of the dummy oxide film (16), the base region in the bipolar transistor region is formed by ion implantation, and thereafter, the dummy oxide film (16) of the bipolar transistor region is left, and the MOS transistor region is formed. The problem is solved by forming the gate oxide film (19) after removing the dummy oxide film.

(E) Function Si ₃ N ₄ (15) described in the section of the problem to be solved by the invention is LOC
After forming OS oxide film (14), silicon nitride film (13)
And after removing the underlying silicon oxide film (12),
It is exposed as shown in FIG.

Then, when this exposed region is thermally oxidized (dummy oxidation),
As shown in FIG. 1E, the silicon under the Si ₃ N ₄ (15) is oxidized, and the Si ₃ N ₄ (15) is raised by the dummy oxide film (16).

Thus the dummy oxide film (1 raised the Si ₃ N ₄ (15)
6) is removed by a predetermined etching method, a dummy oxide film (1) is removed.
This Si ₃ N ₄ (15) is also removed together with 6).

However, if the dummy oxide film (16) is completely removed and a silicon oxide film is formed again, the impurity of boron as a diffusion source diffuses into the silicon oxide film. By removing the impurity in the MOS transistor region and removing it in the MOS transistor region, a change in the impurity distribution can be prevented, and a gate oxide film having a stable film thickness can be obtained.

On the other hand, a method of removing the dummy oxide film (16) as described above and then oxidizing the gate to form a base is also conceivable, but in this case, there is a step of applying the resist and putting it in a furnace for diffusion. The thickness of the gate oxide film changes. In the former method, the base is formed after the dummy oxidation, and thereafter, the dummy oxide film of the bipolar transistor is left.
Moreover, since the base is formed after dummy oxidation, MO
There is a dummy oxide film on the S-type transistor region, and therefore, there is little contamination of the MOS-type transistor region.

Since the gate oxide film is formed thereafter, the gate oxide film does not fluctuate due to the formation of the base.

In addition, since the remaining dummy oxide film covers the surface of the base region, the growth of the oxide film when the gate oxide film is formed is small, and the absorption of the base impurity into the oxide film can be suppressed as much as possible.

(F) Embodiment One embodiment of the present invention will be described below in detail with reference to FIGS. 1A to 1H.

First, as shown in FIG. 1A, an N ⁺ type buried layer (2) having a surface concentration of 10 ¹⁹ cm ^-3 with antimony (Sb) and a surface concentration of boron (B) are formed on the surface of a P type semiconductor substrate (1). A P ⁺ -type buried layer (3) of 10 ¹⁸ cm ^-3 and a lower isolation region (5) corresponding to the isolation region ( 4 ) are deposited, and a well-known vapor phase growth is performed on the semiconductor substrate (1). An N-type epitaxial layer (6) having an impurity concentration of 10 ¹⁵ cm ^-3 is laminated on the entire surface to a thickness of about 5 μm by the method.

Subsequently, as shown in FIG. 1B, the epitaxial layer (6)
After boron (B) forming a P-type well (8) of an N-channel MOS transistor ( 7 ) is ion-implanted on the surface, the P ⁺ -type upper isolation region (9) is diffused from the surface of the epitaxial layer (6). The P-type well (8) and the isolation region ( 4 ) are simultaneously formed by connecting with the lower isolation region (5).

This vertical separation electrically separates the region forming the bipolar transistor ( 10 ) from the region forming the MOS transistors ( 7 ) and ( 11 ), and the diffusion of the vertical separation is caused by diffusion. Because the time is short,
Re-diffusion upward of the N ⁺ type buried layer (2) is suppressed to prevent deterioration of the breakdown voltage of the element.

Next, as shown in FIG. 1C, a silicon oxide film (12) is coated on the epitaxial layer (6), and a silicon nitride film (13) is formed on the silicon oxide film (12). This silicon nitride film (13) is etched to form an oxidation resistant mask. Hereafter, silicon nitride film (13)
The underlying silicon oxide film (12) is used as an underlying silicon oxide film.

Then, LOCOS oxidation is further performed under high temperature and high humidity conditions to form a thick LOCOS oxide film (14) for surface isolation.

In this step, as described in the section of the problem to be solved by the invention, NH ₃ is formed by the reaction of Si ₃ N ₄ and H ₂ O, and this NH ₃
Reacts with Si to form black Si ₃ N ₄ (15) under the underlying silicon oxide film (12).

Next, as shown in FIG. 1D, the silicon nitride film (13)
And a step of removing the underlying silicon oxide film (12).

Therefore, as shown in the figure, the epitaxial layer (6) and the Si ₃ N ₄ (15) shown in black are exposed.

Here, the silicon nitride film (13) and the underlying silicon oxide film (12) are removed from the entire surface, but only the MOS transistor region may be etched in order to prevent a change in the impurity concentration of the substrate.

Next, as shown in FIG. 1E, the semiconductor substrate is subjected to dummy oxidation to form a dummy oxide film (16) in the exposed region.

Here, the dummy oxide film (16) is made of Si ₃ N ₄ shown in black.
This Si ₃ N ₄ is also formed below (15), is separated from the semiconductor substrate, and is raised by the dummy oxide film (16).

Subsequently, as shown in FIG. 1F, for example, a photoresist film (17) having an ion implantation inhibiting ability is formed, the photoresist film in a region corresponding to the base region (18) is removed, and a dummy oxidation is performed by a known ion implantation method. P through membrane (16)
A mold base region (18) is formed and diffused to a predetermined depth by heat treatment.

Here the ion implantation conditions are a dose of 10 ¹³ ~10 ¹⁴ cm ^-2, 30
~ 40 KeV.

Further, as shown in FIG. 1G, the silicon oxide film (16) in a region corresponding to the MOS transistors ( 7 ) and ( 11 )
(A film on which Si ₃ N ₄ (15) is raised) is etched using a known etching method.

Here, by etching this dummy oxide film (16),
The Si ₃ N ₄ (15) whose gate breakdown voltage has been reduced is also removed. Further, by leaving the dummy oxide film (16) corresponding to the bipolar transistor ( 10 ) as it is, the impurity concentration below the dummy oxide film (16) can be made constant.

This is because impurities are re-diffused into the dummy oxide film during thermal oxidation, and if the redistributed dummy oxide film is removed and a new silicon oxide film is formed by new thermal oxidation, the impurities are re-diffused. The impurity concentration is reduced, which adversely affects the characteristics of the bipolar transistor ( 10 ). This problem can be solved as described above.

Thereafter, the region exposed by this etching is subjected to gate oxidation to form a gate oxide film (19) on the surface of the MOS type transistors ( 7 ) and ( 11 ). Here, since the Si ₃ N ₄ (15) shown in black is removed, there is no variation in the film thickness due to the Si ₃ N ₄ (15), so that the gate oxide film (19) having excellent withstand voltage
Can be formed, and since there is no diffusion in the furnace when the base is formed, the fluctuation of the gate oxide film can be reduced.

Thereafter, non-doped polycrystalline silicon to be the gate electrodes (20) of the MOS transistors ( 7 ) and ( 11 ) is deposited on the semiconductor substrate, and the gate electrodes (20) are formed by a predetermined etching method.

In this case, the sheet resistance is about 20Ω / port, and is selectively removed by plasma etching.

Further, after applying a resist (21) having ion implantation blocking capability, a predetermined portion is opened, and an emitter region (22), a collector contact region (23), and a source / drain region (24) of an N-channel MOS transistor ( 7 ) are formed. ) Is simultaneously formed by ion implantation, and a P-channel type
Source / drain region of MOS transistor ( 11 ) (25)
Is formed by ion implantation.

Finally, a passivation film such as a ring lath is formed,
As shown in FIG. 1H, contact holes and electrodes (2
6), (27), (28), etc. are formed.

The features of the present invention in the above steps will be described. First, the first feature is that after forming the LOCOS oxide film (14), the silicon nitride film (13) between the LOCOS oxide films (14) is formed.
By removing the underlying silicon oxide film (12) and forming a dummy oxide film (16) in the re-exposed area, the Si ₃ N ₄ (15) shown in black is raised, and then the base is formed. This is that the Si ₃ N ₄ (15) can be removed together with the removal of the dummy oxide film (16) in the MOS transistor region.

The second feature is that since the dummy oxidation and the removal of the dummy oxide film are repeated between the above-described steps, only the MOS transistor region is processed and the bipolar transistor region is left as it is, whereby the bipolar transistor is removed. It is possible to keep the impurity distribution in the region constant.

On the other hand, the bipolar transistor part is Si ₃ N ₄ (15)
Therefore, even if there is a thin portion of the dummy oxide film (16),
Since a passivation film such as a ring lath is formed before the electrodes are formed, a sufficient withstand voltage can be secured.

(G) Effect of the Invention As described above, Si ₃ N ₄ (15) which causes gate breakdown voltage is raised by the thermal oxidation method, and by removing this thermal oxide film (16), the Si ₃ N _{4 Since} (15) can also be removed, a gate oxide film can be formed satisfactorily and the gate breakdown voltage can be improved.

Also, at this time, by performing this process only on the MOS transistor region, the fluctuation of the impurity in the bipolar transistor region can be suppressed, and the change in characteristics can be prevented.

[Brief description of the drawings]

1A to 1H are cross-sectional views of a semiconductor integrated circuit illustrating an embodiment of the present invention, and FIGS. 2A to 2G are semiconductor integrated circuits illustrating a method of manufacturing a conventional semiconductor integrated circuit. FIG. (1) ... semiconductor substrate, (2), (3) ... buried layer,
( 4 ) ... isolation region, (6) ... epitaxial layer,
( 7 ) ... N-channel MOS transistor, ( 10 ) ...
… Bipolar transistor, ( 11 ) …… P-channel
MOS type transistor, (12) ... silicon oxide film, (1
3) Silicon nitride film, (14) LOCOS oxide film, (1
_{5) ...... Si 3 N 4,} (16) ...... dummy oxide film, (19) ... gate oxide film, (20) .... gate electrode.

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor integrated circuit in which a MOS transistor and a bipolar transistor are formed on the same semiconductor substrate, comprising: forming an underlying silicon oxide film on the semiconductor substrate; Forming a silicon nitride film on the film; forming an LOCOS oxide film using the silicon nitride film as an oxidation-resistant mask; removing the silicon nitride film and underlying silicon oxide film to form a LOCOS oxide film; Exposing the Si3N4 film formed in the vicinity, forming a dummy oxide film so as to form an oxide film again under the Si3N4 film by thermal oxidation again, and a dummy oxide film in the bipolar transistor region. And leave
The dummy oxide film in the region corresponding to the MOS transistor
A method for manufacturing a semiconductor integrated circuit, comprising: at least a step of removing together with the Si3N4 film; and a step of forming a gate oxide film in the removed area. A step of forming a base region by ion implantation in a region corresponding to the bipolar transistor region after the formation of the dummy oxide film; and a step of forming a MOS transistor region by leaving a dummy oxide film in the bipolar transistor region. Forming a gate oxide film after removing the dummy oxide film. 3. The method according to claim 1, further comprising the step of, after forming said gate oxide film, simultaneously forming a source / drain region of a reverse conductive channel type MOS transistor and an emitter region and a collector contact region of said bipolar transistor. ).