JP2511956B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of manufacturing a transistor element suitable for high speed and high integration of a bipolar type integrated circuit.

2. Description of the Related Art Recently, in the field of bipolar integrated circuits, various new technologies have been proposed for improving the switching speed of transistors. The major improvements made by these technologies are to make the internal base of a vertical NPN transistor shallow to form a narrow width in the depth direction of the base to shorten the transit time of electrons in the base. On the other hand, there is a method of lowering the resistance of this parasitic base in order to reduce the delay time due to the coupling between the parasitic base resistance and the base input capacitance that enter in series. As a method of reducing the resistance of the parasitic base, a so-called graft base method is known, in which a parasitic base region for extracting an electrode is formed by diffusion with impurities having a higher concentration than the internal base, and this is used as an external base. Has been. For example, the 1984 International Electron Device Meeting Digest of Technical Papers (INTERNATIONAL EL
ECTRON DEVICE MEETING DIGEST OF TECHNICAL PAPERS P
P.753-756), in the formation of vertical NPN transistor,
A structure is disclosed in which an external base formed under the thermal oxide film and an internal base formed from an opening of the thermal oxide film are connected in the vicinity of an end of the thermal oxide film.

Problems to be Solved by the Invention In order to increase the speed of a bipolar transistor, it is necessary to simultaneously form a shallow internal base and a low resistance external base. As the inner base is made shallower, the layered resistance of the inner base is likely to increase, and in order to reduce this effect, a method of narrowing the width of the emitter is usually adopted. However, in this case, if the high-concentration impurity concentration of the external base is increased, the impurities infiltrate into the internal base, changing the impurity profile of the internal base, and reducing the current amplification factor in terms of direct current,
AC causes a bad phenomenon such as an increase in the base transit time of electrons. The only way to suppress this phenomenon is to reduce the impurity concentration of the external base and reduce the lateral diffusion of the base. According to this method, the penetration of the external base is suppressed, but when the internal base is formed to have a very shallow depth of 150 nanometers, the following structural or manufacturing problems occur. That is, since the opening end formed by the beak-shaped end of the oxide film fluctuates unstable due to etching during the process, the connectivity itself between the external base and the internal base becomes unstable, and further, the connection is At worst, the effective base width is narrow due to the small lateral diffusion of the internal base under this beak, which causes a drawback that a punch-through leak current between the collector and the emitter is likely to occur. there were. For example, as shown in FIG. 3A, after forming an N type buried layer 102 on a P type silicon semiconductor substrate 100 and forming an N type epitaxial semiconductor layer 104, about 25 nanometers The dose is 2 using the silicon nitride film pattern 110 of about 100 nanometer thickness formed on the thin thermal oxide film 108 of the meter as a mask.
Ion implantation of × 10 ¹⁵ / cm ² of boron was performed to form a P-type semiconductor region 116 to be an external base. Further, as shown in FIG. 3 (b), an oxidation resistant silicon nitride film pattern 11 is formed.
Thermal oxidation is performed using 0 as a mask to form an oxide film 122 having a thickness of about 200 nanometers, and then the silicon nitride film pattern 110 and the oxide film 108 are removed to form an opening for an emitter.
A polycrystalline silicon film is deposited on the entire surface, a polycrystalline silicon film pattern 124 is formed by patterning, and further,
Boron with a dose amount of 2 × 10 ¹⁴ / cm ² is ion-implanted into the polycrystalline silicon film pattern 124, and a heat treatment is performed to obtain about 150 nanometers.
P-type semiconductor region 126 which becomes the active base at the depth of the meter
Was formed. Similarly, arsenic was ion-implanted into the polycrystalline silicon film pattern 124, and a heat treatment was performed to form an N-type semiconductor region 128 to be an emitter having a depth of about 50 nanometers. According to such a manufacturing method, the connectivity between the external base 116 and the internal base 126 may be different depending on the shape of the beak-shaped end of the oxide film pattern 122 as shown in FIG. 3B. It will be difficult. Therefore, there is a need for a novel transistor structure with good controllability and a method for manufacturing the same, which solves the problems in the structure and manufacturing caused by the instability of the connection between the external base and the internal base.

Means for Solving the Problems In order to solve such problems, the present invention includes a step of forming an oxidation resistant mask material pattern on a semiconductor layer of the first conductivity type, and at least the oxidation resistant mask material pattern. Forming a second conductive type first semiconductor region on the surface of the semiconductor layer immediately below the mask material pattern and immediately below its end; and forming a second conductive type second semiconductor region around the oxidation resistant mask material pattern. A step of forming a semiconductor region; a step of forming an oxide film having a beak-shaped end portion around the mask material pattern by an oxidation method using the oxidation resistant mask material pattern as a mask; Removing the mask material pattern to form an opening of the oxide film pattern having the beak-shaped end portion; forming a third semiconductor region of the second conductivity type through the opening; In the semiconductor area First
And a step of forming a conductive fourth semiconductor region, wherein the second semiconductor region and the third semiconductor region are connected via the first semiconductor region. A manufacturing method is provided.

Operation When the means according to the present invention is applied to the emitter-base junction of a bipolar transistor, the following operation occurs.

The second conductive type first semiconductor region serving as the intermediate base can be formed without using mask alignment, and the size thereof is almost self-aligned from the end of the insulating film (the insulating film forming the opening of the emitter. It has the advantage that it can be formed with the size of the beak. Further, the second semiconductor region serving as the external base and the third semiconductor region serving as the internal base are connected to each other immediately below the end portion of the opening of the insulating film. Since the impurity concentration or the total number of impurity atoms per unit area can be made smaller than that of the internal base, it was possible to prevent the impurity atoms of the external base from directly entering the internal base. Therefore, it was possible to prevent the occurrence of a bad phenomenon such as a decrease in the current amplification factor in terms of direct current and an increase in the base transit time of electrons in terms of alternating current.

Further, since the external base and the internal base are not directly connected to each other, the impurity profile of each can be optimized independently, so that the controllability of the diffusion of impurities is facilitated and the manufacturing yield is improved.

Embodiment A first embodiment in which the method of construction according to the present invention is applied to the emitter-base junction of a bipolar NPN transistor,
This will be described with reference to FIG.

As shown in FIG. 1, in the N-type epitaxial semiconductor layer 104 having the N-type buried layer 102 formed on the P-type silicon semiconductor substrate 100, the thermal oxide film 122 having a beak-shaped end portion is formed. The P-type semiconductor region 116 serving as an external base and the P-type semiconductor region 126 serving as an internal base formed in the opening formed by the oxide film are formed below the main portion of the oxide film in a beak-shaped oxide film. Connected directly via a P-type semiconductor region 118, which serves as an intermediate base, formed immediately below the end of the N-type semiconductor region, and serves as an emitter.
A polysilicon electrode 124 is formed on 128.

If a polysilicon electrode is used as a diffusion source for the internal base 126 and the emitter 128 as a method for forming such an emitter-base junction, the internal base depth is 150 nanometers, and the emitter depth is 50 nanometers. An excellent structure can be realized, and since the internal base and the external base are connected via the intermediate base having a relatively low impurity concentration, the high concentration impurities of the external base penetrate into the internal base, and It was possible to prevent changing the impurity profile and stabilize the connectivity of the base.

Next, a second embodiment in which the method of the present invention is applied to a method for manufacturing a bipolar NPN transistor will be described with reference to FIG.

As shown in FIG. 2A, a P-type silicon semiconductor substrate 10
After forming the N type buried layer 102 on the 0, the N type epitaxial semiconductor layer 104 was formed. P-type element isolation region 1
After forming 06, a thin thermal oxide film 108 of about 25 nanometers is formed.
Thermal oxidation was performed using the silicon nitride films 110A and 110B having a thickness of about 100 nanometers formed on the A and 108B as masks to form a thick oxide film 112 having a thickness of about 600 nanometers.

As shown in FIG. 2B, a resist pattern 114 is formed by a photomask process, and using this as a mask, a silicon nitride film pattern 110C having a width of about 1 micron is left on a portion where an emitter is to be formed. Using the pattern 114 as a mask, boron having a dose of 2 × 10 ¹⁵ / cm ² is ion-implanted to form a P-type semiconductor region 11 serving as an external base.
Formed 6.

As shown in FIG. 2 (c), after removing the resist pattern 114, the N type semiconductor region 12 is formed by phosphorus ion implantation.
0 is selectively formed, and further, boron with a dose amount of 5 × 10 ¹² / cm ² is ion-implanted through the silicon nitride film pattern 110C so as to have a peak concentration at the silicon interface, and a P-type shallow semiconductor serving as an intermediate base is formed. Region 118 was formed.

As shown in FIG. 2D, thermal oxidation is performed using the oxidation resistant silicon nitride film pattern 110C as a mask, and the thickness is about 20.
An oxide film 122 of 0 nanometer was formed.

As shown in FIG. 2 (e), the silicon nitride film pattern 110 is formed.
After removing C and the oxide film 108A to form an emitter opening, a polycrystalline silicon film is deposited on the entire surface, and this is patterned to form polycrystalline silicon film patterns 124A and 124B. The polycrystalline silicon film pattern 124A was ion-implanted at 2 × 10 ¹⁴ / cm ² , and a heat treatment was performed to form a P-type semiconductor region 126 to be an active base having a depth of about 150 nanometers. Thereafter, similarly, arsenic was ion-implanted into the polycrystalline silicon film pattern 124A, and a heat treatment was performed to form an N-type semiconductor region 128 to be an emitter having a depth of about 50 nanometers.

As shown in FIG. 2 (f), after depositing a silicon oxide film 130 on the entire surface, aluminum electrodes 132A, 132B, 132C and the like were formed according to a usual manufacturing method.

As described above, according to the method of the present invention, a vertical NPN transistor is formed, the base width of which is about 100 nm and an active element portion (internal base) structure excellent in high speed is obtained. Since the external base and the internal base were well connected through the thin and shallow intermediate base, it was possible to prevent the generation of the leak current between the collector and the emitter under the beak-shaped oxide film. .

If the method of the present invention is used, the emitter of the bipolar element can be regarded as a gate, and the external bases on both sides of this gate can be regarded as a source and a drain, so that the internal base functions as a junction field effect transistor. it can. Thus, the method of the present invention can be applied to various semiconductor devices as well as bipolar devices.

EFFECTS OF THE INVENTION According to the manufacturing method of the present invention, an active element portion excellent in high speed and high integration can be manufactured with good controllability.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a bipolar NPN transistor according to the present invention, FIG. 2 is a sectional view of a series of steps showing a method for manufacturing a bipolar NPN transistor according to the method of the present invention, and FIG. 3 is a bipolar NPN according to a conventional method. 6A and 6B are cross-sectional views illustrating a structure of a transistor and a problem in manufacturing the transistor. 100 ... P-type semiconductor substrate, 102 ... N-type buried layer, 104
... N-type semiconductor layer, 106, 116, 118, 126 ... P-type semiconductor region, 120, 128 ... N-type semiconductor region, 108, 112, 122, 130
...... Silicon oxide film, 110 …… Silicon nitride film, 124 ……
Polycrystalline silicon film, 114 ... Resist, 132 ... Aluminum electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-60-223158 (JP, A) JP-A-60-34063 (JP, A) JP-A-60-113968 (JP, A)

Claims (4)

(57) [Claims] 1. A step of forming an oxidation-resistant mask material pattern on a semiconductor layer of the first conductivity type, and a second step on at least the surface of the semiconductor layer immediately below the oxidation-resistant mask material pattern and immediately below the end portion thereof. Forming a conductive type first semiconductor region, forming a second conductive type second semiconductor region around the oxidation resistant mask material pattern, and forming the oxidation resistant mask material pattern. A step of forming an oxide film having a beak-shaped end portion around the mask material pattern by a oxidization method as a mask, and removing the oxidation-resistant mask material pattern to perform oxidation having the beak-shaped end portion. Forming an opening of the film pattern, forming a third semiconductor region of the second conductivity type through the opening, and forming a fourth semiconductor region of the first conductivity type in the third semiconductor region. And the process The method of manufacturing a semiconductor device according to claim a serial second semiconductor region and said third semiconductor region be connected through the first semiconductor region. 2. A first semiconductor region is used as an intermediate base, a second semiconductor region is used as an outer base, a third semiconductor region is used as an inner base, and a fourth semiconductor region is used as an emitter. A method of manufacturing a semiconductor device according to item 1. 3. The first semiconductor region according to claim 1, wherein the total number of impurity atoms per unit area is smaller than that of the second conductivity type third semiconductor region. 2. A method for manufacturing a semiconductor device according to item 2. 4. A third semiconductor region of the second conductivity type and a first semiconductor region.
The fourth semiconductor region of conductivity type is formed by using the same polycrystalline semiconductor as a diffusion source.
Item 2. A method for manufacturing a semiconductor device according to item 2 or 3.