JPS60113968A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60113968A JPS60113968A JP22161083A JP22161083A JPS60113968A JP S60113968 A JPS60113968 A JP S60113968A JP 22161083 A JP22161083 A JP 22161083A JP 22161083 A JP22161083 A JP 22161083A JP S60113968 A JPS60113968 A JP S60113968A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- emitter
- silicon
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000002955 isolation Methods 0.000 claims abstract description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 abstract description 31
- 238000000034 method Methods 0.000 abstract description 14
- 150000004767 nitrides Chemical class 0.000 abstract description 7
- 239000002019 doping agent Substances 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 230000010354 integration Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 241000282806 Rhinoceros Species 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001447 compensatory effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、特にウォールド
エミッタ構造のバイポーラ型トランジスタの製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a bipolar transistor having a walled emitter structure.
半導体装置は、近年ますます高集積化、高密度化が進ん
でおり、特にバイポーラ型ｉ・ランジスタに於いては、
その高速化が要求され、素子サイズの縮少化による接合
容量の低減化の必要性が言われている。その実現の一手
段として、素子間の絶縁分離用の酸化膜をマスクとして
拡散を行ないエミッターを形成する。ウォールドエミッ
タ構造が提晶されている。この方法が実現可能であれば
、絶縁分離用の選択酸化膜とエミッタ間の距離をとる必
要がなくなる為、素子面積を小さくでき、それに伴なっ
て、コレクターと基板間の容量或いは、コレクターとベ
ース間の容量を下げることができ、高速化、及び高集積
化が期待される。Semiconductor devices have become increasingly highly integrated and densely packed in recent years, especially in bipolar type i-transistors.
There is a demand for higher speeds, and there is a need to reduce junction capacitance by reducing element size. One way to achieve this is to perform diffusion using an oxide film for isolation between elements as a mask to form an emitter. The walled emitter structure is crystallized. If this method can be realized, there will be no need to maintain a distance between the selective oxide film for isolation and the emitter, so the device area can be reduced, and the capacitance between the collector and the substrate or the collector and base It is possible to reduce the capacity between devices, and is expected to achieve higher speed and higher integration.
しかしながら、従来ウォールドエミッタ法で工ミッタを
形成すると（エミッタ拡散窓の開孔の際に、分離酸化膜
のエツジが後退してしまい）分離酸化膜の側面付近でベ
ース幅が減少し、エミッタとコレクタ間が短絡してしま
う、それを防ぐＫは分離酸化膜のエツジ近傍にベースと
同型の不純物層を、補償的に形成しておく必要があった
。しかしこの方法では、不純物拡散層を選択的に形成す
る工程が必要となり、又このマスクの位置が選択酸化膜
の位置に対しずれると、補償不純物拡散層が必要１メ上
にコレクタ或いはエミッタと接っすることになり、エミ
ッタとペース間或いはコレクタとベース間の接合客数が
増えるという問題があった。However, when an emitter is formed using the conventional walled emitter method (the edge of the isolation oxide film recedes when the emitter diffusion window is opened), the base width decreases near the sides of the isolation oxide film, and the emitter and collector To prevent short-circuiting between the two electrodes, it was necessary to form an impurity layer of the same type as the base near the edge of the isolation oxide film in a compensatory manner. However, this method requires a step to selectively form the impurity diffusion layer, and if the position of this mask deviates from the position of the selective oxide film, the compensating impurity diffusion layer may be formed one layer above the collector or emitter. As a result, there is a problem in that the number of connections between the emitter and the pace or between the collector and the base increases.
本発明の目的は、前記の欠点を除き、ウォールド・エミ
ッタ構造のトランジスタを実現し、高速で高集積密度化
の期待できる半導体装置の製造方法を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, realize a transistor with a walled emitter structure, and provide a method for manufacturing a semiconductor device that can be expected to achieve high speed and high integration density.
本発明の半導体装置の製造方法は、−導電型シリ−賜ン
基板上に第１のシリコン酸化）漠を形成する工程と、該
第１のシリコン酸化膜上にシリコン窒化膜な形成する工
程と、写真食刻法により選択的に前記シリコン窒化膜を
除去する工程と、前記シリコン窒化膜をマスクとしてＭ
ｔｌ記第１のシリコン酸化膜をオーバーエツチングし、
前記シリコン窒化膜のひさしを設ける工程と、不純物を
含有する多結晶シリコン膜を気相成長させ、該多結晶シ
リコン膜を異方性エツチングにより除去し、前記シリコ
ン窒化膜のυ・さしの１のみに前記多結晶シリコン膜を
残す工程と、非酸化性雰囲気で熱処理を施し、前記多結
晶シリコン瞑に含まれる不純物を、前記シリコン基板内
に拡散させる工程と、前記シリコン望化ｊ須をマスクと
して選択酸化し素子分離酸化膜を形成する工程を含むこ
とをＢ１敵とする。The method for manufacturing a semiconductor device of the present invention includes: - forming a first silicon oxide film on a conductive type silicon substrate; and forming a silicon nitride film on the first silicon oxide film. , a step of selectively removing the silicon nitride film by photolithography, and a step of removing the silicon nitride film using the silicon nitride film as a mask.
Over-etching the first silicon oxide film,
The step of providing a canopy of the silicon nitride film, growing a polycrystalline silicon film containing impurities in a vapor phase, removing the polycrystalline silicon film by anisotropic etching, a step of leaving the polycrystalline silicon film only on the substrate; a step of performing heat treatment in a non-oxidizing atmosphere to diffuse impurities contained in the polycrystalline silicon film into the silicon substrate; and a step of masking the silicon substrate. B1 includes a step of selectively oxidizing and forming an element isolation oxide film.
本発明によれば、分離酸化膜のエツチング近所にベース
と同じ型の不純物拡散Ｊ鋤が、分離酸化膜のエツジの位
置に対し自己整合的に形成され、更に分離酸化膜のエッ
ヂ部分では、酸化膜々厚が従来のものに比べ厚くなって
いる。従ってエミッタ拡散窓の開孔の際の酸化膜のエツ
ジの陵退量を低減でき、しかも分離酸化膜の側壁伺近（
では補償ベース層が形成されている為、従来問題となっ
ていた分離酸化膜エッヂ付近でのベース幅減少によるコ
レクタ・エミッタ間に短絡を防ぐことができる。According to the present invention, an impurity diffusion J-plow of the same type as the base is formed in the vicinity of the etching of the isolation oxide film in a self-aligned manner with respect to the edge position of the isolation oxide film. The film thickness is thicker than the conventional one. Therefore, it is possible to reduce the amount of receding of the edge of the oxide film when opening the emitter diffusion window.
Since a compensating base layer is formed in this device, it is possible to prevent a short circuit between the collector and emitter due to a decrease in the base width near the edge of the isolation oxide film, which has been a problem in the past.
この様に本発明法で形成したトランジスタを集積回路に
組み込むことにより高速で、高集積密度の半導体装置が
得られる。As described above, by incorporating the transistor formed by the method of the present invention into an integrated circuit, a semiconductor device with high speed and high integration density can be obtained.
次に従来技術と比較しながら、本発明の詳細な説明する
。Next, the present invention will be explained in detail while comparing it with the prior art.
第１図から第３図までは、分離酸化膜のエツジ付近に補
償ベース拡散層を設けずにウォールド・エミッタを形成
した例を示すものであり、第４図は、従来技術で補償ベ
ース拡散層を設けた状態を示している。第５図から第１
１図までは、本発明法を用いて、ウォールド・エミッタ
構造のトランジスタを実現した第１の実施例を示すもの
であり第１２図と第１３図は、第２の実施例を示１′も
のである。1 to 3 show an example in which a walled emitter is formed without providing a compensation base diffusion layer near the edge of the isolation oxide film, and FIG. This shows the state in which the Figure 5 to 1
1 to 1 show a first embodiment in which a transistor with a walled emitter structure was realized using the method of the present invention, and FIGS. 12 and 13 show a second embodiment. It is.
第１図は、素子分＠酸化を行ない、更に＃化膜を通して
イオン注入を行ない、ベース層（１０３）を形成したと
ころを示す断面図である。次にシリコ／酸化膜をエツチ
ングし、エミッタ拡散窓用の開孔を設け、不純物ドープ
された多結晶シリコンを拡散源として、エミッタ拡散層
を形成した状態を示す断面図が第２図である。又、分離
酸化膜（２０２）のエツジ部分を拡大したのが鐙：３図
である。第３図かられかる様に、分１ｌｉＩＩ酸化膜の
側壁付近では、ベース幅が狭くなっており、それに伴な
いコレクタ・エミッタ間の耐圧の減少あるいは短縮が生
じてしまう、そこでウォールド・エミッタを実現するに
は、分離酸化膜の側壁付近に補償ベース拡散層を設ける
必要がある。しかしその補償拡散層を従来法で形成する
には、第４図［Ａ）Ｋ示す様に、写真食刻法等で、分離
酸化膜のエツジ部分のみが露出しているマスクを設は負
性ベース形成の際より、加速エネルギーあるいは、ドー
ズ量を増加して、イオン注入を行ない、補償拡散層を形
成する方法が考えられるが、この方法だと、第４図ｆｂ
）に示す様に、補償ベース拡散層の位置が、分離酸化膜
に対しズレることがあり、極端なら合には、補償ベース
拡散層が形成されないことかあるこれを防ぐ為にマージ
ンをとると、真性ベースより高濃度は補償ベース拡散層
の領域が増えてし゛よい、その結果コレクタベース間、
あるいは、エミッタ・ベース間の答桁が増大し高速化の
妨げと／Ｌる。それに対し本発明の第１の実施例では、
まず。FIG. 1 is a cross-sectional view showing the state in which a base layer (103) is formed by performing elemental oxidation and further performing ion implantation through the # oxide film. Next, the silicon/oxide film is etched, an opening for an emitter diffusion window is formed, and an emitter diffusion layer is formed using impurity-doped polycrystalline silicon as a diffusion source. FIG. 2 is a cross-sectional view showing the state in which an emitter diffusion layer is formed. Further, Figure 3 shows an enlarged view of the edge portion of the isolation oxide film (202). As can be seen from Figure 3, the base width becomes narrow near the sidewalls of the 1liII oxide film, and as a result, the withstand voltage between the collector and emitter decreases or is shortened.Therefore, a walled emitter is realized. To achieve this, it is necessary to provide a compensation base diffusion layer near the sidewalls of the isolation oxide film. However, in order to form the compensation diffusion layer using the conventional method, as shown in FIG. A possible method is to perform ion implantation with increased acceleration energy or dose compared to when forming the base to form a compensation diffusion layer, but if this method is used,
), the position of the compensation base diffusion layer may be misaligned with respect to the isolation oxide film, and in extreme cases, the compensation base diffusion layer may not be formed.If a margin is taken to prevent this, Higher concentrations than the intrinsic base may increase the area of the compensation base diffusion layer, resulting in a collector-base gap,
Alternatively, the number of response digits between the emitter and the base increases, which hinders speeding up. In contrast, in the first embodiment of the present invention,
first.
第５図にその断面を示す様て、シリコン基板（５０１）
上に第１のシリコンＲご化膜（５０２）とシリコン窒化
膜（５０３）を形成する。次に、フォトレジストをマス
クとして、前記シリコン窒化膜を選択的に除去し、更Ｖ
Ｃ前記第１のシリコン酸化膜をオーバエッチし、前記シ
リコン窒化膜のひさしを設け、更に露出したシリコン基
板上に８α１のシリコン酸化膜に比べ充分薄い第２のシ
リコン酸化膜を形成する。その状態な示すのが第６図で
ある。As shown in FIG. 5, a silicon substrate (501)
A first silicon R oxide film (502) and a silicon nitride film (503) are formed thereon. Next, using the photoresist as a mask, the silicon nitride film is selectively removed, and further V.
C: Over-etch the first silicon oxide film to provide an overhang of the silicon nitride film, and further form a second silicon oxide film that is sufficiently thinner than the 8α1 silicon oxide film on the exposed silicon substrate. FIG. 6 shows this state.
この第２のシリコン酸化膜ハ故で多結晶シリコン膜の異
方性エツチングを行う際にシリコン基板がアタックされ
ない様にする為のストッパーとなる。This second silicon oxide film serves as a stopper to prevent the silicon substrate from being attacked during anisotropic etching of the polycrystalline silicon film.
次ニ形成スヘきトランジスタのベースノド−バントと同
型の不純物を含む多結晶シリコン膜を気相成長させ異方
性エツチングにより、前記多結晶シリコンを前記窒化膜
のひさしの下のみに残し、それ以外の多結晶シリコンを
全て除去する。次に非酸化性の雰囲気で熱処理を施し、
前記多結晶シリコンから市ｈピ第２のシリコン酸化膜を
逃して、シリコン基板へ、前記多結晶シリコン中の不純
物を拡散する、その状態を示す１１Ｍ図が第７しＩであ
る。Next, a polycrystalline silicon film containing the same type of impurity as the base dopant of the transistor is grown in a vapor phase, and anisotropic etching is performed to leave the polycrystalline silicon only under the nitride film and to Remove all polycrystalline silicon. Next, heat treatment is performed in a non-oxidizing atmosphere,
Figure 11M shows the state in which the second silicon oxide film is released from the polycrystalline silicon and the impurities in the polycrystalline silicon are diffused into the silicon substrate.
更に前記シリコン窒化Ｂ４（６ｏ３）をマスクとして、
絶縁分離Ｊｒｉの酸化ｊｊ史（８（１４）を形成前７．
）（第８賂り次に第９図に示す様にベース層（９０６）
をイオン注入で形成し、史にウォールド・エミッタの開
孔を設け、エミッタ形成用の不純・籾を含む多結晶シリ
コンを付は多結晶シリコンからの拡散でエミッタを形成
する（第１０図）。以上の方法でウォールド・エミッタ
産のトランジスタケ作製すると、第１０図Ｇτ拡大断面
図を示した様に、絶縁分離酸化膜の側壁部分には、負性
ベースの拡散ノ脅９外に、前記多結晶シリコン７Ｊ−ら
の拡散によって形成された補償ベース拡散層があり、か
つ、絶縁分離酸化膜のエツジ付近の酸化膜々厚か従来よ
り厚い為、エミッタ開孔の際の酸化ｊ莫のエツジの後退
が少ない。従って、分離欧化膜の側壁付近でのエレクタ
とエミッタ間の耐圧の劣化のない良好なトランジスタ特
性が期待される。Furthermore, using the silicon nitride B4 (6o3) as a mask,
7. Before forming oxidation jj history (8(14)) of insulation isolation Jri.
) (8th layer) Next, as shown in Figure 9, the base layer (906)
is formed by ion implantation, an opening for a walled emitter is formed, polycrystalline silicon containing impurities and grains for emitter formation is added, and an emitter is formed by diffusion from the polycrystalline silicon (FIG. 10). When a walled emitter transistor is fabricated using the above method, as shown in the enlarged cross-sectional view of Gτ in FIG. There is a compensating base diffusion layer formed by the diffusion of crystalline silicon 7J- et al., and the oxide film near the edge of the insulating isolation oxide film is thicker than before, so the edge of the oxidation layer during emitter opening is Less setbacks. Therefore, good transistor characteristics are expected without deterioration of breakdown voltage between the erector and emitter near the sidewalls of the separated European film.
以上が本発明の第１の実施例であるが、第１の実施例に
於いて分離酸化のマスクの窒化膜の周辺にひさしを設け
た後に第２のシリコン酸化膜を形成しているが、本発明
の第２の実施例として、該第２のシリコン酸化膜を形成
せずにベースと同型のドーパントを含む多結晶シリコン
膜を気相成長させ、異方性エツチングを行なって、前記
窒化膜のひさしの下のみに多結晶シリコンを残し、その
際に第１２図に示す様にシリコン基板もエツチングし、
非酸化性雰囲気での熱処理、史には、分離酸化を行なう
ことによって、本発明の主目的である補償ベース拡散層
を形成すると伴に素子形成面と、分離酸化膜表面がほぼ
同一の高さとなる様な構造を実現できる。該構造はトラ
ンジスタ形成後の配線工程にとっては有利である。特に
配線構造が多層となったり、配線間隔が縮少された際に
、配線のステップカバレジの改善にとり効果的である。The above is the first embodiment of the present invention. In the first embodiment, the second silicon oxide film is formed after providing an eaves around the nitride film of the isolation oxidation mask. As a second embodiment of the present invention, a polycrystalline silicon film containing a dopant of the same type as the base is grown in a vapor phase without forming the second silicon oxide film, and anisotropic etching is performed to remove the nitride film. The polycrystalline silicon was left only under the eaves of the wafer, and at the same time the silicon substrate was also etched as shown in Figure 12.
In the history of heat treatment in a non-oxidizing atmosphere, separation oxidation is performed to form a compensation base diffusion layer, which is the main purpose of the present invention, and to make the element formation surface and the separation oxide film surface almost at the same height. Various structures can be realized. This structure is advantageous for the wiring process after transistor formation. This is particularly effective in improving step coverage of wiring when the wiring structure is multilayered or the wiring spacing is reduced.
以上、実施例を用いて本発明の説明を行なった。The present invention has been explained above using Examples.
が、本発明の主える所は、選択酸化のマスクとなる窒化
膜の周辺にひさしを設け、前記ひさしの下に不純物を含
む多結晶シリコンを有した状態で非酸化性の熱処理を行
ない、更に絶縁分離酸化を行なうことによって、絶縁分
離酸化膜の周辺近傍に自己整合的に、ベースと同じ型の
不純物拡散層を設けることによって良好な特性を有する
ウォールド・エミッタ構造のトランジスタを実現し、又
該ウォールド・エミッタ構造のトランジスタを用いるこ
とにより半導体装置の高速化と高集積化をはかることに
ある。However, the main feature of the present invention is to provide an eaves around the nitride film that serves as a mask for selective oxidation, perform non-oxidizing heat treatment with polycrystalline silicon containing impurities under the eaves, and further By performing insulation isolation oxidation, a transistor with a walled emitter structure having good characteristics can be realized by providing an impurity diffusion layer of the same type as the base in a self-aligned manner near the periphery of the insulation isolation oxide film. The purpose of this invention is to increase the speed and integration of semiconductor devices by using transistors with a walled emitter structure.
以上の様に、従来法でウォールド・エミッタ型のトラン
ジスタを作製する場合、補償ベース拡散層と、分離酸化
膜のエツジとの位置ずれを考慮すると、補償ベース拡散
層領域を広くとらなければならス、その為に、エミッタ
・ベース間ベースとコレクタ間での接合容量が増大して
しまうと言う問題があった。これに対し、本発明法でウ
オールド・エミッタ構造のトランジスタを実現すれば、
絶縁分離酸化膜のエツジに対し自己整合的に必要最少限
の補償ベース拡散層を設けることができ、微少サイズの
良好な特性を有するトランジスタを実現することができ
、該トランジスタを組み込んだ半導体装置の重速化と高
集積化がはかれる。As described above, when manufacturing a walled emitter type transistor using the conventional method, the compensation base diffusion layer area must be widened in order to take into account the misalignment between the compensation base diffusion layer and the edge of the isolation oxide film. Therefore, there is a problem in that the junction capacitance between the emitter and the base and between the base and the collector increases. On the other hand, if a wall emitter structure transistor is realized using the method of the present invention,
The minimum necessary compensation base diffusion layer can be provided in a self-aligned manner to the edge of the insulating isolation oxide film, making it possible to realize a micro-sized transistor with good characteristics, and improving the performance of semiconductor devices incorporating the transistor. Faster speeds and higher integration are being achieved.
第１図から第３図までは、補償ベース拡散層を設けずに
、ウォールド・エミッタを形成した一例を示す断面図で
あり、第４図は、従来技術を用い補償ベース拡散層を設
け、ウォールド・エミッタを形成した一例を示す断面図
であり、第５図から第１１図は、本発明法を用いてウォ
ールド・エミッタ構造のトランジスタを実現した第１の
実施例を示す断面図であり、第１２図と第１３図は第２
の実施例を示す断面図である。
同、図に於いて、
１０１．５０１．１２０１・・・・・・シリコン基板、
１０２゜２０２、８０４．１００４．１３０４ ・・・
・・・素子分離酸化膜、１０３．２０３，４０３，９０
６．１００６・・・・・・・真性ペース拡散層、４０５
，７０５，８０５，１００５，１３０５・・・・・・補
償ベース拡散層、２０４，９０６．１００７・・・・・
・エミッタ拡散層、２０５，７０４．１００８・・・・
・・不純物を含む多結晶シリコン、４０９・・・・・・
レジス）、５０２゜６００２．６０４・・・・・・シリ
コン酸化膜、５０３，６０３・・・・・・シリコン窒化
膜。
第１図
究２図
第３起
４ρδ
尾４ 図
元、！５図
元乙図
＼
ＹＪ７図 ７θみ
筋６図
８ρ汐
箭ｑ胆
犀／ρ図
党Ｎ起1 to 3 are cross-sectional views showing an example of forming a walled emitter without providing a compensation base diffusion layer, and FIG.・It is a cross-sectional view showing an example of forming an emitter, and FIGS. Figures 12 and 13 are the second
FIG. In the same figure, 101.501.1201...silicon substrate,
102°202, 804.1004.1304...
...Element isolation oxide film, 103.203,403,90
6.1006...Intrinsic pace diffusion layer, 405
, 705, 805, 1005, 1305...Compensation base diffusion layer, 204,906.1007...
・Emitter diffusion layer, 205,704.1008...
...Polycrystalline silicon containing impurities, 409...
502°6002.604...Silicon oxide film, 503,603...Silicon nitride film. Figure 1 Study 2 Figure 3 Origin 4 ρδ Tail 4 Figure origin,! Figure 5 Genotsu Figure ＼ YJ7 Figure 7 θ Mizure 6 Figure 8 ρ Shioken q Gall Rhinoceros / ρ Figure Party N Origin
Claims (1)
形成する工程と該第１のシリコン酸化膜上にシリコン窒
化膜を形成する工程と写負食刻法により選択的に前記シ
リコン窒化膜を除去する工程と前記シリコン窒化膜をマ
スクとして前記第１のシリコン酸化膜をオーバーエツチ
ングし、前記シリコン窒化膜のひさしを設ける工程と第
２の導電型の不純物を含有する多結晶シリコン膜を前記
シリコン窒化膜のひさしの下のみに設ける工程と、非酸
化性雰囲気で熱処理を施し、前記多結晶シリコン膜に含
まれている不純物を前記シリコン基板内に拡散させる工
程と、前記シリコン窒化ｊ換をマスクとして選択化し、
素子分離酸化膜を形成する工程とを含むことを特徴とす
る半導体装置の製造方法。a step of forming a first silicon oxide film on a first silicon substrate; a step of forming a silicon nitride film on the first silicon oxide film; a step of removing the film; a step of over-etching the first silicon oxide film using the silicon nitride film as a mask to provide a canopy of the silicon nitride film; and a step of removing a polycrystalline silicon film containing impurities of a second conductivity type. a step of providing only under the eaves of the silicon nitride film; a step of performing heat treatment in a non-oxidizing atmosphere to diffuse impurities contained in the polycrystalline silicon film into the silicon substrate; and a step of dispersing the silicon nitride film. Select as a mask,
1. A method of manufacturing a semiconductor device, comprising the step of forming an element isolation oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22161083A JPS60113968A (en) | 1983-11-25 | 1983-11-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22161083A JPS60113968A (en) | 1983-11-25 | 1983-11-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60113968A true JPS60113968A (en) | 1985-06-20 |
Family
ID=16769444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22161083A Pending JPS60113968A (en) | 1983-11-25 | 1983-11-25 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60113968A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63261749A (en) * | 1987-04-17 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS63261748A (en) * | 1987-04-17 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
-
1983
- 1983-11-25 JP JP22161083A patent/JPS60113968A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63261749A (en) * | 1987-04-17 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS63261748A (en) * | 1987-04-17 | 1988-10-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
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